A high performance 0.35-μm 3.3-V BiCMOS technology optimized forproduct porting from a 0.6-μm 3.3-V BiCMOS technology

A 0.35-μm logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5-V version offers lower power and higher performance. A 3.3-V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6-μm 3.3-V BiCMOS process. A two-step design process for converting an existing production worthy 0.6-μm 3.3-V BiCMOS design to a 0.35-μm design is described. The silicon results are described     

2.5-V bipolar/CMOS circuits for 0.25-μm BiCMOS technology

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-μm BiCMOS technology. A pair of ECL/CMOS level converters with built-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance     

0.3-μm mixed analog/digital CMOS technology for low-voltageoperation

A 0.3-μm mixed analog/digital CMOS technology for low-voltage operation has been demonstrated, including a new MOSFET structure with laterally doped buried layer (LDB) and a double-polysilicon capacitor with low voltage coefficient. The LDB-structure MOSFET provides constant threshold voltage which is independent of channel length, high current drivability 10% over that of a conventional structure, and low junction capacitance which is less than 1/2 that of the conventional structure. The double-polysilicon capacitor achieves a voltage coefficient of 1/10 that of a conventional capacitor by introducing arsenic ion implantation to the top polysilicon plate and a Si₃N₄ capacitor-insulator, despite the insulator thickness being scaled down to oxide-equivalent 20 nm     

0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip     

Al/W/TiNx/TiSiy/Si barrier technology for1.0-μm contacts

A reliable contact diffusion barrier has been successfully formed by sintering in nitrogen a physically sputtered W/Ti bilayer. After a 650°C furnace anneal, a TiN_x/TiSi_y layer on contact with the silicon substrate was formed beneath the overlying W. No reaction between N₂ and W was observed. Arsenic implanted in the silicon substrate tended to retard the silicidation of titanium. Substantial redistribution of both B and As across the silicide layer was also observed during the contact sintering process. The 1.0-μ contacts fabricated with the Al/W/TiN_x/TiSi_y/Si barrier technology exhibited low and tightly distributed contact resistivities (less than 10^-6 Ω-cm²). No excessive leakage of the shallow junctions was observed even after thermally stressing the sample at 400°C for 8 h     

Advanced process device technology for 0.3-μm high-performancebipolar LSIs

A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3-μm bipolar LSIs. Fabricated 0.5-μm U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 μm², and they have an isolation width of 2.0 μm, a minimum emitter width of 0.2 μm, a maximum cutoff frequency (f_T) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3-μm bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f_T and base resistance is also discussed     

A high-performance 0.5-μm BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5-μm BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 μm² by creating self-aligned bit-sense and V_ss contacts. A WSi_x polycide emitter n-p-n transistor with an emitter area of 0.8×2.4 μm² provides a peak cutoff frequency (f_T) of 14 GHz with a collector-emitter breakdown voltage (BV_CFO) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f_T and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process     

High performance 3.3- and 5-V 0.5-μm CMOS technology for ASIC's

Process integration of two manufacturable high performance 0.5-μm CMOS technologies, one optimized for 5.0 V operation and the second optimized for 3.3-V operation, will be presented. The paper will emphasize poly-buffered LOGOS (PBL) isolation, MOS transistor design using conventional and statistical modeling to reduce circuit performance sensitivity to process fluctuations, gate oxide and gate length control, and hot carrier reliability of the transistors. Manufacturing and simulation data for both 3.3- and 5.0-V technologies will be shown. The nominal ring oscillator delay is measured for both 3.3- and 5.0-V technologies as 80 ps. Therefore, 5.0-V technology equivalent speed is achieved in the 3.3-V technology with a reduction in power consumption by a factor of 2.4     

0.15-μm RF CMOS technology compatible with logic CMOS forlow-voltage operation

Radio Frequency (RF) CMOS is expected to replace bipolar and GaAs MESFETs in RF front-end ICs for mobile telecommunications devices in the near future. In order for the RF CMOS to be popularly used in this application, compatibility of its process for high-speed logic CMOS and low supply voltage operation are important for low fabrication cost and low power consumption. In this paper, a 0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation is described. Because the fabrication process is the same as the high-speed logic CMOS, manufacturability of this technology is excellent. Some of the passive elements can be integrated without changing the process and others can be integrated with the addition of a few optional processes. Mixed RF and logic CMOS devices in a one-chip LSI can be realized with relatively low cost. Excellent high-frequency characteristics of small geometry silicon MOSFETs with low-power supply voltage are demonstrated. Cutoff frequency of 42 GHz of n-MOSFETs, which is almost the same level at that of general high-performance silicon bipolar transistors, was obtained. N-MOSFET's maintained enough high cutoff frequency of 32 GHz even at extremely low supply voltage of 0.5 V. Moreover, it was confirmed that degradation of minimum noise figure for deep submicron MOSFETs with 0.5 V operation is sufficiently small compared with 2.0 V operation. These excellent high-frequency characteristics of small geometry silicon MOSFETs under low-voltage operation are suitable for mobile telecommunications applications     

A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in0.25-μm SiGe BiCMOS

A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 × 16 b input data buffer are integrated in a 0.25-μm SiGe BiCMOS technology. The chip multiplexes 16 parallel input data streams each at 622 Mb/s into a 9.953-Gb/s serial output stream. The device also produces a 9.953-GHz output clock from a 622- or 155-MHz reference frequency. The on-board 10-GHz voltage-controlled oscillator (VCO) has a 10% tuning range allowing the chip to accommodate both the SONET/SDH data rate of 9.953 Gb/s and a forward error correction coding rate of 10.664 Gb/s. The 6 × 16 b input data buffer accommodates ±2.4 ns of parallel input data phase drift at 622 Mb/s. A delay-locked loop (DLL) in the input data buffer allows the support of multiple input clocking modes. Using a clock generator PLL bandwidth of 6 MHz, the 9.953-GHz output clock exhibits a generated jitter of less than 0.05 UI_P-P over a 50-kHz to 80-MHz bandwidth and jitter peaking of less than 0.05 dB     

A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μm CMOS

This paper describes the design of a two-step analog-to-digital converter (ADC). By using techniques such as improved switching and offset compensated amplifiers, the high-speed two-step architecture can be expanded toward high resolution. The ADC presented here achieves 9 ENOB with a spurious-free dynamic range of more than 72 dB, at a sample rate of 25 MSample/s. The ADC is realized in a 0.35-μm mainstream CMOS process without options such as double poly. It measures 0.66 mm ² and dissipates 195 mW from a 3.3-V power supply     

A 0.18-/spl mu/m RF SiGe BiCMOS technology with collector-epi-free double-poly self-aligned HBTs

This paper describes an RF SiGe BiCMOS technology based on a standard 0.18-/spl mu/m CMOS process. This technology has the following key points: 1) A double-poly self-aligned SiGe-HBT is produced by adding a four-mask process to the CMOS process flow-this HBT has an SiGe epitaxial base selectively grown on an epi-free collector; 2) two-step annealing of CMOS source/drain/gate activation is utilized to solve the thermal budget tradeoff between SiGe-HBTs and CMOS; and 3) a robust Ge profile design is studied to improve the thermal stability of the SiGe-base/Si-collector junction. This process yields 73-GHz f/sub T/, 61-GHz f/sub max/ SiGe HBTs without compromising 0.18-/spl mu/m p/sup +//n/sup +/ dual-gate CMOS characteristics.     

Integration of a double-polysilicon emitter-base self-alignedbipolar transistor into a 0.5-μm BiCMOS technology for fast 4-MbSRAM's

The single-polysilicon non-self-aligned bipolar transistor in a 0.5-μm BiCMOS technology has been converted into a double-polysilicon emitter-base self-aligned bipolar transistor with little increase in process complexity. Improved bipolar performance in the form of smaller base resistance and base-collector capacitance, larger knee current, higher peak cutoff frequency, and shorter ECL gate delay has been demonstrated. This technology will prove useful in meeting the requirements for higher performance in fast, high-density, SRAM circuits     

An 0.18-μm CMOS for mixed digital and analog applications withzero-volt-Vth epitaxial-channel MOSFETs

An 0.18-μm CMOS technology with multi-V_ths for mixed high-speed digital and RF-analog applications has been developed. The V _ths of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFET's with zero-volt-V_th for RF analog circuits. The zero-volt-V_th MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750°C, the film quality is as good as the bulk silicon because high pre-heating temperature (940°C for 30 s) is used in H₂ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g_m and f_T values than those of bulk cases. Furthermore, the g_m and f_T values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V_th will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications     

A 3-V 0.5-μm CMOS A/D audio processor for a microphone array

A 0.5-μm 3-V CMOS mixed-mode audio processor is presented. It is mainly composed of 11 low-noise input channels and a dedicated digital audio processor. Analog input signals are provided through an 11-microphone array. The chip size is about 50 mm², and the power dissipation is less than 100 mW. This circuit is dedicated to multimedia applications     

A versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-μm,3.5-nm Tox, 1.8-V CMOS technology

This I/O driver supports 3.3/2.5/1.8-V interfaces in a 3.5-nm Tox, 1.8-V CMOS technology. A bias generator, its switch capacitors, and a level shifter with protection network guarantee reliability and improve noise rejection. Measured output timing degradation is 2.5 ps per I/O switching. Buried resistors limit variation in output impedance. Interface delay of 2 ns with worst case I/O switching allows 400-MHz operation     

Selection and modeling of integrated RF varactors on a 0.35-/spl mu/m BiCMOS technology

Integrated varactors are becoming a common feature for many RF designs and in particular RF voltage controlled oscillators (VCOs). Optimization of the quality of both the inductor and the varactor from the VCO core is essential. This work details the characterization and optimization of a number of varactor types available on a typical submicron BiCMOS process. Engineering of the bottom plate of the varactor was used to optimize the quality factor of the varactor. No additional mask layers or processing steps were required to achieve this. Integrated isolated diode varactors with quality factors of 30 at 2 GHz have been demonstrated with tuning capacitance ranges of 2.5. Integrated MOS capacitor varactors with quality factors of 50 at 2 GHz have been demonstrated with tuning capacitance range of 5. A spice model for one of the varactor types is further developed in this paper. Accurate prediction of varactor performance over voltage bias and frequency was achieved.     

BF2 and boron double-implanted source/drain junctionsfor sub-0.25-μm CMOS technology

A double implant source/drain junction formation process using BF ₂ and boron is proposed for PMOSFET in sum-0.25-μm CMOS technology. Compared to the more conventional, single implant processes using BF₂, the double implant process with downscaled BF₂ implant energy offers the advantages of lower junction capacitance, less boron penetration, thinner gate oxide, and wider process window, as experimentally demonstrated     

0.3-μm gate length p-channel AlGaAs/InGaAs heterostructure fieldeffect transistors with high cut-off frequency

P-channel Heterostructure Field Effect Transistors (HFETs) with a 0.3-μm gate were fabricated by Mg ion implantation. The maximum transconductance was 68 mS/mm and there was no serious drain or gate leakage current, regardless of this short gate length. The gate turn on voltage (@I_gs=-1 μA/μm) was -2.1 V and its absolute value was large enough for use in complementary HFETs. S-parameters measurements showed a very high cut-off frequency of over 10 GHz. Results indicated the superiority of less-diffusive Mg ion implantation for forming p⁺-layer in p-channel HFETs     

0.3-μm advanced SAINT FET's having asymmetricn+-layers for ultra-high-frequency GaAs MMIC's

Improvements in the microwave performance and noise performance of buried p-layer self-aligned gate (BP-SAINT) FETs are discussed. Specifically, a self-aligned gate electrode and an asymmetric n⁺ -layer structure are investigated. The self-aligned gate electrode reduces parasitic gate capacitances by 0.13 to 0.23 pF/mm compared with a conventional BP-SAINT FET. The asymmetric n⁺-layer structure reduces short-channel effects (drain conductance, threshold voltage shift, etc.) and gate-drain capacitance. A 0.3-μm gate-length FET was realized without an increase of short-channel effects by using an asymmetric n⁺-layer structure (advanced SAINT). Improvement of microwave performance is confirmed in this FET structure