Efficient Reverse Converters for 4-Moduli Sets {2^{2n-1}-1, 2^{n}, 2^{n}+1, 2^{n}-1} and {2^{2n-1}, 2^{2n-1}-1, 2^{n}+1, 2^{n}-1} Based on CRTs Algorithm

Speed and complexity of a reverse converter are two important factors that affect the performance of a residue number system. In this paper, two efficient reverse converters are proposed for the 4-moduli sets {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } and {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } with 5 \(n\) -bit and 6 \(n\) -bit dynamic range, respectively. The proposed reverse converter for moduli set {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed based on CRT and New CRT-I algorithms and in two-level structure. Also, an efficient reverse converter for moduli set {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed by applying New CRT-I algorithm. The proposed reverse converters are based on adders and hence can be simply implemented by VLSI circuit technology. The proposed reverse converters offer less delay and hardware cost when compared with the recently introduced reverse converters for the moduli sets {2 \(^{n}+1\) , 2 \(^{n}-1\) ,2 \(^{n}\) , 2 \(^{2n+1}-1\) } and {2 \(^{n}+1\) , 2 \(^{n}-1\) , 2 \(^{2n}\) , 2 \(^{2n+1}-1\) }.     

A 5 GHZ CMOS Power VCO with Novel Frequency-Modulation for RF Transmitter

A 5 GHz transformer-feedback power oscillator with novel frequency modulation (FM) up to 10 MHz is presented in this paper. The novel FM is achieved by a CMOS transistor between transformer and ground, which is designed for varying the equivalent inductance and mutual inductance of the transformer and shows no DC connection with the oscillation circuit. The major frequency tuning is realized by the variable capacitor which is controlled by a phase lock loop. The RF VCO with 210 MHz tuning range operates in class-E mode to achieve a cost-effective transmitter, which demonstrates a high DC-to-RF conversion efficiency of 39 %. A RF power of 15.1 dBm and phase noise better than \(-\) 109 dBc/Hz @ 100 kHz from the central frequency of 5.5 GHz is obtained with the biasing conditions V \(_\mathrm{ds}\) = 1.8 V and V \(_\mathrm{gs}\) = 0.65 V. The VCO also demonstrates an ultra-low voltage operation capability: with V \(_\mathrm{ds}\) = V \(_\mathrm{gs}\) = 0.6 V and DC power consumption of 9 mW, the output power is 4.5 dBm and the phase noise better than \(-\) 93 dBc/Hz @ 100 kHz. The die size of the transformer-feedback power oscillator is only \(0.4\times 0.6\) mm \(^{2}\) .     

Method for Designing Efficient Mixed Radix Multipliers

The multiplication of two signed inputs, \(A {\times } B\) , can be accelerated by using the iterative Booth algorithm. Although high radix multipliers require summing a smaller number of partial products, and consume less power, its performance is restricted by the generation of the required hard multiples of B ( \(\pm \phi B\) terms). Mixed radix architectures are presented herein as a method to exploit the use of several radices. In order to implement efficient multipliers, we propose to overlap the computation of the \(\pm \phi B\) terms for higher radices with the addition of the partial products associated to lower radices. Two approaches are presented which have different advantages, namely a combinatory design and a synchronous design. The best solutions for the combinatory mixed radix multiplier for \(64\times 64\) bits require \(8.78\) and \(6.55~\%\) less area and delay in comparison to its counterpart radix-4 multiplier, whereas the synchronous solution for \(64\times 64\) bits is almost \(4{\times }\) smaller in comparison with the combinatory solution, although at the cost of about \(5.3{\times }\) slowdown. Moreover, we propose to extend this technique to further improve the multipliers for residue number systems. Experimental results demonstrate that best proposed modulo \(2^{n}{-}1\) and \(2^{n}{+}1\) multiplier designs for the same width, \(64{\times }64\) bits, provide an Area-Delay-Product similar for the case of the combinatory approach and \(20~\%\) reduction for the synchronous design, when compared to their respective counterpart radix-4 solutions.     

An Ideal Multi-secret Sharing Scheme Based on Connectivity of Graphs

Secure communication has become more and more important for many modern communication applications. In a secure communication, every pair of users need to have a secure communication channel (each channel is controlled by a server) In this paper, using monotone span programs we devise an ideal linear multi-secret sharing scheme based on connectivity of graphs. In our proposed scheme, we assume that every pair of users, \(p\) and \(q\) , use the secret key \(s_{pq} \) to communicate with each other and every server has a secret share such that a set of servers can recover \(s_{pq} \) if the channels controlled by the servers in this set can connect users, \(p\) and \(q\) . The multi-secret sharing scheme can provide efficiency for key management. We also prove that the proposed scheme satisfies the definition of a perfect multi-secret sharing scheme. Our proposed scheme is desirable for secure and efficient secure communications.     

BER Evaluation of IEEE 802.15.4 Compliant Wireless Sensor Networks Under Various Fading Channels

This paper presents bit error rate (BER) analysis of wireless sensor networks (WSNs) consisting of sensor nodes based on an IEEE 802.15.4 RF transceiver. Closed-form expressions for BER are obtained for WSNs operating over AWGN, Rayleigh and Nakagami-m fading channels. For the purpose of analysis, we consider an IEEE 802.15.4 RF transceiver using direct sequence spread spectrum-offset quadrature phase shift keying (DSSS-OQPSK) modulation under 2.4 GHz frequency band in a WSN. Analytical expressions for BER are derived for a wireless link between sensor nodes that act as a transmitter unit and a base station without considering the effect of interferers in the wireless environment. Numerical results for BER are obtained by varying the IEEE 802.15.4 standard specific physical layer parameters, such as number of bits used to represent a Zigbee symbol, number of modulation levels used in an OQPSK modulator, and various values of Rayleigh and Nakagami-m fading parameters, denoted as \(\alpha \) and \(m\) , respectively. Moreover, optimum values of physical layer parameters are identified for improved system performance. It is found that error performance analysis of WSN shows improvement when lower number of bits is used to represent a Zigbee symbol. Specifically, under a Rayleigh fading channel which reflects a real-time WSN environment, the network exhibits better performance only when it is operated at high SNR values, i.e., BER of order \(10^{-2}\) is achieved when SNR lies in the range 5–15 dB. Also, the effect of fading parameters on network performance shows that better results are obtained for higher values of \(\alpha \) and \(m\) for Rayleigh and Nakagami-m fading channels, respectively.     

A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

A fully integrated 0.18- \(\upmu \hbox {m}\) CMOS LC-tank voltage-controlled oscillator (VCO) suitable for low-voltage and low-power S-band wireless applications is proposed in this paper. In order to meet the requirement of low voltage applications, a differential configuration with two cross-coupled pairs by adopting admittance-transforming technique is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed VCO can operate at 0.4 V supply voltage. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosting circuit and the standard mode PMOS varactors in the proposed oscillator architecture. The simulation results show that the proposed VCO achieves phase noise of \(-\) 120.1 dBc/Hz at 1 MHz offset and 39.3 % tuning range while consuming only \(594~\upmu \hbox {W}\) in 0.4 V supply. Figure-of-merit with tuning range of the proposed VCO is \(-\) 192.1 dB at 3 GHz.     

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing

We propose an ultra-low power memory design method based on the ultra-low ( \(\sim \) 0.2 V) write-bitline voltage swing to reduce the write power dissipation for read-decoupled SRAM (RD-SRAM) cells. By keeping the write bitlines at ground level (0 V) during standby and charging them to a low voltage \(V_\mathrm{L}\) ( \(\sim \) 0.2 V) during write operations, the power dissipation for the write bitlines is greatly reduced (0.2 V/ \(V_\mathrm{DD})^{ 2 }\,\times \) 100 %) due to reduced voltage swing (from \(V_\mathrm{DD }\)  = 1.2 to 0.2 V) on the write bitlines. The proposed method is applicable to both dual-voltage and single-voltage operations. We analyze the proposed ultra-low write-bitline voltage swing method and investigate its reliability based on 10K Monte-Carlo simulations. We further verify the functionality and performance of our proposed design through measurements on the fabricated prototypes based on the 65 nm CMOS process. By means of a \(256 \times 64\) bit RD-SRAM memory implementation, we show that our proposed method reduces 87 % write power dissipation when compared to a conventional design.     

Nanovoid Formation and Dynamics in He+-Implanted Nanocrystalline Silicon

Helium implantation in single crystal silicon is known to lead, after a proper thermal treatment, to the formation of voids with diameters ranging between 10 nm and 30 nm. Formation of voids is governed by the coalescence of vacancies created by implantation, initially trapping helium atoms. At high temperatures ( \({\ge}700^{\circ }\hbox {C}\) ), helium leaves the nanobubbles and outdiffuses, while the now empty voids grow in size and eventually change their shape to form tetrakaidecahedra (Wulff construction). In this communication, we report how He⁺ implantation in heavily boron-doped nanocrystalline silicon shows a completely different dynamics. Annealing at \(500^{\circ }\hbox {C}\) leads to the formation of large voids, located around grain boundaries, along with a large number of nanovoids with an average diameter of 2–4 nm and an estimated density of \(3\times 10^{17}\,\hbox {cm}^{-3}\) distributed throughout the grains. Annealing at higher temperature (up to \(1000^{\circ }\hbox {C}\) ) also induces a decrease of the void size with a change in their density, finally accounting to \(2\times 10^{18}\,\hbox {cm}^{-3}\) . The high temperature annealing also causes vacancy evaporation down to a depth of 80–100 nm from the outer surface. The possibility of obtaining a stable, uniform distribution of nanometer-sized voids is of major relevance as a novel tool for phonon and electron engineering in thermoelectric materials.     

Approximation algorithms for broadcasting in duty cycled wireless sensor networks

Broadcast is a fundamental operation in wireless sensor networks (WSNs). Given a source node with a packet to broadcast, the aim is to propagate the packet to all nodes in a collision free manner whilst incurring minimum latency. This problem, called minimum latency broadcast scheduling (MLBS), has been studied extensively in wireless ad-hoc networks whereby nodes remain on all the time, and has been shown to be NP-hard. However, only a few studies have addressed this problem in the context of duty-cycled WSNs. In these WSNs, nodes do not wake-up simultaneously, and hence, not all neighbors of a transmitting node will receive a broadcast packet at the same time. Unfortunately, the problem remains NP-hard and multiple transmissions may be necessary due to different wake-up times. Henceforth, this paper considers MLBS in duty cycled WSNs and presents two approximation algorithms, BS-1 and BS-2, that produce a maximum latency of at most \((\Delta -1) TH\) and \(13TH\) respectively. Here, \(\Delta\) is the maximum degree of nodes, \(T\) denotes the number of time slots in a scheduling period, and \(H\) is the broadcast latency lower bound obtained from the shortest path algorithm. We evaluated our algorithms under different network configurations and confirmed that the latencies achieved by our algorithms are much lower than existing schemes. In particular, compared to OTAB, the best broadcast scheduling algorithm to date, the broadcast latency and transmission times achieved by BS-1 is at least \(\frac{1}{17}\) and \(\frac{2}{5}\) that of OTAB respectively.     

Minimum payment collaborative sensing network using mobile phones

Mobile phones with embedded sensors have been applied in various collaborative sensing applications. To encourage mobile phone users to perform collaborative sensing, the data demanders usually pay mobile phone users for required data. In this paper, we study the Minimum Payment of Attaining the Required Data with mobile phones (MPARD) problem in collaborative sensing network: given sensing regions \(R = \{R_1, R_2, \ldots , R_m\}\) , the set of requisite data \(D_i\) for each sensing region \(R_i\) and a set of mobile phones \(M\) , the \(MPARD\) problem studies how to select mobile phones to obtain all the required data such that the data demanders’ total payment to mobile phone users is minimized. In reality, some systems need the fresh sensing data from mobile phones at each pre-determined time slot, and others don’t require the real-time data and the sensing data from previous time slots is also deemed useful. Based on the above two different requirements of data timeliness, we first define two subproblems derived from \(MPARD\) problem: \(MPARD_t\) and \(MPARD_p\) . After that, for each subproblem, we propose an approximation algorithm for the situation where the trajectories of mobile phones are determinate and a heuristic for the situation where trajectories are unknown. Simulation results demonstrate that our algorithms are efficient.     

Performance Analysis of 4\times 4 and 8\times 8 MIMO System,to Achieve Higher Spectral Efficiency in Rayleigh and Rician Fading Distributions

The proposed work deals with the performance analysis of \(4 \times 4\) and \(8 \times 8\) multiple input multiple output (MIMO) wireless communication system to achieve higher spectral efficiency in Rayleigh and Rician fading distributions. The key channel model used is spatial multiplexing. Singular value decomposition is used to carry out the simulation of \(4\times 4\) and \(8\times 8\) MIMO channel. This scheme also employs the Waterfilling algorithm which allocates the power in all sub-channels improving the Spectral Efficiency. Next generation wireless communication systems require implementations of MIMO to realize higher spectral efficiency.     

A 97 dB 400 MHz rail to rail fully differential opamp based on split length FGMOS-MOS cell

Recently introduced MOS-FGMOS split length cell has been used to increase the DC gain of a fully differential op amp. Resultant proposed opamp structure exhibits gain of 97 dB and unity gain bandwidth of 400 MHz with power consumption of 1.2 mW. An opamp design has been verified with Cadence Spectre using a 130 nm technology at 1.2 V and has a slew rate of \(53\,\hbox {V}/\mu \hbox {s}\) with a phase margin of \(78^{\circ }\) .     

Downlink SINR Study in Multiuser Large Scale Antenna Systems

In this paper, the downlink signal-to-interference-plus-noise ratio (SINR) performance in multiuser large scale antenna systems with matched filter (MF) and regularized zero-forcing (RZF) precoding is investigated. The probability density function (PDF) for MF is derived and the distribution in high signal-to-noise ratio (SNR) regime is studied. Results indicate that the PDF of downlink SINR for MF converges to \(\mathcal F\) distribution when the interference is dominant over noise. For MF, the asymptotic SINR is just the reciprocal of the ratio of the number of users \(U\) to the number of transmit antennas \(N\) , and is irrelevant to the average transmit power when \(N\) and \(U\) grow with fixed ratio. However, when \(U\) is a large constant, the transmit power could be proportional to \(\ln N \big /N \) to maintain a specified quality of service, as a result of the large scale antenna system effect. In addition, the closed form of asymptotic SINR for RZF is derived by solving two mathematical expectations related to eigenvalues of large dimensional random matrices. Simulation results validate the derived PDF and analytical results.     

A Novel 2.5–3.1 GHz Wide-Band Low-Noise Amplifier in 0.18 \upmu \hbox {m} CMOS

Aiming for the simultaneous realization of constant gain, accurate input and output impedance matching and minimum noise figure (NF) over a wide frequency range, the circuit topology and detailed design of wide broadband low noise amplifier (LNA) are presented in this paper. A novel 2.5–3.1 GHz wide-band LNA with unique characteristics has been presented. Its design and layout are done by TSMC 0.18  \(\upmu \hbox {m}\) technology. Common gate stage has been used to improve input matching. In order to enhance output matching and reduce the noise as well, a buffer stage is utilized. Mid-stages which tend to improve the gain and reverse isolation are exploited. The proposed LNA achieves a power gain of 15.9 dB, a NF of 3.5 dB with an input return loss less than \(-\) 11.6, output return loss of \(-\) 19.2 to \(-\) 19 and reverse isolation of \(-\) 38 dB. The LNA consumes 54.6 mW under a supply voltage of 2 V while having some acceptable characteristics.     

Mutual Distance Bounding Protocol with Its Implementability Over a Noisy Channel and Its Utilization for Key Agreement in Peer-to-Peer Wireless Networks

In order to protect a wireless sensor network and an RFID system against wormhole and relay attacks respectively, distance bounding protocols are suggested for the past decade. In these protocols, a verifier authenticates a user as well as estimating an upper bound for the physical distance between the user and itself. Recently, distance bounding protocols, each with a mutual authentication, are proposed to increase the security level for such systems. They are also suggested to be deployed for key agreement protocols in a short-range wireless communication system to prevent Man-in-the-Middle attack. In this paper, a new mutual distance bounding protocol called NMDB is proposed with two security parameters ( \(n\) and \(t\) ). The parameter \(n\) denotes the number of iterations in an execution of the protocol and the parameter \(t\) presents the number of errors acceptable by the verifier during \(n\) iterations. This novel protocol is implementable in a noisy wireless environment without requiring final confirmation message. Moreover, it is shown that, how this protocol can be employed for the key agreement procedures to resist against Man-in-the-Middle attack. NMDB is also analyzed in a noisy environment to compute the success probability of attackers and the rejection probability of a valid user due to channel errors. The analytically obtained results show that, with the proper selection of the security parameters ( \(n\) and \(t\) ) in a known noisy environment, NMDB provides an appropriate security level with a reliable performance.     

Outage Capacity Analysis of a Cooperative Relaying Scheme in Interference Limited Cognitive Radio Networks

In this study, we investigate the outage capacity of a cooperative relaying based cognitive radio network in slow fading channel. Our network scenario consists of a primary transmitter (PT) and primary receiver (PR) as well as a group of \(M\) secondary transmitter (ST)–receiver (SR) pairs. We grouped STs into active and inactive. Only one active ST may transmit data at a time in parallel with the PT satisfying a predefined interference threshold \(I_{th}\) to the PR. Due to fading/shadowing or interference caused by ST to the PR, primary user (PU) may fail to achieve its target rate \(R_{{\textit{PT}}}\) over a direct link. To overcome this, we can boost up primary capacity by using inactive STs as cooperative relay (Re) nodes for the PU. In addition, one of the inactive STs that achieves \(R_{{\textit{PT}}}\) will be act as a best decode-and-forward relay to forward the primary information. In this paper, a closed-form expression of the outage capacity is derived. Results show that outage capacity improves with increasing cooperative nodes as well as when the active ST is located farther away from the PR.     

Anisotropic Thermopower of the Kondo Insulator \hbox {CeRu}_4\hbox {Sn}_6

The intermetallic compound \(\hbox {CeRu}_4\hbox {Sn}_6\) has been tentatively classified as Kondo insulator. This class of material, especially non-cubic representatives, is not yet fully understood. Here we report thermopower measurements on single-crystalline \(\hbox {CeRu}_4\hbox {Sn}_6\) between 2 K and 650 K, along the main crystallographic directions. Large positive thermopower is observed in the directions along which the hybridization is strong and a Kondo insulating gap forms. A negative contribution to the thermopower dominates for the crystallographic \(c\) axis where hybridization is weak and metallicity prevails.     

Construction of (2k,k, 2) Convolutional Codes with Double-Loop Cyclic Codes

In this paper, by taking multiple-time information in blocks into the coding of linear block codes, a new class of (2 \(k\) , \(k\) , 2) convolutional codes is constructed, by which a new way of constructing long codes with short ones is obtained. After that, the type of embedded codes is determined and the optimal values of the linear combination coefficients are derived by using a three-dimensional state transfer matrix to analyze and testify the constructing mechanism of the codes. Finally, the simulation experiment tests the error-correcting performance of the (2 \(k\) , \(k\) , 2) convolutional codes for different value of \(k\) , it is shown that the performance of the new convolutional codes compares favorably with that of traditional (2, 1, \(l\) ) convolutional codes.     

A remotely-powered, 20 Mb/s, 5.35 pJ/bit impulse-UWB WSN tag for cm-accurate-localization sensor networks

This paper presents an ultra-low-power, low-voltage sensor node for wireless sensor networks. The node scavenges RF energy out of the environment, resulting in a limited available power budget and causing an unstable supply voltage. Hence, accurate and extensive power management is needed to achieve proper functionality. The fully integrated, autonomous system is described, including the scavenging circuitry with integrated antenna, the power detection and power control circuits, the on-chip clock reference, the UWB transmitter and the digital control circuitry. The wireless sensor node is implemented in \(0.13 \,\upmu \hbox {m}\) CMOS technology. The only external components are a storage capacitor and a UWB transmit antenna. The system consumes only \(113\, \upmu \hbox {W}\) during burst mode, while only 8 nW is consumed during the scavenging operation, enabling an efficiency of 5.35 pJ/bit which is significantly better than current state-of-the-art UWB tags. Due to the use of impulse-radio UWB, also cm-accurate localization of the tag can be achieved.     

A Wide Tuning Range Voltage Controlled Oscillator with a High Tunable Active Inductor

This paper presents a wide tuning range CMOS voltage controlled oscillator (VCO) with a high-tunable active inductor circuit. In this VCO circuit, the coarse frequency is achieved by tuning the integrated active inductor circuit. The VCO circuit is designed in 0.18  \(\upmu \hbox {m}\) CMOS process and simulated with Cadence Spectra. The simulation results show the frequency tuning range from 120 MHz to 2 GHz resulting in a tuning range of 94 %. The phase noise variation is from \(-\) 80 to \(-\) 90 dBc/Hz at a 1 MHz frequency offset, and output power variation is from \(-\) 4.7 to \(+\) 11.5 dBm. The active inductor power consumption is 2.2 mW and the total power dissipation is 7 mW from a 1.8 V DC power supply. By comparing the proposed VCO circuit with the general VCO topology, the results show that this VCO architecture by using the novel, high-tunable and low power active inductor circuit, presents a better performance regarding low chip size, low power consumption, high tuning range and high output power.