一种具有精确增益控制的CMOS可编程增益放大器

采用0.13μm RF CMOS工艺,设计了一款具有精确增益步长控制的宽带可编程增益放大器.在传统电阻网络衰减器的基础上,提出了一种新的增益控制方法.该方法采用两个互相重叠的反馈环路,通过改变环路中跨导的比值以实现精细的增益步长控制.测试结果表明,当电源电压为1.2V时,功耗为24 mW,-3 dB带宽为600MHz....     

一种用于接收机的低功耗自动增益控制环路

This paper proposes a new structure to lower the power consumption of a variable gain amplifier (VGA) and keep the linearity of the VGA unchanged. The structure is used in a high rate amplitude-shift keying (ASK) based IF-stage. It includes an automatic gain control (AGC) loop and ASK demodulator. The AGC mainly consists of six-stage VGAs. The IF-stage is realized in 0.18 μ m CMOS technology. The measurement results show that the power consumption of the whole system is very low. The system consumes 730 μ A while operating at 1.8 V. The minimum ASK signal the system could detect is 0.7 mV (peak to peak amplitude).     

一个新型的带自动增益控制环路的低功耗ASK接收机

实现了一个适用于短距离无线系统的低功耗ASK中频接收机电路.该接收机包括一个用于补偿信道衰减的自动增益控制环和一个ASK检波器.自动增益控制环中采用了新型的限流跨导器和带前馈的差分峰值检测器,从而以较低的功耗实现了较高的压缩比及较快的响应速度.通过在峰值存储单元中引入零点及在峰值检测电路中引入前馈,实现了对自动增益控制环阻尼特性的调整.ASK检波器中传统的整流器和低通滤波器被整合为更紧凑的结构,从而进一步降低了功耗.仿真结果验证了本文所提技术的有效性.     

一种可植于软件无线电的低功耗可编程增益放大器

本文提出了一种新的技术,用于优化可编程增益放大器的带宽和功耗的关系。这个可编程增益放大器由三级级联的放大器组成,每一级放大器包括可变增益放大器和直流失调电压消除电路。在消除直流失调的电路中,高通的截止频率可从4 kHz到80 kHz变化。可编程增益放大器芯片使用0.13微米的工艺加工,测试结果表明增益可以从-5dB到60dB连续可调。在 60dB增益模式下,当带宽可从1MHz到10MHz变换,电路消耗的功耗为0.85mA到3.2mA,电源电压为1.2V。它的带内OIP3值为14dBm。     

一种应用于高清视频模拟前端的多功能开关电容可编程增益放大器

A multifunctional programmable gain amplifier(PGA) that provides gain and offset adjusting abilities for high-definition video analog front-ends(AFE) is presented. With a switched-capacitor structure, the PGA also acts as a sample and holder of the analog-to-digital converter(ADC) in the AFE to reduce the power consumption and chip area of the whole AFE. Furthermore, the PGA converts the single-ended video signal into differential signal for the following ADC to reject common-mode noise and interferences. The 9-bit digital-to-analog converter(DAC) for gain and offset adjusting is embedded into the switched capacitor networks of the PGA. A video AFE integrated circuit based on the proposed PGA is fabricated in a 0.18- m process. Simulation and measurement results show that the PGA achieves a gain control range of 0.90 to 2.34 and an offset control range of –220 to220 mV while consuming 10.1 mA from a 1.8 V power supply.     

一种用于卫星导航接收机的低噪声放大器设计

设计了一种可用于多模式卫星导航接收机的射频前端低噪声放大器,设计电路可在1.13～1.95 GHz工作,兼容了GPS,北斗及GLONOSS导航系统的工作频段。电路采用0.18 μm CMOS工艺实现。仿真结果表明,频带内S11和S22均在-10 dB以下,功率增益＞10 dB,带内最小噪声系数可达到2.2 dB,输出1 dB压缩点为-5.585 dBm,在1.8 V电源电压下,主体电路消耗12 mA电流。因此,该低频噪声放大器模块可满足当前各种导航系统的工作要求。     

一种带宽为3.8GHz，增益步长为0.1dB的可编程增益放大器

A broadband programmable gain amplifier（PGA） with a small gain step and low gain error has been designed in 0.13 m CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A two-stage gain control method, which consists of a resistor ladder attenuator and an active fine gain control stage, provides the small gain step. A look-up table based gain control method is introduced in the fine gain control stage to lower the gain error.The proposedPGAshows a decibel-linear variable gainfrom4 to20 dB with a gain step of 0.1 dB and a gain error less than˙0.05 dB. The 3-dB bandwidth and maximum IIP3 are 3.8 GHz and 17 dBm, respectively.     

一种CMOS卫星导航接收机多模低噪声放大器设计

本文介绍了一种用于卫星导航接收机中的多模低噪声放大器模块的设计.采用主流CMOS工艺,对源极负反馈的共源共栅放大器的放大管栅源两极间增加可调电容、调整偏置电压、共用片外匹配以及调整输出电感的方法,实现多个频点的噪声和功率匹配.采用TSMC 0.18μm 1P4M射频CMOS工艺进行流片验证,在1.207GHz到1.575GHz频段多个频点处的可获得17.3dB到18.5dB增益,在1.8V工作电压下,噪声系数均小于1.8dB,工作电流均小于3.6mA,完全满足接收机的应用.     

一种可用于遥测接收机的宽带AGC环路

介绍了一种可用于遥测接收机的宽带、高精度AGC电路,该电路利用了高速超高精度乘法器具有可外控分母电压的特性。同时由于乘法器的GBW很高,使得这种AGC电路在带宽和精度方面的性能都比较好。     

一种用于大规模无线传感网RF前端电路的dB线性可编程增益放大器

设计了一种应用于大规模无线传感网RF前端芯片的数字控制CMOS可编程增益放大器(PGA).该放大器采用五级增益单元级联结构,每个增益单元采用了固定增益放大器加可编程衰减器的结构,且具有直流漂移抑制功能.增益的变化通过两步完成,R-2R梯形电阻网络实现6dB增益步进,而0.75dB步进由串行电阻网络来完成.后仿真结果表明,放大器的动态范围为10～88dB,0.75dB步进,增益精确度为0.7mdB,最大增益下输出三阶交调点为16.1dBm.可编程增益放大器采用SMIC 0.18μm 1P6M混合信号CMOS工艺实现,核面积约为0.08mm2.     

GNSS接收机锁相环最佳环路带宽的选取

锁相环环路带宽值的选取对于锁相环的跟踪误差性能有重要影响。基于全球卫星导航系统(GNSS）接收机中常用锁相环结构与数学模型,首先介绍了锁相环及其重要组成部分环路滤波器的结构和原理,然后分析了环路带宽的取值对锁相环两个最重要的误差源——环路热噪声误差和晶振阿伦偏差的影响,给出了低动态下使锁相环总的跟踪误差最小的最佳环路带宽的理论表达式。对基于由现场可编程门阵列（FPGA）芯片、温补晶振和模/数接口电路构建的实际硬件接收机平台进行了验证,结果表明：当根据最佳环路带宽的理论表达式取环路带宽值时,锁相环的跟踪误差最小。所推得的理论表达式不仅可以应用于GNSS接收机,也适用于一般的载波跟踪环设计。     

基于65nm CMOS用于导航接收机的2mW 50dB范围宽带混合AGC设计

实现了一种用于导航接收机的低功耗宽带混合自动增益控制(AGC)环路。I/Q路中单个AGC由四级可编程增益放大器(PGAs)、差分峰值检测、两个比较器、控制算法逻辑、译码器和参考电压源组成。除了能由AGC环路控制外,PGA的增益也能通过SPI接口由片外数字基带处理器控制。为获得低功耗和噪声,采用一种改进的源简并放大器,且I/Q路间的相位失配能以0.2?精度在?5?范围内校准。整体电路用65nm CMOS实现,测试的PGA总增益为9.8dB~59.5dB,平均步进为0.95dB,且仿真带宽超过110MHz。从射频放大器RFA输入端口加功率-76.7dBm~-56.6dBm跳变的80% AM信号,测试建立时间约为180μs,且随着时钟频率加倍减小到90μs。单个AGC用2.5V电源供电时消耗约0.8mA电流,占用750?300μm2芯片面积。     

A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

正A constant loop bandwidth fractional-TV frequency synthesizer for portable civilian global navigation satellite system(GNSS) receivers implemented in a 130 nm 1P6M CMOS process is introduced.Via discrete working regions,the LC-VCO obtains a wide tuning range with a simple structure and small VCO gain.Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps.The optimized bandwidth is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies.Measurement results show that this synthesizer attains an in-band phase noise lower than -93 dBc at a 10 kHz offset and a spur less than -70 dBc;the bandwidth varies by±3%for all the GNSS signals.The whole synthesizer consumes 4.5 mA current from a 1 V supply,and its area(without the LO tested buffer) is 0.5 mm~2.     

一种应用于GNSS接收机常数环路带宽的小数频率合成器

提出了一种应用于手持式民用GNSS接收机常数环路带宽的小数频率合成器,并在0.13μm 1P6M 的CMOS工艺中实现。通过离散的工作区域,LC-VCO用简单的结构获得宽的调节范围和小的压控灵敏度。提出的杂散抑制技术来最小化由于鉴频鉴相器和电荷泵引入的相位偏移。当PLL输出频率改变或温度变化时,通过自动环路校正模块自适应调整电荷泵电流保持优化的环路带宽不变。测试结果显示,该频率合成器带内相位噪声小于-93dBc（10 kHz 频率偏移处）,杂散小于-70 dBc, 环路带宽变化小于?3%;在1V的电源供电下,整个合成器（不包括本振测试buffer）消耗4.5mA电流,面积为0.5mm2。     

A digitally controlled phase-locked loop with a digitalphase-frequency detector for fast acquisition

A digitally controlled phase-locked loop (DCPLL) that achieves fast acquisition by employing a digital phase-frequency detector (DPFD) and a variable loop gain scheme was developed for an advanced clock synthesizer and was fabricated in a 3.3-V 0.6-μm CMOS process. The DPFD was developed to measure the frequency difference and to generate digital outputs corresponding to the difference. Using these features, the DCPLL achieves ideally one-cycle frequency acquisition when programmed with an appropriate gain. The experimental results show that the fabricated DCPLL exhibits three-cycle and one-cycle frequency acquisitions, when locking to 400 MHz (VCO at 800 MHz) and 200 MHz (VCO at 400 MHz), respectively     

一种应用于双通道卫星导航接收机的高效率低噪声电源解决方案

本文提出了一种应用于双通道卫星导航接收机的高效率低噪声电源解决方案,主要包括降压型DC-DC转换器和低压差稳压器。为了获得更好的噪声抑制和抗干扰性能,应用脉冲宽度调制(PWM)作为DC-DC转换器的控制方式。提出了一种改进的低功耗PWM控制电路,通过周期性的关断跨导放大器,将转换器的平均静态功耗降低了一半,并且具有较高的工作频率。针对双通道接收机的特点,对输出级功率管的尺寸进行了优化,使效率最优。另外,提出了一种基于限流原理的新型软启动电路,无须使用片外大电容或数模转换器,降低了设计复杂度。电路使用180nm CMOS工艺流片,测试结果显示,DC-DC转换器在2MHz的工作频率下拥有最高93.1%的转换效率,整个双通道接收机在3.3V电源供电下仅消耗电流20.2mA。     

A high-efficiency,low-noise power solution for a dual-channel GNSS RF receiver

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented.The power solution involves a DC-DC buck converter and a followed low-dropout regulator(LDO).The pulsewidth -modulation(PWM) control method is adopted for better noise performance.An improved low-power highfrequency PWM control circuit is proposed,which halves the average quiescent current of the buck converter to 80μA by periodically shutting down the OTA.The size of the output stage has also been optimized to achieve high efficiency under a light load condition.In addition,a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current.Fabricated with commercial 180-nm CMOS technology,the DC-DC converter achieves a peak efficiency of 93.1%under a 2 MHz working frequency.The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.     

A low power automatic gain control loop for a receiver

This paper proposes a new structure to lower the power consumption of a variable gain amplifier(VGA) and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying(ASK) based IF-stage.It includes an automatic gain control(AGC) loop and ASK demodulator.The AGC mainly consists of sixstage VGAs.The IF-stage is realized in 0.18μm CMOS technology.The measurement results show that the power consumption of the whole system is very low.The system consumes 730μA while oper...     

A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver

The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance.The circuit is validated by simulations and fabricated in a standard 0.18μm 1P6M CMOS process. Close-loop phase noise measured is lower than -95 dBc at 200 kHz offset while the measured tuning range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply.The whole silicon required is only 0.53 mm~2.     

一种适用于便携式多模式全球卫星导航系统接收机的低功耗宽带频率合成器设计

本文提出了一种适用于便携式多模式全球卫星导航系统（GNSS）接收机的低功耗宽带频率合成器,并分析了GNSS接收机频率合成器的设计要点。该频率合成器通过采用具有调谐曲线补偿功能的单一VCO实现了较宽的频率范围,同时具有较低的功耗和好的相位噪声性能。该频率合成器在CMOS 0.18um 1P6M工艺上流片验证成功。测试表明,带内相位噪声小于-95dBc@200KHz,频率调谐范围为1.47-1.83GHz,而整个电路面积仅为0.55mm2,整个频率合成器功耗小于11.2mw。