不同氧化退火工艺下SiO2/SiC界面特性研究

The effect of the different re-oxidation annealing （ROA） processes on the SiO2/SiC interface charac- teristics has been investigated. With different annealing processes, the flat band voltage, effective dielectric charge density and interface trap density are obtained from the capacitance-voltage curves. It is found that the lowest interface trap density is obtained by the wet-oxidation annealing process at 1050 ℃ for 30 min, while a large num- ber of effective dielectric charges are generated. The components at the SiO2/SiC interface are analyzed by X-ray photoelectron spectroscopy （XPS） testing. It is found that the effective dielectric charges are generated due to the existence of the C and H atoms in the wet-oxidation annealing process.     

超薄SiO2/HfO2双层栅介质的时变击穿特性和击穿机制的研究

The characteristics of TDDB （time-dependent dielectric breakdown） and SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT （equivalent-oxide-thickness） of the gate stack （Si/SiO2/HfOz/TiN/TiA1/TiN/W） is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks： one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.     

Characterization of the effects of nitrogen and hydrogen passivation on SiO2/4H-SiC interface by low temperature conductance measurements

In this work we investigate the effects of NO annealing and forming gas (FG) an-nealing on the electrical properties of SiO2/SiC interface by low-temperature con-ductance measurements. With nitrogen passivation, the density of interface states (DIT) is significantly reduced in the entire energy range, and the shift of flatband voltage, ΔVFB, is effectively suppressed to less than 0.4 V. However, very fast states are ob-served after NO annealing and the response frequencies are higher than 1 MHz at room temperature. After additional FG annealing, the DIT and ΔVFB are further re-duced. The values of the DIT decrease to less than 1011 cm-2eV-1 for the energy range of EC-ET≥0.4 eV. It is suggested that the fast states in shallow energy levels origi-nated from the N atoms accumulating at the interface by NO annealing. Though FG annealing has a limited effect on these shallow traps, hydrogen can terminate the re-sidual Si and C dangling bonds corresponding to traps at deep energy levels and im-prove the interface quality further. It is indicated that NO annealing in conjunction with FG annealing will be a better post-oxidation process method for high perfor-mance SiC MOSFETs.     

利用物理气相淀积工艺制备的HfTaON薄膜热力学稳定性研究

We investigate the thermal stability of HfTaON films prepared by physical vapor deposition using high resolution transmission electronic microscope （HRTEM） and X-ray photoelectron spectroscopy （XPS）. The results indicate that the magnetron-sputtered HfTaON films on Si substrate are not stable during the post-deposition annealing （PDA）. HfTaON will react with Si and form the interfacial layer at the interface between HfTaON and Si substrate. Hf-N bonds are not stale at high temperature and easily replaced by oxygen, resulting in significant loss of nitrogen from the bulk film. SiO2 buffer layer introduction at the interface of HfraON and Si substrate may effectively suppress their reaction and control the formation of thicker interfacial layer. But SiO2 is a low k gate dielectric and too thicker SiO2 buffer layer will increase the gate dielectric＇s equivalent oxide thickness. SiON prepared by oxidation of N-implanted Si substrate has thinner physical thickness than SiO2 and is helpful to reduce the gate dielectric＇s equivalent oxide thickness.     

Influences of Injection Barrier and Mobility on Recombination Rate and Zone in OLEDs

The luminous efficiency of organic light-emitting devices depends on the recombination probability of electrons injected at the cathode and holes at the anode. A theoretical model to calculate the distribution of current densities and the recombination rate in organic single layer devices is presented taking into account the charge injection process at each electrode, charge transport and recombination in organic layer. The calculated results indicate that efficient single-layer devices are possible by adjusting the barrier heights at two electrodes and the carrier mobilities. Lowering the barrier heights can improve the electroluminescent（EL） efficiency pronouncedly in many cases, and efficient devices are still possible using an ohmic contact to inject the low mobility carrier, and a contact limited contact to inject the high mobility carrier. All in all, high EL efficiency needs to consider sufficient recombination, enough injected carriers and well transport.     

Effects of defect states on the performance of CuInGaSe2 solar cells

Device modeling has been carried out to investigate the effects of defect states on the performance of ideal CulnGaSe2 （CIGS） thin film solar cells theoretically. The varieties of defect states （location in the band gap and densities） in absorption layer CIGS and in buffer layer CdS were examined. The performance parameters： open-circuit voltage, short-circuit current, fill factor, and photoelectric conversion efficiency for different defect states were quantitatively analyzed. We found that defect states always harm the performance of CIGS solar cells, but when defect state density is less than 10 14 cm-3 in CIGS or less than 10 18 cm-3 in CdS, defect states have little effect on the performances. When defect states are located in the middle of the band gap, they are more harmful. The effects of temperature and thickness are also considered. We found that CIGS solar cells have optimal performance at about 170 K and 2 μm of CIGS is enough for solar light absorption.     

介质前后双重臭氧处理实现锗/氧化铪间界面钝化

The physical and electrical properties of a Ge/GeO₂/HfO₂/Al gate stack are investigated.A thin interfacial GeO₂ layer（ 1 nm） is formed between Ge and HfO₂ by dual ozone treatments,which passivates the Ge/high-k interface.Capacitors on p-type Ge substrates show very promising capacitance-voltage（C-V） characteristics by using in situ pre-gate ozone passivation and ozone ambient annealing after high-k deposition,indicating efficient passivation of the Ge/HfO₂ interface.It is shown that the mid-gap interface state density at the Ge/GeO₂ interface is 6.4×10¹¹ cm^-2·eV^-1.In addition,the gate leakage current density of the Ge/GeO₂/HfO₂/Al gate stack passivated by the dual ozone treatments is reduced by about three orders of magnitude compared to that of a Ge/HfO₂/Al gate stack without interface passivation.     

CuPc/C60 heterojunction thin film optoelectronic devices

The optoelectronic properties of heterojunction thin film device with ITO/CuPc/C60/Al structure have been investigated through analyzing their current–voltage characteristics, optical absorption and photocurrent. In this organic photovoltaic device CuPc acts as an optically active layer, C60 as the electron–transporting layer and ITO and Al as electrodes. It is observed that under illumination, the excitons are formed, which subsequently drift towards the interface with C60, where an internal electric field is present. The excitons that reach to the interface are subsequently dissociated into free charge carriers due to the electric field present at the interface. The experimental results show that in this device the total current density is a function of injected carriers at electrode–organic semiconductor surface, the leakage current through the organic layer and collected photogenerated current that results from the effective dissociation of excitons.     

Two-Dimensional Simulation of Interface States Effect on AlGaAs/GaAs HEMT

In most heterostructures there are various interface states due to lattice mismatch or imperfections at the interface.The properties of an AlGaAs/GaAs interface are intimately related to the device performance.The existence of interface states in an Al.Ga,-.As/GaAs heteros...     

括非耗尽势垒层的AlGaN/GaN MIS-HFET电荷控制解析模型

An analytical charge control model considering the insulator/AlGaN interface charge and undepleted AlGaN barrier layer is presented for AlGaN/GaN metal–insulator–semiconductor heterostructure field effect transistors (MIS-HFETs) over the entire operation range of gate voltage. The whole process of charge control is analyzed in detail and partitioned into four regions: I—full depletion, II—partial depletion, III—neutral region and IV—electron accumulation at the insulator/AlGaN interface. The results show that two-dimensional electron gas (2DEG) saturates at the boundary of region II/III and the gate voltage should not exceed the 2DEG saturation voltage in order to keep the channel in control. In addition, the span of region II accounts for about 50% of the range of gate voltage before 2DEG saturates. The good agreement of the calculated transfer characteristic with the measured data confirms the validity of the proposed model.     

高K栅介质/金属栅极金属氧化物半导体晶体管平带电压roll-off现象物理起源研究

本文从能带平衡的角度来研究带有高K栅介质/金属栅极的金属氧化物半导体晶体管平带电压roll-off现象,认为随着高K介质与Si衬底之间中间层厚度的减小,高K介质与Si之间直接的电子交换会从无到有,越来越强,而这可能是roll-off现象的起源之一。此外给出了在不同条件下基于此模型得到的理论模拟结果。     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

Thermal stability of high-k Er-silicate gate dielectric formed by interfacial reaction between Er and SiO2 films

We fabricated a high-k Er-silicate gate dielectric using interfacial reaction between Er and SiO₂ films and investigated its thermal stability. The reduced capacitance with increasing annealing temperature is associated with the chemical bonding change of Er-silicate from Er-rich to Si-rich, induced by a reaction between Er-silicate and Si during thermal treatment. Further an increase in the annealing temperature (>500 °C) causes the formation of Si dangling bonds, which is responsible for an increased interface trap density.     

Nanoscale electrical characterization of ultrathin high-k dielectric MOS stacks: A conducting AFM study

Extreme scaling in both silicon and alternative channel CMOS has highlighted the importance of localized characterization on the nanometer scale. We have used a conductive-contact atomic force microscopy (C-AFM) technique in ultra high vacuum (UHV) conditions to analyze and compare intrinsic stack degradation mechanisms leading to breakdown (BD) for ultrathin high-k dielectric films of (4 nm) Hf_xSiO_y/SiO₂ on Si and (2 nm) ZrO₂/GeO₂ on Ge. Simultaneous nanoscale current–voltage I–V characteristics, topography, tunneling current and relative tip–surface contact interactions as normal and lateral force maps revealed localized injected charge dependence on electrical stress. It is shown that the charge can propagate laterally. Successive voltage scanning is related to the overall post-BD conductivity for pre- to post-BD degradation propagation. In contrast with SiO₂ interface, an increased GeO₂ interlayer reactivity yielding more active interface defects is suggested.     

Influence of the SiO2 layer thickness on the degradation of HfO2/SiO2 stacks subjected to static and dynamic stress conditions

The substitution of the SiO₂ gate oxide in MOS devices by a material with a high-k dielectric constant is being deeply studied nowadays to solve the problem of the leakage currents that appear with the progressive scaling of SiO₂ thickness. To improve the quality of the high-k/Si interface a very thin SiO₂ film is grown between both materials. In this work, HfO₂/SiO₂ stacks with different SiO₂ thickness were subjected to different types of stress (static and dynamic) to analyze the effect of this interfacial layer of SiO₂ in the degradation of the stack. The results show that the dielectric degradation depends on the stress applied and that the thickness of the SiO₂ interfacial layer influences the advanced stages of the stack degradation.     

Lanthanum diffusion in the TiN/LaOx/HfSiO/SiO2/Si stack

Band edge Complementary Metal Oxide Semiconductor (CMOS) devices are obtained by insertion of a thin LaO_x layer between the high-k (HfSiO) and metal gate (TiN). High temperature post deposition anneal induces Lanthanum diffusion across the HfSiO towards the SiO₂ interfacial layer, as shown by Time of Flight Secondary Ions Mass Spectroscopy (ToF-SIMS) and Atom Probe Tomography (APT). Fourier Transform Infrared Spectroscopy in Attenuated Total Reflexion mode (ATR-FTIR) shows the formation of La-O-Si bonds at the high-k/SiO₂ interface. Soft X-ray Photoelectron Spectroscopy (S-XPS) is performed after partial removal of the TiN gate. Results confirm La diffusion and changes in the La chemical environment.     

Tunneling component suppression in charge pumping measurement and reliability study for high-k gated MOSFETs

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high-k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high-k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO₂-dominated high-k gate dielectrics is like mobile defect; while that with SiO₂-dominated ones is similar to the near-interface/border trap.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.     

Electrical characterization of metal-oxide-high-k dielectric-oxide-semiconductor (MOHOS) structures for memory applications

Conventional SONOS (polysilicon-oxide-nitride-oxide-silicon) non-volatile memory devices use silicon nitride as the charge storage layer. In this work, metal-oxide-high-k dielectric-oxide-silicon (MOHOS) structures are fabricated using HfO₂ and Dy₂O₃ high-k dielectrics as the charge storage layer. The Al/SiO₂/Dy₂O₃/SiO₂/Si capacitors have a C–V memory window of 1.88 V and a leakage current density of 10⁻⁸ A/cm². This leakage current is lower than those of Al/SiO₂/HfO₂/SiO₂/Si capacitors and other similar capacitors reported in the literature. A minimum detection window of 0.5 V for MOHOS capacitors can be maintained up to 2 × 10⁸ s using as-deposited Dy₂O₃. The better performance of the Al/SiO₂/Dy₂O₃/SiO₂/Si structure over Al/SiO₂/HfO₂/SiO₂/Si is attributed to the larger conduction band offset at the Dy₂O₃/SiO₂ interface (2.3 eV) versus 1.6 eV at the HfO₂/SiO₂ interface.     

BE-SONOS flash memory along with metal gate and high-k dielectrics in tunnel barrier and its impact on charge retention dynamics

We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO₃/HfAlO/SiO₂. These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon(BE-SONOS). In the proposed structure HfAlO and AlLaO₃ replace Si₃N₄ and the top SiO₂ layer in a conventional oxide/nitride/oxide(ONO) tunnel stack. Due to the lower conduction band offset(CBO) and high permittivity of the proposed material in the tunnel layer, it offers better program/erase(P/E) speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high-k materials while scaling, for the same equivalent oxide thickness(EOT). We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4%(at room temperature) after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time.