A compact, high-gain, 2-20-GHz MMIC amplifier

The authors describe an advanced MMIC amplifier providing a 20-dB gain block over the 2-20-GHz frequency range. The chip requires only three external bias capacitors and is well suited to automatic assembly. By simultaneously offering improved gain, power, and circuit density in the 2-20-GHz range, a significant advancement in single chip performance has been achieved     

A design technique for a 60 GHz-bandwidth distributed basebandamplifier IC module

A DC-60 GHz, 9 dB distributed amplifier IC module is fabricated with 0.15 μm InAlAs-InGaAs low-noise HEMTs with 155 GHz f_T and 234 GHz f_max. The device is mounted in a metal package with 1.8 mm coaxial cable signal interfaces. The package is specially designed using three-dimensional electromagnetic field analyses, resulting in very flat frequency characteristics of the module within 1.5 dB gain ripples over the entire bandwidth. A multichip module loaded with two amplifier ICs in cascade is also fabricated, and operates at a 17.5 dB gain from 60 kHz to 48 GHz. The 1 dB gain compression output power is about 5 dBm for both modules. The noise figure of the single-chip module is approximately 4 dB over a 10-40 GHz frequency range     

100-GHz high-gain InP MMIC cascode amplifier

A high-gain InP monolithic millimeter-wave integrated circuit (MMIC) cascode amplifier has been developed which has 8.0 dB of average gain from 75 to 100 GHz when biased for maximum bandwidth, and more than 12 dB of gain at 80 GHz at the maximum-gain bias point, representing the highest gains reported to date, obtained from MMICs at W band (75-100 GHz). Lattice-matched InGaAs-InAlAs high-electron-mobility-transistors (HEMTs) with 0.1-μm gates were the active devices. A coplanar waveguide (CPW) was the transmission medium for this MMIC with an overall chip dimension of 600×500 μm     

A 2-18 GHz low-noise/high-gain amplifier module

The effectiveness of the two-tier matrix amplifier as a very-low-noise device with very high associated gains across multioctave frequency bands is theoretically and experimentally demonstrated. Experimental modules whose topology is based on a computer-optimized design exhibit an average noise figure of F=3.5 dB with an associated average gain of G=17.8 dB across the 2-18 GHz frequency band. These state-of-the-art results were achieved with GaAs MESFETs whose minimum noise figure is F=2.2 dB at 18 GHz and whose gate dimensions are 0.25×200 μm. The design considerations and the test results are discussed in detail     

5-60-GHz high-gain distributed amplifier utilizing InP cascodeHEMTs

A high-gain InP MMIC cascode distributed amplifier was developed which has 12 dB of gain from 5 to 60 GHz with over 20-dB gain control capability and a noise figure of 2.5-4 dB in the Ka band. Lattice-matched InAlAs/InGaAs cascode HEMTs on InP substrate with 0.25-μm gate length were the active devices. Microstrip was the transmission medium for this MMIC with an overall chip dimension of 2.3 mm×0.9 mm. The gain/noise figure advantages of the InP HEMT over the AlGaAs HEMT and the superior gain performance of the cascode HEMT over the common-source HEMT are demonstrated     

基于宽带高增益的放大器设计

文中介绍了一种基于集成运算放大器实现的宽带高增益放大器,本系统创造性地利用两级宽带运放VCA822压控放大,宽带运算放大器OPA690输出,完成了一个通频带50 kHz~40 MHz,增益0~68 dB可调的宽带高增益放大器。放大器噪声小,通频带范围宽,最大放大倍数大,后级加入了开关手动切换的自动增益控制电路模块,自制电源降压模块。系统采用多种方式消除了高增益,高频自激。放大器输入输出阻抗均为50Ω,方便和前后级电路匹配。     

A very thin power amplifier multichip module for 1.9-GHz cellularphone systems

A compact thin power amplifier module for 1.9-GHz cellular phone systems has been incorporated using MCM-D technology and planarization technology of all passive components. The module consists of four Si-MOSFETs and is 9.4×7.2×1 mm, resulting in a volume of 0.07 cc including its shield metallic case. The module was designed with the computer simulator, Libra, and simplified lumped-element equivalent circuits of passive components. The fabricated module exhibited an output power of 33.3 dBm and power efficiency of 29%. These results suggest that these technologies will be very useful for the miniaturization of circuit components for GHz-band mobile communications     

A 6.5—16-GHz monolithic power amplifier module

A miniaturized 6.5-16-GHz power amplifier module, which includes T/R switch, dual polarity power supply, switch driver, and gate functions, was designed using two types of broad-band MMIC amplifiers. The two cascade designs were a 900-1200-µm FET amplifier and a 300-300-µm feedback amplifier which were used to provide large and small gain functions, respectively. The module exhibits 35 dB of gain, 1-W power output, and 55-dB T/R switch isolation.     

ESD protection design for 1- to 10-GHz distributed amplifier in CMOS technology

Two distributed electrostatic discharge (ESD) protection schemes are presented and applied to protect distributed amplifiers (DAs) against ESD stresses. Fabricated in a standard 0.25-/spl mu/m CMOS process, the DA with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of 5.5 kV and machine-model (MM) ESD level of 325 V and exhibits the flat-gain of 4.7 /spl plusmn/ 1 dB from 1 to 10 GHz. With the same amount of parasitic capacitance, the DA with the second protection scheme of the decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level over 8 kV and MM ESD level is 575 V, and has the flat-gain of 4.9 /spl plusmn/ 1.1 dB over the 1 to 9.2-GHz band. With these two proposed ESD protection schemes, the broad-band RF performances and high ESD robustness of the DA can be successfully codesigned to meet the application specifications.     

A 24-GHz high-gain Yagi-Uda antenna array

A compact 24-GHz Yagi-Uda antenna has been developed using standard design tables and simple scaling to take into account the added capacitance due to the supporting dielectric substrate. The antenna results in a directivity of 9.3 dB, a front-to-back ratio of 11 dB, and a bandwidth of 2.5-3%. The Yagi-Uda antenna has been implemented in an 11-beam system using a planar array and a 2-inch Teflon spherical lens. The measured patterns show a 22 dB gain beam, a cross-polarization level of -24 dB, and a crossover level of -6 dB. The design method presented in this paper is quite straightforward, and can be used to develop low-, medium-, and even high-gain endfire Yagi-Uda antennas.     

UHF大功率功放模块设计的新方法

针对OFDM信号对功放高峰值功率的要求,提出了工作在220～400 MHz的大功率功放模块设计的新方法.该方法结合ADS软件仿真分析,按仿真模型用QFX86射频同轴电缆自制了功率分配/合成网络,用该网络设计了一款输出峰值功率不小于300W的功放模块.该模块已成功应用于某电台中且工作良好.     

Bipolar high-gain limiting amplifier IC for optical-fiber receivers operating up to 4 Gbit/s

A monolithic integrated high-gain limiting amplifier for future optical-fiber receivers is described. It is characterized by the following features: high insertion-voltage gain (maximum 54 dB); high input dynamic range (about 52 dB) at constant output-voltage swing (400 mV/SUB p-p/); high operating speed (up to at least 4 Gb/s); low power dissipation (350 mW at 50-/spl Omega/ load); standard supply voltage (5 V); 50-/spl Omega/ output buffer; one-chip solution; and small fabrication costs by use of a 2-/spl mu/m standard bipolar technology without needing polysilicon self-aligning processes. The good values of operating speed and power consumption, which the authors believe has until now not nearly been achieved by other comparable bipolar amplifier ICs, are a result of careful circuit design and optimization. The amplifier was extended to a high-sensitivity (amplitude and time) decision circuit operating at up to 4.0 Gb/s by adding a high-speed master-slave D-flip-flop IC fabricated with the same technology.     

一款高增益宽带低噪声放大器的设计

采用0.5μm GaAs E-PHEMT工艺设计了一款0.5～5 GHz高增益宽带低噪声放大器芯片.该放大器采用三级共源结构,运用负反馈技术有效地进行了输入输出阻抗匹配,针对高频增益不足问题,在共栅晶体管的栅极到地之间增加栅极电容,提高了高频增益,改善了增益平坦度,拓展了带宽.同时,放大器前两级应用电流复用技术,大大降...     

10-GHz Si bipolar amplifier and mixer ICs for coherent opticalsystems

Using a 30-GHz f_T silicon bipolar process, 10-GHz amplifier and mixer ICs for a multigigabit-per-second coherent optical-fiber communication system were fabricated. The dual-feedback amplifier with triple Darlington achieves a 10-GHz bandwidth and 20-dB gain. The Gilbert-cell mixer operates up to 10 GHz with a 10-dB conversion loss. The simulation technique, used for the design of these ICs includes an improved interconnect line model for the high-frequency region. The 10-GHz amplifier has a 1-mm² chip size and 210-mW power dissipation. The mixer has 2-mm² chip size and 550-mW power dissipation     

A high-gain monolithic D-band InP HEMT amplifier

This paper describes a three-stage monolithic amplifier that exhibits a small-signal gain of 30 dB at 140 GHz. The amplifier employs AlInAs/GaInAs/InP high electron mobility transistor devices with 0.1×150 μm² gate periphery, is implemented with coplanar waveguide circuitry fabricated on an InP substrate, and occupies a total area of 2 mm². Gain exceeding 10 dB was measured on-wafer from 129 to 157 GHz. This is the highest reported gain per stage for a transistor amplifier operating at these frequencies     

A 12-dB high-gain monolithic distributed amplifier

By reducing gate and drain line loss associated with the active elements of a distributed amplifier, significant gain improvements are possible. Loss reduction is achieved in a novel monolithic distributed amplifier by replacing the common-source FET's of the conventional design with cascode elements having a gate length of one-quarter micron. A record gain of over 10 dB from 2 to 18 GHz and a noise figure of 4 dB at 7 GHz have been achieved on a working amplifier. Details of the design and fabrication process are described.     

A 3-10-GHz low-noise amplifier with wideband LC-ladder matching network

Reactive matching is extended to wide bandwidths using the impedance property of LC-ladder filters. In this paper, we present a systematic method to design wideband low-noise amplifiers. An SiGe amplifier with on-chip matching network spanning 3-10 GHz delivers 21-dB peak gain, 2.5-dB noise figure, and -1-dBm input IP3 at 5 GHz, with a 10-mA bias current.     

The tapered matrix amplifier: a low-power high-gain broadband amplifier

A new distributed amplifier topology that offers greatly reduced power consumption is presented. The tapered matrix amplifier (TMA) originates from the combination of transmission line tapering and matrix cascading of distributed amplifiers. The design of a TMA is however complicated by contrasting requirements of the tapered lines, the lumped line approximation and the parasitics of the circuit components. Therefore, a pragmatic design approach leveraging circuit optimization is proposed to handle these complexities. As a proof of concept, a prototype broadband amplifier was implemented in a 90 nm bulk CMOS process. It features an average gain of 15.8 dB over the pass-band, stretching from DC to 22 GHz, while consuming only 12.9 mW of DC power. The average noise figure in the pass-band is 5.4 dB, and the average IIP3 is ?7.3 dBm. The die area occupied by the amplifier is only 0.31 mm². In addition, it is shown that the prototype design can be easily adapted for high linearity while keeping the increase in power consumption to a minimum.     

Design of a 32.7-GHz bandwidth AGC amplifier IC with wide dynamicrange implemented in SiGe HBT

A wide-bandwidth automatic gain control (AGC) amplifier IC was developed using a self-aligned selective-epitaxial SiGe heterojunction bipolar transistor (HBT). A transimpedance load circuit was used, and its damping factor was optimized to achieve a wide bandwidth of 32.7 GHz. Capacitor peaking was introduced to the second variable-gain amplifier in order to obtain a wide gain dynamic range of 19 dB. The amplifier IC has a noise figure of 18 dB and an eye pattern at 25 Gb/s     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.