Programmable VLSI cubic-like function implementation

An analogue VLSI implementation of a cubic-like function is presented, whose design is focused to reduce the circuit complexity. Simulations show that the V-I characteristic of the circuit resembles a cubic function, which can be easily adjusted by changing the bias parameters     

AES密码算法的VLSI实现

给出AES轮加密结构,详细分析MixColumns模块功能,提出基于VLSI实现的方案。用移位寄存器和异或单元代替有限域乘法模块,简化了电路的规模。在子密钥产生模块中,提出了根据密钥长度设计不同模块的方法,加快了芯片运行速度。     

VLSI implementation of discrete wavelet transform

This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is simple, modular, and cascadable for computation of one or multidimensional DWT. It comprises of four basic units: input delay, filter, register bank, and control unit. The proposed architecture is systolic in nature and performs both high- and low-pass coefficient calculations with only one set of multipliers. In addition, it requires a small on-chip interface circuitry for interconnection to a standard communication bus. A detailed analysis of the effect of finite precision of data and wavelet filter coefficients on the accuracy of the DWT coefficients is presented. The architecture has been simulated in VLSI and has a hardware utilization efficiency of 87.5%. Being systolic in nature, the architecture can compute DWT at a data rate of N×10⁶ samples/s corresponding to a clock speed of N MHz     

Design and VLSI implementation of QMF banks

The authors consider the design of multirate filterbanks for applications such as subband coding with IIR QMF (quadrature mirror filter) pairs. These offer reduced complexity and low latency at the expense of the loss of exact linear phase. In particular, consideration is given to the use of all-pass sections where linear phase is approximately achieved by being part of the objective in numerical optimisation experiments. This approach compares favourably with previous IIR based approaches. Finite wordlength design using simulated annealing shows that low coefficient wordlength may be used. This leads to efficient realisations with three-port adaptors. Using pipelining implementation, a flexible VLSI architecture is designed that can be used for a variety of subband decompositions. Layout and simulation of the design have been performed.     

具有多种工作模式的AES算法的VLSI实现

从结构和算法上对AES算法进行了分析和优化,在一个模块内集成了加密和解密功能,实现了AES算法的所有5种工作模式,使其能满足多种保密性应用的需求.仿真和综合结果表明,此设计结构较好的实现了面积与速度的折中.     

Analysis of pulse propagation on high-speed VLSI chips

A method for the analysis of lossy distributed interconnections on high-speed LSI/VLSI chips is presented. The method is based on a piecewise decomposition technique in which nonlinear branches are replaced by piecewise-linear time-dependent sources. Parameters of the piecewise-linear functions are computed iteratively so that the network's topological and constitutive relations are satisfied. Examples to illustrate the analysis algorithms are presented     

VLSI design and implementation fuels the signal-processingrevolution

The article provides a comprehensive overview of the history of how signal-processing researchers have been effectively transforming signal-processing algorithms into efficient implementations. Starting from the early days of analog circuits for signal processing, to digital signal processors (DSPs), to application specific DSPs and programmable DSPs, and to the trend of integrating a complete system on a single chip, this article provides a thorough coverage of the past and the present of design and implementation technology for signal processing systems. Moreover, it presents the exciting challenges faced by the study of the design and implementation of current and future signal processing applications. Topics covered include milestones in signal-processing integrated circuits, the past and future of the signal processor, signal processing in consumer applications, and design automation for signal processing     

Systolic array for VLSI implementation of realization techniques

A technique for implementing the realization algorithm from input-output data of the system directly in hardware is proposed. The proposed technique results in low cost, special purpose devices which can quickly solve realization problems. The systolic arrays for VLSI implementation of the different steps of the realization algorithm are developed.     

32位嵌入式RISC处理器的VLSI实现

本文实现了一个低功耗,高速度的32位RISC处理器。芯片采用了ARM V4的指令集,哈佛结构和五级流水线。同时利用了改进的流水冲突检测控制和异常处理使得流水线能以较高的速度顺序流动。与商用的ARM7TDMI相比,在0.6mm的工艺上达到了与商用0.35mm工艺制造相同的速度,同时CPI降低了26%,MIPS上升了36%。整个系统在APTIX公司提供的MP3CF硬件仿真器上完成了硬件验证,现已完成了版图设计并提交流片。     

一种适用于AVS自适应环路滤波器的VLSI实现

提出了一种新的适用于AVS自适应环路滤波器的VLSI实现。在实现时,采用了垂直滤波和水平滤波交叉进行的顺序,使得中间数据存储单元只需要存储两个8×8的块而不是整个宏块的数据,并且通过有效的控制机制,完成对一个宏块数据进行环路滤波仅需316个时钟周期,可以达到高清实时解码的要求。     

Architectures for VLSI implementation of movement-compensated video processors

Architecture elements suitable for VLSI implementation and real-time operation in movement-compensated video (MCV) processors are presented. The algorithm used in the video processor is based on motion estimation and compensation techniques. An overview of the algorithm is given with emphasis placed on one of the key functions used in the prediction, the two-dimensional interpolator. A VLSI implementation is presented which incorporates design techniques of pipelining, parallelism, and module replication. Furthermore, it is shown that modifications to the algorithm can be made based on the use of a high degree of parallelism yielding an efficient structure which relieves constraints for high-speed execution. The operations then rely on a simpler one-dimensional interpolator to form one of the building blocks of the two-dimensional interpolator. It is indicated that the parallel structure which is formed with these building blocks can be implemented on two circuits and that it can operate at speeds meeting real-time requirements.     

VLSI implementation of a CDMA blind adaptiveinterference-mitigating detector

This paper presents the design and the main performance results of a single-ASIC implementation of the recently proposed extended complex-valued blind anchored interference-mitigating detector (EC-BAID) for code division multiple access (CDMA) transmission. Such a detector, which exhibits a remarkable robustness to multiple access interference, operates in blind mode, i.e., it only requires knowledge of the timing of the wanted user's signature code, and it is therefore very well-suited for integration into handheld single-user terminal demodulators. The implementation of the interference-mitigating detector is based on a patented optimized architecture which leads, in 0.25-μm CMOS technology, to a roughly 25 Kgate plus 23-Kbit RAM single-chip ASIC supporting chip rates up to 4 Mchip/s with a maximum internal clock frequency of 32.768 MHz. The main design drivers are thoroughly discussed, and the relevant performance results are compared to the theoretical behavior. A possible extension to multirate CDMA systems adopting orthogonal variable spreading factor (OVSF) sequences is also addressed     

VLSI implementation of digital channeliser using distributed arithmetic

A VLSI architecture for a digital channeliser based on the time-multiplexed tree filter bank is described, in which the maximum sharing of the arithmetic operations at each stage is achieved. A very efficient implementation of the band-splitting filter is achieved by using distributed arithmetic, allowing a single chip design that does not require multipliers for an 8 channel channeliser.<>     

Soft-output sphere decoding: algorithms and VLSI implementation

Multiple-input multiple-output (MIMO) detection algorithms providing soft information for a subsequent channel decoder pose significant implementation challenges due to their high computational complexity. In this paper, we show how sphere decoding can be used as an efficient tool to implement soft-output MIMO detection with flexible trade-offs between computational complexity and (error rate) performance. In particular, we provide VLSI implementation results which demonstrate that single tree-search, sorted QR-decomposition, channel matrix regularization, log-likelihood ratio clipping, and imposing runtime constraints are the key ingredients for realizing soft-output MIMO detectors with near max-log performance at a chip area that is only 58% higher than that of the best-known hard-output sphere decoder VLSI implementation.     

Architecture-driven synthesis techniques for VLSI implementation ofDSP algorithms

The state of the art of compiling digital signal processing (DSP) algorithms into silicon is discussed. It is indicated how digital signal processing differs from numerical data processing, including the consequences for the synthesis tools. On the basis of a broad range of DSP applications, four classes of architectures are then distinguished to serve as templates for four different synthesis systems. Although each of these four silicon compilers is tuned to a specific class of applications in order to generate area-efficient chips, they all accept as input the same behavioral DSP specification. The four selected architectural styles are best characterized by hard-wired bit-serial data-paths, microcoded multiprocessors, cooperating bit-parallel data-paths, and regular arrays. The characteristics of the first three architectures are treated in more detail in a discussion of three different Cathedral synthesis environments for their respective design. A fourth Cathedral environment, aiming at the synthesis of regular arrays, is still in an early stage of development and is not discussed. The claims for the compilers are substantiated by typical designs     

Block-matching criterion for efficient VLSI implementation ofmotion estimation

A new block-matching motion estimation criterion is presented, which can be implemented in VLSI more efficiently than the conventional criterion. The proposed scheme can reduce the amount of hardware required and increase the speed of computation in a VLSI chip with acceptable video performance. Video performance and VLSI implementation using the proposed criterion are presented     

Novel Viterbi decoder VLSI implementation and its performance

An advanced, high-speed, and universal-coding-rate Viterbi decoder VLSI implementation is presented. Two novel circuit design schemes have been proposed: scarce state transition (SST) decoding and direct high-coding-rate convolutional code generation and variable-rate decoding. SST makes it possible to omit the final decision circuit and to reduce the required path memory length without degrading error probability performance. Moreover, the power consumption of the SST Viterbi decoder is significantly reduced when implemented as a CMOS device. These features overcome the speed limits of high-speed and high-coding-gain Viterbi decoder VLSIs in the rate one-half mode imposed by the thermal limitation. The other Viterbi decoding scheme makes it possible to realize a simple and variable coding-rate forward-error-correction circuit by changing only the branch metric calculation ROM tables. By employing these schemes, high-speed (25-Mb/s) and universal-coding-rate Viterbi decoder VLSIs have been developed     

A very fast multiplication algorithm for VLSI implementation

We present a simple recursive algorithm for multiplying two binary N-bit numbers in parallel O(log N) time. The simplicity of the design allows for a regular layout. The area requirement of this algorithm is comparable with that of much slower designs classically used in monolithic multipliers and in signal processing chips, hence the construction has definite practical impact.     

An all-CMOS ternary identity cell for VLSI implementation

A ternary identity cell composed only of CMOS transistors is presented. The circuit has fewer transistors and better performance than that of previously reported designs. A nano-watt power consumption and fast switching time are important advantages that this circuit possesses. Applications include buffers, pad drivers and triflops.