采用异步实现的快速傅里叶变换处理器

介绍一种采用异步实现结构的快速傅里叶变换处理器,该处理器的控制采用本地握手信号取代传统的系统时钟。给出了处理器中异步加法器的电路结构,设计了一个采用Booth译码Wallace tree结构的异步乘法器。通过对一个8点的异步快速傅里叶变换处理器进行电路仿真,得到该处理器完成一次变换的平均响应时间为31.15 ns,仅为最差响应时间42.85 ns的72.7%。可见,采用异步方式的快速傅里叶变换处理器在性能方面较同步处理器存在优势。     

ASIC中的异步时序设计

绝大部分ASIC设计工程师在实际工作中都会遇到异步设计的问题。文章针对异步时序产生的问题,介绍了几种同步的策略。特别是结绳法和异步FIFO的异步比较法,都是比较新颖的方法。     

An asynchronous neighbor discovery algorithm for wireless sensor networks

We consider the problem of determining, in a distributed, asynchronous and scalable manner, what nodes are “neighbors” in a wireless network. Neighbor discovery is an important enabler of network connectivity and energy conservation. An asynchronous, probabilistic neighbor discovery algorithm is presented that permits each node in the network to develop a list of its neighbors, which may be incomplete. The algorithm is analyzed and parameter settings are derived which maximize the fraction of neighbors discovered in a fixed running time. A companion distributed algorithm is also described which allows all the nodes in the network to execute that neighbor discovery algorithm without the need to agree on a common start time.     

Simple method of asynchronous circuits implementation in commercial FPGAs

This paper presents a simple implementation method of pipelined asynchronous circuits, suitable for commercial field programmable gate arrays (FPGAs). Contrary to other existing asynchronous design techniques, the presented method does not require the application of additional user actions such as constraining or building hard macros. As a design example, an architecture of the asynchronous PicoBlaze compatible microcontroller and 12-bit pipelined fast array multiplier have been considered. The developed synchronous and asynchronous versions of the microcontroller as well as fast array multiplier have been implemented and tested using Xilinx FPGAs, and then compared in terms of the area requirement, power consumption and performance.     

Public integrity verification for data sharing in cloud with asynchronous revocation

Cloud data sharing service, which allows a group of people to access and modify the shared data, is one of the most popular and efficient working styles in enterprises. Recently, there is an uprising trend that enterprises tend to move their IT service from local to cloud to ease the management and reduce the cost. Under the new cloud environment, the cloud users require the data integrity verification to inspect the data service at the cloud side. Several recent studies have focused on this application scenario. In these studies, each user within a group is required to sign a data block created or modified by him. While a user is revoked, all the data previously signed by him should be resigned. In the existing research, the resigning process is dependent on the revoked user. However, cloud users are autonomous. They may exit the system at any time without notifying the system admin and even are revoked due to misbehaviors. As the developers in the cloud-based software development platform, they are voluntary and not strictly controlled by the system. Due to this feature, cloud users may not always follow the cloud service protocol. They may not participate in generating the resigning key and may even expose their secret keys after being revoked. If the signature is not resigned in time, the subsequent verification will be affected. And if the secret key is exposed, the shared data will be maliciously modified by the attacker who grasps the key. Therefore, forcing a revoked user to participate in the revocation process will lead to efficiency and security problems. As a result, designing a practical and efficient integrity verification scheme that supports this scenario is highly desirable. In this paper, we identify this challenging problem as the asynchronous revocation, in which the revocation operations (i.e., re-signing key generation and resigning process) and the user's revocation are asynchronous. All the revocation operations must be able to be performed without the participation of the revoked user. Even more ambitiously, the revocation process should not rely on any special entity, such as the data owner or a trusted agency. To address this problem, we propose a novel public data integrity verification mechanism in which the data blocks signed by the revoked user will be resigned by another valid user. From the perspectives of security and practicality, the revoked user does not participate in the resigning process and the re-signing key generation. Our scheme allows anyone in the cloud computing system to act as the verifier to publicly and efficiently verify the integrity of the shared data using Homomorphic Verifiable Tags (HVTs). Moreover, the proposed scheme resists the collusion attack between the cloud server and the malicious revoked users. The numerical analysis and experimental results further validate the high efficiency and scalability of the proposed scheme. The experimental results manifest that re-signing 10,000 data blocks only takes 3.815 ?s and a user can finish the verification in 300 ?ms with a 99% error detection probability.     

Asynchronous switching for low-power networks-on-chip

Asynchronous switching is proposed to achieve low power Network on Chip. Asynchronous switching reduces the power dissipation of the network if the activity factor of the data transfer between two ports α_data is less than Aα_c+Bα_clk. Closed form expressions for power dissipation of different network topologies are provided for both synchronous and asynchronous switching. The expressions are technology independent and are used for power estimation. Asynchronous switching is compared with synchronous switching for different network densities N/L_cXL_c. The area of the asynchronous switch is 50% greater than the area of the synchronous switch. However, the power dissipation of asynchronous switching decreased by up to 70.8% as compared to the power dissipation of the conventional synchronous switching for Butter-Fly Fat Tree (BFT) topology. Asynchronous switching is more efficient in CLICHE topology than in both BFT and Octagon topologies achieving higher power reduction 75.7%. Asynchronous switching becomes more efficient as technology advances and network density increases. A reduction in power dissipation reaches 82.3% for 256 IPs with the same chip size. Even with clock gating, asynchronous switching achieves significant power reduction 77.7% for 75% clock activity factor.     

3WDSPl00高速链路口模块的设到

本文介绍了BWDSPl00芯片的高速互联接口——链路口的实现方法，功能验证结果表明，模块功能覆盖率和代码覆盖率均达到100％，符合设计要求。同时给出了流片后BWDSPl00芯片和FPGA链路口互联测试结果，结果表明300MHz下模块功能正确且传输稳定可靠。     

一种微机异步通信网络PC—TALK的实现

本文介绍了一种微机异步通信网络。该网价格低谦、通信功能完善，可以实现文件传送、文件猎取、电子邮件、图形、表格传送等多种功能，是一种在通信速率要求不高、数据传送不是太频繁的情况下，实现近远程通信的理想网络系统。     

ASIC设计中的同步复位与异步复位

复位问题是ASIC设计中的一个关键问题,其处理得当与否将直接影响整个电路的性能,在此本文从多个角度对同步复位和异步复位进行了讨论和分析,并且比较了各自的优缺点,重点针对异步复位过程中存在的亚稳态问题采用两级复位同步和复位分配缓冲树的方法进行了相应的解决.     

高压变频调速技术及其在电厂中的应用

文章在简单分析了高压变频器技术特点的基础上,详细分析了影响高压变频器选用所必须考虑的技术因素,以及采用高压变频器的经济性。     

Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs

Asynchronous serial transceivers have been recently used for data serializing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the asynchronous serial transmission but they have serious challenges to use this technology. In this paper, we present a new FPGA architecture corresponding with a new routing algorithm to use the asynchronous data serializing technique in modern FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (18.81% and 48.73%, respectively) by using the asynchronous data serializing without any performance degradation in cost of reasonable overhead in area and power consumption. The resulting improvements will increase for larger and more complex FPGAs.     

恒转矩工作的电力传动中变频器的选择

在恒定转矩工作和频繁起动的可变速电力传动中,对变频器的选型问题进行了研究,并提出了评估变频器功率损耗的数学模型,通过实验,验证了数学模型的适用性。     

基于功率因数闭环控制的异步电动机软起动器的研究

异步电动饥起动电流过大将对电网造成很大的冲击，本文在分析异步电动机功率刚数角特性的基础上，以电机的功率因数角作为系统的反馈量进行闭环控制，避免了在电机起动过程中．由于电机端门输入电压的变化引起的电磁转矩振荡及电流振荡，保障了电机电压按预期的规律进行例节。实验结果证明了该方法的有效性.     

Asynchronous particle filter for tracking using non-synchronous sensor networks

This paper deals with the problem of tracking using a sensor network when the sensors are not synchronised. We propose a new algorithm called the asynchronous particle filter that, with much less computational burden than the traditional particle filter, has a slightly poorer performance. Thus, it is a good solution to real-time applications with non-synchronised sensors when high performance is required. The low computational burden of the method lies in the fact that we do not predict and update the state every time a measurement is collected. Its high performance is due to the fact that we account for the time instant at which each measurement was taken.     

无模型控制方法在异步电动机控制中的仿真研究

在异步电动机的转差频率矢量控制中,其控制不需要复杂的磁通检测,且运算和控制简单,因而在基频以下的调速系统中得到较多的应用。但该系统存在比较明显的缺陷。基于此,本文设计了一种无模型自适应控制器,将该控制器引入原系统,与原系统构成前馈补偿。仿真试验表明,该方法有效减小了转矩脉动,改善了定子电流波形,具有良好的动、静态性能。     

一种软起动装置的研究

本文对矿用软起动装置的主电路进行了设计并阐述了软起动装置的工作原理：对晶闸管的电压等级和电流等级进行了分析计算和选型：并且给出了晶闸管的过电压保护、过电流保护、过热保护、主电路与控制电路之间的电气隔离等。并介绍了针对本装置进行的相关检验检测数据和结论。检测结果表明本文所做研究和设计的可行性与正确性。     

技术趋于统一 业务走向综合：从Cebit‘94看世界电信与计算机技术的发展

今天的世界电信界和计算机界正处在一个飞速发展的变化时期,高技术日新月异,新产品层出不穷。面对这样一个技术与产品令人眼花缭乱的形势,如何把握世界电信与计算机技术发展的主旋律,看准市场方向,已成为大家非常关心的问题。作者于今年3月下旬赴德国现代科技城汉诺威参加了Cebit’94——国际电信与计算机产品展览会,本文介绍了Cebit’94所展示的最新技术和产品,并围绕当今电信与计算机工业一些主要的技术发展热点进行了讨论。     

基于DSP的异步电机矢量控制

矢量控制是一种高性能的交流电机控制方法,具有控制转矩小,电流谐波成分少等优点。本文介绍了一种以TI公司的TMS320F2812为核心的基于矢量控制变频调速系统设计,描述了各硬件功能单元的组成结构和设计特点,并给出了设计方案和软硬件的设计方法。     

三相异步电机损耗及运行效率的在线测量

针对目前测量电机效率需要先停机、进行负载分离以便进行空载试验、堵转实验、测试成本较高、对生产影响大、不能提供实时数据的特点,提出了一种异步电机效率测量的新方法.不需进行空载试验、堵转实验,能在不停机的情况下进行效率的测量。该方法使用一种测量仪器在线测量定子功率因数,使用变频器获取电机运行效率模型参数,求得电机效率,     

Asynchronous control of modules activity in integrated systems for reducing peak temperatures

The paper describes a new control method of integrated circuit (IC) modules activity in a modern processor design. The control method leads to improved frequency ability of integrated systems. The proposed solution, based only on computing flow modification, could be easily integrated into all future designs, ranging from a portable computing to a multi-core computing. A new approach to the thermal control method is described along with simulation results. An example of incorporation in current and future integrated circuits into mainstream designs is presented with exemplary algorithms and final simulation results.