Breakdown voltage analysis for the new RESURF AlGaN/GaN HEMTs

This paper demonstrates that the depletion process for AlGaN/GaN high electron mobility tran-sistors(HEMTs)is different than that for silicon power devices by analyzing active region depletion.Based on the special breakdown principle that occurs in AlGaN/GaN HEMTs,we propose a new reduced surface field AlGaN/GaN HEMT with a double low-density drain(LDD)and a positively charged region near the drain to optimize the surface electric field and increase the breakdown voltage.In this structure,two negative charge regions with different doses are introduced into the polarization AlGaN layer to form a double LDD and decrease the high electric field near the gate by depleting two-dimensional electron gas.A positively charged region is added to the electrode near the drain to decrease the high electric field peak at the drain edge.By applying ISE(integrated systems engineering)simulation software,we verify that the virtual gate effect occurs in the AlGaN/GaN HEMTs.The breakdown voltage is improved from 257 V in the conventional structure to 550 V in the proposed structure.     

Novel high voltage RESURF AlGaN/GaN HEMT with charged buffer layer

A novel reduced surface field (RESURF) Al GaN /GaN high electron mobility transistor(HEMT)with charged buffer layer is proposed. Its breakdown mechanism and on-state characteristics are investigated.The HEMT features buried Fluorine ions in the GaN buffer layer both under the Drift and the Gate region (FDG). The section of FDG under the drift region (FD) not only reduces the electric field (E-field) peak at the gate edge but also enhances the E-field in the drift region by the assisted depletion, leading to a significant improvement in breakdown voltage (BV). Moreover, the section of FDG under the gate (FG) enhances the back barrier and effectively prevents electron injecting from the source to form leakage current, thus a higher BV is achieved. The BV of the proposed HEMT sharply increases to 750 V from 230 V of conventional AlGaN /GaN HEMT with the same dimensional parameters, and the specific on-resistance (Ron,sp) just increases to1.21 m?·cm~2from 1.01 m?·cm~2.     

Growth and characterization of 0.8-μm gate length AlGaN/GaN HEMTs on sapphire substrates

AlGaN/GaN high electron mobility transistor (HEMT) structures were grown on 2 inch sapphire substrates by MOCVD, and 0.8-μm gate length devices were fabricated and measured. It is shown by resistance mapping that the HEMT structures have an average sheet resistance of approximately 380 Θ/sq with a uniformity of more than 96%. The 1-mm gate width devices using the materials yielded a pulsed drain current of 784 mA/mm atV _gs=0.5 V andV _ds=7 V with an extrinsic transconductance of 200 mS/mm. A 20-GHz unity current gain cutoff frequency (f _T) and a 28-GHz maximum oscillation frequency (f _max) were obtained. The device with a 0.6-mm gate width yielded a total output power of 2.0 W/mm (power density of 3.33 W/mm) with 41% power added efficiency (PAE) at 4 GHz.     

新型RESURF AlGaN/GaN HEMTs器件耐压分析

本文首先从器件有源区耗尽过程分析表明AlGaN/GaN HEMTs器件具有与传统Si功率器件不同的耗尽过程,针对AlGaN/GaN HEMTs器件特殊的耐压机理,提出了一种降低表面电场,提高击穿电压的新型RESURF AlGaN/GaN HEMTs结构.新结构通过在极化的AlGaN层中引入分区负电荷,辅助耗尽二维电子气,有效降低了引起器件击穿的栅极边缘高电场,并首次在漏极附近引入正电荷使漏端高电场峰降低.利用仿真软件ISE分析验证了AlGaN/GaN HEMTs器件具有的"虚栅"效应,通过电场和击穿特性分析获得,新结构使器件击穿电压从传统结构的257V提高到550V.     

A simplification method for capacitance models in AlGaN/GaN high electron mobility transistors under large drain voltage using channel analysis

This article analyzes the bias dependence of gate‐drain capacitance (C_gd) and gate‐source capacitance (C_gs) in the AlGaN/GaN high electron mobility transistors under a high drain‐to‐source voltage (V_ds) from the perspective of channel shape variation, and further simplifies C_gd and C_gs to be gate‐to‐source voltage (V_gs) dependent only at high V_ds. This method can significantly reduce the number of parameters to be fitted in C_gd and C_gs and therefore lower the difficulty of model development. The Angelov capacitance models are chosen for verifying the effectiveness of simplification. Good agreement between simulated and measured small‐signal S‐parameters, large‐signal power sweep, and power contours comprehensively proves the accuracy of this simplification method.     

Look-up table based I-V model for GaN HEMT devices for Microwave Applications

In this work, a newly found innovative interposable lookup table based nonlinear empirical DC I-V model for GaN HEMT device has been formulated. Angelov and Yang's models have been taken as reference models to study the effects of bias (V_gs, V_ds) dependent traps (gate lag and drain lag), self-healing, virtual gate formation, etc. on I-V characteristics functions and their inclusion into I-V equation functions of the proposed model. A new polynomial ratio function of V_ds with its coefficients varying with V_gs has been formulated as a first function of the I-V model equation, to describe the transfer characteristics of the GaN HEMT. The obtained coefficients of the polynomial ratio function have been calculated by the curve fitting tool, are used to form a look-up table so that the I-V model is fast and accurate. Model verification has been done using 8 × 75 µm gate periphery and 0.25 µm gate length GaN HEMT of UMS foundry. The measured and modeled results of I-V characteristics as well as transfer characteristics are compared and found to be matched accurately with each other. Because of this, this model is more accurate and proficient in the representation of GaN HEMT I-V characteristics when compared to the Angelov DC I-V model. The proposed methodology can be used to model all GaN HEMT devices.Using the proposed nonlinear I-V equation, an empirical model has been generated in AWR MWO using an interpolable lookup table of coefficients varying with V_gs for the GaN HEMT of UMS, CREE and WIN foundry, which can be used for Computer-Aided Design (CAD) of RF circuits, etc.     

A physics‐based model of DC and microwave characteristics of GaN/AlGaN HEMTs

A physics‐based model of AlGaN/GaN High Electron Mobility Transistor (HEMT) is developed for the analysis of DC and microwave characteristics. Large‐ and small‐signal parameters are calculated for a given device dimensions and operating conditions. Spontaneous and piezoelectric polarizations at the heterointerface and finite effective width of the 2DEG gas have been incorporated in the analysis. The model predicts a maximum drain current of 523 mA/mm and transconductance of 138 mS/mm for a 1 μm × 75 μm device, which are in agreement with the experimental data. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

Genetic algorithm‐based neural‐network modeling approach applied to AlGaN/GaN devices

An accurate equivalent circuit large‐signal model (ECLSM) for AlGaN‐GaN high electron mobility transistor (HEMT) is presented. The model is derived from a distributed small‐signal model that efficiently describes the physics of the device. A genetic neural‐network‐based model for the gate and drain currents and charges is presented along with its parameters extraction procedure. This model is embedded in the ECLSM, which is then implemented in CAD software and validated by pulsed and continuous large‐signal measurements of on‐wafer 8 × 125‐μm GaN on SiC substrate HEMT. Pulsed IV simulations show that the model can efficiently describe the bias dependency of trapping and self‐heating effects. Single‐ and two‐tone simulation results show that the model can accurately predict the output power and its harmonics and the associated intermodulation distortion (IMD) under different input‐power and bias conditions. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013.     

Flexible color LCD panel driven by low‐voltage‐operation organic TFT

Abstract— A flexible color LCD panel driven by organic TFTs (OTFTs) was successfully demonstrated. A pentacene OTFT with an anodized Ta₂O₅ gate insulator, which can be operated at low voltage, was developed. In order to improve the electrical performance of the OTFT, the gate insulator was surface treated by processes such as O₂ plasma, UV light irradiation, and hexamethyldisilane treatments. The fabricated OTFT exhibited a mobility of 0.3 cm²/V‐sec and a current on/off ratio of 10⁷ with a low operating drain voltage of ?5 V. A fast‐response‐time flexible ferroelectric LCD, which contains polymer networks and walls, was integrated with the OTFTs by using a lamination and a printing technique. As a result, color images were achieved on the fabricated panel by using a field‐sequential‐color method at a low driving voltage of less than 15 V_pp.     

Characterization of a SAG‐InGaN/AlGaN LED by mixed‐source HVPE with a multi‐sliding boat system

Abstract— The selective area growth (SAG) of a InGaN/AlGaN light‐emitting diode (LED) is performed by using mixed‐source hydride vapor‐phase epitaxy (HVPE) with a multi‐sliding boat system. The SAG‐InGaN/AlGaN LED consists of a Si‐doped AlGaN cladding layer, an InGaN active layer, a Mg‐doped AlGaN cladding layer, and a Mg‐doped GaN capping layer. The carrier concentration of the n‐type Al_xGa_1?xN (x ～ 16%) cladding layer depends on the amount of poly‐Si placed in the Al‐Ga source. The carrier concentration is varied from 2.0 × 10¹⁶ to 1.1 × 10¹⁷ cm^?3. Electroluminescence (EL) characteristics show an emission peak wavelength at 426 nm with a full width at half‐maximum (FWHM) of approximately 0.47 eV at 20 mA. It was found that the mixed‐source HVPE method with a multi‐sliding boat system is a candidate growth method for III‐nitride LEDs.     

Fabrication of poly‐Si complementary metal oxide semiconductor inverter by all sputtering deposition process

Direct current sputtering was used for deposition of Si film for precursor film of excimer laser annealing, n⁺‐Si/p⁺‐Si film for source/drain contact, and SiO₂ film for gate insulator of polycrystalline silicon thin‐film transistor. Using these methods, poly‐Si thin‐film complementary metal oxide semiconductor inverter was fabricated by all sputtering process for the first time. The field‐effect mobility was, respectively, 6.5 and 12.5 cm²/Vs for n‐TFTs and p‐TFTs. This inverter exhibits a full rail‐to‐rail swing and abrupt voltage transfer characteristics over the entire voltage range, and the output voltage gain was ~117 at V_dd = 20 V.     

High performance a‐IGZO thin‐film transistors with mf‐PVD SiO2 as an etch‐stop‐layer

In this work, we report on high‐performance bottom‐gate top‐contact (BGTC) amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin‐film transistor (TFT) with SiO₂ as an etch‐stop‐layer (ESL) deposited by medium frequency physical vapor deposition (mf‐PVD). The TFTs show field‐effect mobility (μ_FE) of 16.0 cm²/(V.s), sub‐threshold slope (SS^?1) of 0.23 V/decade and off‐currents (I_OFF) < 1.0 pA. The TFTs with mf‐PVD SiO₂ ESL deposited at room temperature were compared with TFTs made with the conventional plasma‐enhanced chemical vapor deposition (PECVD) SiO₂ ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μ_FE, SS^?1, and I_OFF, however, significant differences were measured in gate bias‐stress stability when stressed under a gate field of +/?1 MV/cm for duration of 10⁴ s. The TFTs with mf‐PVD SiO₂ ESL showed lower threshold‐voltage (V_TH) shifts compared with TFTs with 300 °C PECVD SiO₂ ESL and TFTs with 200 °C PECVD SiO₂ ESL. We associate the improved bias‐stress stability of the mf‐PVD SiO₂ ESL TFTs to the low hydrogen content of the mf‐PVD SiO₂ layer, which has been verified by Rutherford‐Back‐Scattering‐Elastic‐Recoil‐Detection technique.     

Charge density and bare surface barrier height in GaN/AlGaN/GaN heterostructures: A modeling and simulation study

In this article, we present a physics‐based model to explain the effect of the GaN cap layers on the 2D electron gas density and the bare surface barrier height in AlGaN/GaN heterostructures. We consider that the 2DEG originates from the surface donor states present on the GaN cap top surface. The influence of a 2D hole gas, formed when the valence band crosses the Fermi energy level, has also been considered. This model agrees well with the published experimental results and TCAD simulations, and can easily be incorporated into the modeling of GaN/AlGaN/GaN‐based HEMT devices.     

Efficiency‐enhanced Doherty power amplifier using Chireix‐like compensation technology

This article presents a novel efficiency‐enhanced Doherty power amplifier (DPA) by using a Chireix‐like compensation technique. This technique introduces a compensation circuit structure at the combiner to offset the phase difference effect of a DPA for enhancing drain efficiency. A DPA based on the proposed structure is fabricated with two 10 W GaN high electron mobility transistor (HEMT) transistors. The fabricated DPA with such proposed compensation structure manifests a measured saturated output power of 43.5 dBm and drain efficiency of 68% to 71% in the frequency range of 3.2 to 3.7 GHz. Forty‐five percent of drain efficiency can be achieved at 6 dB power back‐off. And the adjacent channel leakage ratio (ACLR) is better than ?48.6 dBc with digital predistortion.     

Hybrid small‐signal model parameter extraction of GaN HEMTs on Si and SiC substrates based on global optimization

This article presents efficient parameters extraction procedure applied to GaN High electron mobility transistor (HEMT) on Si and SiC substrates. The method depends on combined technique of direct and optimization‐based to extract the elements of small‐signal equivalent circuit model (SSECM) for GaN‐on‐Si HEMT. The same model has been also applied to GaN‐on‐SiC substrate to evaluate the effect of the substrates on the model parameters. The quality of extraction was evaluated by means of S‐parameter fitting at pinch‐off and active bias conditions.     

New small‐signal extraction method applied to GaN HEMTs on different substrates

In this article, a new extraction technique is proposed to extract the small‐signal parameters of gallium nitride (GaN) high electron mobility transistors (HEMTs) on three different substrates namely, Si, SiC, and Diamond. This extraction technique used a single small‐signal circuit model to efficiently describe the physical and electrical properties of GaN on different substrates. This technique takes into account any asymmetry between the gate‐source and gate‐drain capacitances on the asymmetrical GaN HEMT structure, charge‐trapping effects, passivation layer inclusion, as well as leakage currents associated with the nucleation layer between the GaN buffer layer and the different substrates. The extracted values were then optimized using the grey wolf optimizer. The proposed technique was demonstrated through a close agreement between simulated and measured S‐parameters.     

Bayesian inference‐based small‐signal modeling technique for GaN HEMTs

A new modeling methodology for gallium nitride (GaN) high‐electron‐mobility transistors (HEMTs) based on Bayesian inference theory, a core method of machine learning, is presented in this article. Gaussian distribution kernel functions are utilized for the Bayesian‐based modeling technique. A new small‐signal model of a GaN HEMT device is proposed based on combining a machine learning technique with a conventional equivalent circuit model topology. This new modeling approach takes advantage of machine learning methods while retaining the physical interpretation inherent in the equivalent circuit topology. The new small‐signal model is tested and validated in this article, and excellent agreement is obtained between the extracted model and the experimental data in the form of dc I–V curves and S‐parameters. This verification is carried out on an 8 × 125 μm GaN HEMT with a 0.25 μm gate feature size, over a wide range of operating conditions. The dc I–V curves from an artificial neural network (ANN) model are also provided and compared with the proposed new model, with the latter displaying a more accurate prediction benefiting, in particular, from the absence of overfitting that may be observed in the ANN‐derived I–V curves.     

Characteristics of a‐IZO TFTs with high‐κ HfSiOx gate insulator annealed in various conditions

In this work, we investigate the enhanced performance of amorphous indium zinc oxides‐based thin film transistors with hafnium silicate (HfSiO_x) gate insulators. HfSiO_x gate insulators annealed at various conditions are deposited by cosputtering of hafnium oxide and Si. The structural properties of HfSiO_x are investigated using the atomic force microscopy, X‐ray diffraction, and x‐ray photoelectron spectroscopy (XPS). techniques. Furthermore, the electrical characteristics of HfSiO_x are analyzed to investigate the effect of annealing conditions. We obtain optimal results for thin film transistors with HfSiO_x gate insulators annealed for 1 h at 100 °C, with a saturation mobility of 1.2 cm²/V · s, threshold voltage of 2.2 V, on current/off current ratio of 2.0 × 10⁶, and an insulator surface roughness of 0.187 nm root mean square.     

Neuro‐space mapping modeling approach for trapping and self‐heating effects on GaAs and GaN devices

In recent years, neural networks have been successfully applied for modeling the nonlinear microwave devices as GaAs and GaN MESFETs/HEMTs. Many modeling approaches have been developed for small and large signal applications. In this contribution, a neuro‐space mapping approach is proposed for modeling the trapping and the self‐heating effects on GaAs and GaN devices. The Angelov empirical model is used as the coarse model, which can be adjusted using DC and Pulsed I/V measurements at different static bias points. The proposed approach is tested for the MGF1923 GaAs MESFET and for an AlGaN/GaN HEMT. DC and transient simulation results are compared to DC and Pulsed I/V measurements. Good results are obtained for the DC and dynamics I/V characteristics at different static bias points.     

Circuits and AMOLED display with self‐aligned a‐IGZO TFTs on polyimide foil

A process to make self‐aligned top‐gate amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) on polyimide foil is presented. The source/drain (S/D) region's parasitic resistance reduced during the SiN interlayer deposition step. The sheet resistivity of S/D region after exposure to SiN interlayer deposition decreased to 1.5 kΩ/□. TFTs show field‐effect mobility of 12.0 cm²/(V.s), sub‐threshold slope of 0.5 V/decade, and current ratio (I_ON/OFF) of >10⁷. The threshold voltage shifts of the TFTs were 0.5 V in positive (+1.0 MV/cm) bias direction and 1.5 V in negative (?1.0 MV/cm) bias direction after extended stressing time of 10⁴ s. We achieve a stage‐delay of ~19.6 ns at V_DD = 20 V measured in a 41‐stage ring oscillator. A top‐emitting quarter‐quarter‐video‐graphics‐array active‐matrix organic light‐emitting diode display with 85 ppi (pixels per inch) resolution has been realized using only five lithographic mask steps. For operation at 6 V supply voltage (V_DD), the brightness of the display exceeds 150 cd/m².