低功耗低噪声CMOS放大器设计与优化

分析了两种传统的基于共源共栅结构的低噪声放大器LNA技术:实现噪声优化和输入匹配SNIM技术并在功耗约束下同时实现噪声优化和输入匹配PCSNIM技术。针对其固有不足,提出了一种新的低功耗、低噪声放大器设计方法。     

A miniature low‐power ultra‐wideband low noise amplifier in 0.18 μm CMOS

A 0.18‐μm CMOS low‐noise amplifier (LNA) operating over the entire ultra‐wideband (UWB) frequency range of 3.1–10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 ± 2.5 dB, minimum input matching of ?8 dB, noise figure from 3.9 to 6.3 dB, and IIP3 from ?8 to ?1.9 dBm, while consuming only 9 mW over 3–10 GHz. It occupies only 0.55 × 0.4 mm² without RF and DC pads. The design uses only two on‐chip inductors, one of which is such small that could be replaced by a bonding wire. The gain, noise figure, and matching of the amplifier are also analyzed. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.     

Analysis and design of a fully integrated CMOS low‐noise amplifier for concurrent dual‐band receivers

This article thoroughly analyzes a concurrent dual‐band low‐noise amplifier (LNA) and carefully examines the effects of both active and passive elements on the performance of the dual‐band LNA. As an example of the analysis, a fully integrated dual‐band LNA is designed in a standard 0.18‐μm 6M1P CMOS technology from the system viewpoint for the first time to provide a higher gain at the high band in order to compensate the high‐band signal's extra loss over the air transmission. The LNA drains 6.21 mA of current from a 1.5‐V supply voltage and achieves voltage gains of 14 and 22 dB, input S₁₁ of 15 and 18 dB, and noise figures of 2.45 and 2.51 dB at 2.4 and 5.2 GHz, respectively. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

Hybrid Ku‐band low‐noise amplifier for mobile DBS active phased‐array antennas

In this article we present a two‐stage Ku‐band low‐noise amplifier (LNA) using discrete pHEMT transistors on non‐PTFE substrates for low‐cost direct broadcast satellite (DBS) phased‐array systems (patent pending). The vertical input configuration of the LNA lends itself to direct integration with input port of antenna modules of the phased array, which minimizes preamplification losses. DC decoupling between LNA stages is realized using interdigital microstrip capacitors such that the implementation reduces the number of discrete microwave components and thereby not only reduces the component and assembly costs but also decreases the standard deviation of such crucial parameters of phased‐array systems as the end‐to‐end phase shift of the amplifier and the amplifier gain. Using the proposed printed decoupling capacitors, a cost reduction better than 30% of the original costs has been achieved. Additionally, we present a hybrid design procedure for the complete LNA, including its input and output connectors as well as packaging effects. This method is not based on parameter extraction, but encompasses electromagnetic (EM) field simulator results which are further combined using a high‐level circuit simulator. According to the presented measurement results, the implemented Ku‐band LNA has a noise figure better than 0.9 dB and a gain higher than 20 dB with a gain flatness of 0.3 dB over a 5% bandwidth. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

Alternative approach to low‐noise amplifier design for ultra‐wideband applications

Conventional ultra‐wideband low‐noise amplifiers require a flat gain over the entire 3.1–10.6 GHz bandwidth, which severely restraints the trade‐off spaces in low noise amplifier design. This article proposes a relaxed gain‐flatness requirement based on system level investigations. Considering the wireless transceiver front‐end with antenna and propagation channel, the unflat‐gain low‐noise amplifier with an incremental gain characteristic does not degrade the performance of overall system. As an alternative to its flat‐gain counterpart, the proposed unflat gain requirement tolerates gain ripple as large as 10 dB, which greatly eases the design challenges to low‐noise amplifier for ultra‐wideband wireless receivers. Two low‐noise amplifier examples are given to demonstrate the feasibility and design flexibility under the proposed gain‐flatness requirement. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

A 3.4 dB NF k‐band LNA with a tapped capacitor matching network in 65 nm CMOS technology

This article proposes a tapped capacitor network for low‐noise amplifier (LNA) input matching which can provide much broader bandwidth than traditional ones. According to the design, the implemented LNA can realize noise match and power match simultaneously, which will broaden LNA's bandwidth without introducing larger noise than traditional ones. In addition, input pad parasitic capacitance can be absorbed by the network. Then a k‐band LNA with the matching network designed in 65 nm CMOS technology is shown to demonstrate the performance of the matching network. The tested results show that frequency band of S₁₁ less than ?10 dB is about 17 GHz and minimum NF is about 3.4 dB. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:146–153, 2015.     

A low-noise fully-differential CMOS preamplifier for neural recording applications

A fully-differential bandpass CMOS preamplifier for extracellular neural recording is presented in this paper.The capacitive-coupled and capacitive-feedback topology is adopted.We describe the main noise sources of the proposed preamplifier and discuss the methods for achieving the lowest input-referred noise.The preamplifier has a midband gain of 43 dB and a DC gain of 0.The-3 dB upper cut-off frequency of the preamplifier is 6.8 kHz.The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands.It has an input-referred noise of 3.36 μVrms integrated from 1 Hz to 6.8 kHz for recording the local field potentials(LFPs)and the mixed neural spikes with a power dissipation of 24.75 μW from 3.3 V supply.When the passband is configured as 100 Hz-6.8 kHz for only recording spikes,the noise is measured to be 3.01 μVrms.The 0.115 mm2 prototype chip is designed and fabricated in 0.35-μm N-well CMOS(complementary metal oxide semiconductor)2P4M process.     

Design and implementation of a dual‐band concurrent fully‐integrated LNA for WLAN IEEE 802.11a/b/g applications

This article presents a dual‐band concurrent fully‐integrated low‐noise amplifier (LNA) targeted to WLAN IEEE 802.11a/b/g standards. The use of a concurrent topology enables saving die area and power consumption compared with the parallel solution that employs two separated LNAs. An original design methodology that helps in the selection of input/output matching network element values is also presented. The LNA die area is 1.0 × 0.9 mm² and it consumes 9 mW (5 mA at 1.8 V). © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Analysis and design of packaged and ESD protected BiCMOS RF front‐end for a UHF receiver

The design of packaged and ESD protected RF front‐end circuits for UHF receiver working at ISM band is presented. By extensively evaluating the effects of the package and ESD parasitics on the LNA input impedance, transconductance, and noise figure, some useful guidelines on the design of inductively degenerated common emitter LNA with package and ESD protection are provided. In addition, by taking advantage of both the bipolar and MOSFET devices, a BiFET mixer with low noise and high linearity is also described in this article. With the careful consideration of the tradeoffs among noise figure, linearity, power gain, and power consumption, the front‐end is implemented in a generic low‐cost 0.8‐μm BiCMOS technology. The on‐board measurement of the packaged RF front‐end circuits demonstrates a 20.3‐dB power gain, 2.6‐dB DSB noise figure, and ?9.5‐dBm input referred third intercept point while consuming about 3.9‐mA current. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

A reconfigurable DCS1800/W‐CDMA LNA: Design and implementation issues

The authors present in this article a dual‐standard dual‐mode low‐noise amplifier (LNA) for DCS1800/W‐CDMA‐FDD applications. To save die area compared to conventional parallel LNAs, the authors have employed an alternative circuit configuration. It consists of sharing the most die consuming elements (inductances) in both operation standards, enabling a more compact solution. The standard selection is performed through a bias scheme (MOS switches) that allows alternating between the two involved standards. The LNA die area is 1.0 × 1.2 mm² and it consumes 6.8 mW (3.8 mA under 1.8 V), including bias circuitry. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

A highly integrated AMLCD with low‐voltage operation

A highly integrated low‐temperature polysilicon AMLCD has been designed that operates from a 3‐V power supply and has a low‐voltage digital interface. This has been achieved by reducing the threshold voltage of the TFTs and integrating digital column drive circuits and charge‐pump circuits onto the display substrate. In standby mode, the display is capable of retaining an image without the need for external signals through the integration of dynamic‐memory circuits within the pixels of the display.     

Planar antenna beam deflection using low‐loss metamaterial for future 5G applications

A method to tilt the beam of a planar antenna in the E‐plane is demonstrated by implementing a metamaterial (MM) structure onto the antenna substrate at the fifth‐generation (5G) band of 3.5 GHz. The beam tilting is achieved due to the phase change that occurs when the electromagnetic (EM) wave traverses through two media with different refractive indices. A new adjacent square‐shaped resonator (ASSR) structure is proposed to achieve the beam tilting in a dipole antenna. This structure provides a very low loss of ?0.2 dB at 3.17 GHz. The simulation and measurement results illustrate that the radiation beam of the dipole antenna is tilted by +25° and ?24° depending on the position of the ASSR array onto the dipole antenna substrate. In addition, no degradation in the gain is observed as in the conventional beam‐tilting methods; in fact, gain enhancement values of 3 dB (positive deflection) and 2.7 dB (negative deflection) are obtained compared with that of a dipole antenna with no ASSR array. The reflection coefficient of the dipole antenna with ASSR array has a good agreement with that of the dipole antenna with no ASSR array. The measured results agree well with the simulated ones.     

基于物联网与互联网的电动车充电系统设计

为了提高电动车充电的安全性与稳定性,该文设计了一种基于物联网互联网的电动车充电系统,系统主要由网络层、控制层与使用层构成,具有电路监控、过载保护及插座防拔功能。系统选用STM32F407作为主控芯片,利用ESP8266进行TCP网络通讯,用户通过APP(用户终端),可以实时获取充电系统的功率值且可对充电系统下达通电、断电及开锁指令,主控芯片STM32F407通过ESP8266接收到指令后,根据指令内容完成相关操作。系统具有网络化、智能化的特点,且可扩展预约、视频监控等功能。     

Ultra‐low‐power polysilicon AMLCD with full integration

Abstract— An LTPS TFT‐LCD that only consumes 0.07 mW of power was developed. It is the world's first LCD equipped with all the circuits needed to display still images continuously for up to 1 year on a button battery. At the same time, the panel is capable of displaying 260,000‐color moving pictures.     

A novel pixel memory using integrated voltage‐loss‐compensation (VLC) circuit for ultra‐low‐power TFT‐LCDs

Abstract— A novel pixel memory using an integrated voltage‐loss‐compensation (VLC) circuit has been proposed for ultra‐low‐power TFT‐LCDs, which can increase the number of gray‐scale levels for a single subpixel using an analog voltage gray‐scale technique. The new pixel with a VLC circuit is integrated under a small reflective electrode in a high‐transmissive aperture‐ratio (39%) 3.17‐in. HVGA transflective panel by using a standard low‐temperature‐polysilicon process based on 1.5‐μm rules. No additional process steps are required. The VLC circuit in each pixel enables simultaneous refresh with a very small change in voltage, resulting in a two‐orders‐of‐magnitude reduction in circuit power for a 64‐color image display. The advanced transflective TFT‐LCD using the newly proposed pixel can display high‐quality multi‐color images anytime and anywhere, due to its low power consumption and good outdoor readability.     

A millimeter‐wave CMOS power amplifier design using high‐Q slow‐wave transmission lines

A three‐stage 60‐GHz power amplifier (PA) has been implemented in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. High‐quality‐factor slow‐wave coplanar waveguides (S‐CPW) were used for input, output and inter‐stage matching networks to improve the performance. Being biased for Class‐A operation, the PA exhibits a measured power gain G of 18.3 dB at the working frequency, with a 3‐dB bandwidth of 8.5 GHz. The measured 1‐dB output compression point (OCP_1dB) and the maximum saturated output power P_sat are 12 dBm and 14.2 dBm, respectively, with a DC power consumption of 156 mW under 1.2 V voltage supply. The measured peak power added efficiency PAE is 16%. The die area is 0.52 mm² (875 × 600 μm²) including all the pads, whereas the effective area is only 0.24 mm². In addition, the performance improvement of the PA in terms of G, OCP_1dB, P_sat, PAE and the figure of merit using S‐CPW instead of thin film microstrip have been demonstrated. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:99–109, 2016.     

Design of low‐loss directional couplers with compensated coupled‐line sections in suspended microstrip technique

Design of coupled line 3dB directional couplers realized in suspended microstrip technique has been presented. The main goal was to minimize the insertion losses of the coupler, what has been achieved by a proper choice of the realization technique. As the chosen coupled line geometry is asymmetric to achieve good electrical performance of the resulting coupler, capacitive compensation technique has been utilized to equalize capacitive and inductive coupling coefficients. Furthermore, a distributed‐element approach has been investigated for realization of compensation capacitances, due to their physical size resulting from the dielectric structure. The proposed coupler has been designed in two versions, having center frequencies equal to 0.89 and 1.1 GHz, manufactured and measured. The measurement results show good agreement with electromagnetic analyses and prove the correctness and usefulness of the presented design method. The manufactured couplers exhibit insertion losses as low as 0.08 dB at the center frequency.     

A W‐band RF‐MEMS switched LNA in a 70 nm mHEMT process

This work presents a monolithic integrated reconfigurable active circuit consisting of a W‐band RF micro‐electro‐mechanical‐systems (MEMS) Dicke switch network and a wideband low‐noise amplifier (LNA) realized in a 70 nm gallium arsenide (GaAs) metamorphic high electron mobility transistor process technology. The RF‐MEMS LNA has a measured gain of 10.2–15.6 dB and 1.3–8.2 dB at 79–96 GHz when the Dicke switch is switched ON and OFF, respectively. Compared with the three‐stage LNA used in this design the measured in‐band noise figure (NF) of MEMS switched LNA is minimum 1.6 dB higher. To the authors’ knowledge, the experimental results represent a first time demonstration of a W‐band MEMS switched LNA monolithic microwave integrated circuit (MMIC) in a GaAs foundry process with a minimum NF of 5 dB. The proposed novel integration of such MEMS switched MMICs can enable more cost‐effective ways to realize high‐performance single‐chip mm‐wave reconfigurable radiometer front‐ends for space and security applications, for example. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:639–646, 2015.     

Broadband high‐efficiency monolithic InGaP/GaAs HBT power amplifiers for wireless applications

In this article, a broadband approach to high‐efficiency power amplifier performance, based on the parallel‐circuit Class E mode, is discussed. Results for a practical implementation of multi‐band and multi‐mode handset power amplifiers are shown. Measurements demonstrate the feasibility of the concept for highly efficient operation of DCS1800, PCS1900, CDMA2000, and WCDMA. PAE is greater than 50% at 30 dBm output power in the DCS1800 and PCS1900 bands, as well as better than 38% at 27 dBm output power and an ACLR of ?37 dBc is achieved for WCDMA operation. © 2003 Wiley Periodicals, Inc. Int J RF and Microwave CAE 13, 496–510, 2003.     

A comparison of three‐dimensional electromagnetic and RC parasitic extraction analysis of mm‐wave on‐chip passives in SiGe BiCMOS low‐noise amplifiers

Layout parasitics significantly impact the performance of mm‐wave microelectronic circuits. These effects may be estimated by including foundry‐qualified pcell interconnect models in schematic with or without additional RC parasitics extraction (RCPE), or by generating an EM simulation (FEM and MoM) of the layout and cosimulating with active device models. In this paper, these methods are compared at by simulating the compression (P1db), gain (S₂₁), and noise figure (NF) of a V‐band LNA in 130 nm SiGe BiCMOS and comparing the results of different simulation approaches to measurements. It is found that the FEM cosimulated results agree better with the measurements than the other methods, providing a maximum error of 0.8 dB in gain, 0.18 dB in NF, and 0.6 dB in P1dB. This is a significant improvement over the errors obtained with pcell‐based schematic (2.6 dB in gain, 0.1 dB in NF, and 2.2 dB in P1db), schematic simulation with RCPE (1.55 dB in gain, 1.15 dB in NF, and 0.8 dB in P1db), and MoM cosimulation (0.67 dB in gain, 0.72 in NF, and 0.67 in P1db). This experiment validates the preference to FEM cosimulation in mm‐wave microelectronic circuits yet would indicate that reasonably accurate first‐iteration results may be obtained through a combined pcell‐RCPE approach with significantly shorter simulation time.