Effects of gate‐bias stress on ZnO thin‐film transistors

Abstract— The effects of gate‐bias and thermal stress on the stability issues of zinc oxide thin film transistors (ZnO TFTs) deposited on glass substrates were investigated. The shift in threshold voltage for devices undergoing various post‐growth annealing conditions using a stretched‐exponential formalism was analyzed. The analysis indicated that the extracted parameters such as the time constant and the effective energy barrier (E^τ) can be correlated to the device trap states associated with the annealing conditions. Improvement in the channel conductance and interface quality, hence the resultant device stability, can therefore be resumed when subject to a thermal treatment at 400°C for 30 minutes compared with those annealed for a shorter time.     

Experimental decomposition of the positive bias temperature stress‐induced instability in self‐aligned coplanar InGaZnO thin‐film transistors and its modeling based on the multiple stretched‐exponential functions

Decomposition of the positive gate‐bias temperature stress (PBTS)‐induced instability into contributions of distinct mechanisms is experimentally demonstrated at several temperatures in top‐gate self‐aligned coplanar amorphous InGaZnO thin‐film transistors by combining the stress‐time‐divided measurements and the subgap density‐of‐states (DOS) extraction. It is found that the PBTS‐induced threshold voltage shift (ΔV_T) consists of three mechanisms: (1) increase of DOS due to excess oxygen in the active region; (2) shallow; and (3) deep charge trapping in the gate insulator components. Corresponding activation energy is 0.75, 0.4, and 0.9 eV, respectively. The increase of DOS is physically identified as the electron‐capture by peroxide. Proposed decomposition is validated by reproducing the PBTS time‐evolution of I–V characteristics through the technology computer‐aided design simulation into which the extracted DOS and charge trapping are incorporated. It is also found that the quantitative decomposition of PBTS‐induce ΔV_T accompanied with the multiple stretched‐exponential models enables an effective assessment of the complex degradation nature of multiple PBTS physical processes occurring simultaneously. Our results can be easily applied universally to any device with any stress conditions, along with guidelines for process optimization efforts toward ultimate PBTS stability.     

Letter: Solution‐processed flexible zinc‐tin oxide thin‐film transistors on ultra‐thin polyimide substrates

In this letter, solution‐processed flexible zinc‐tin oxide (Z_0.35T_0.65O_1.7) thin‐film transistors with electrochemically oxidized gate insulators (AlOx:Nd) fabricated on ultra‐thin (30 µm) polyimide substrates are presented. The AlOx:Nd insulators exhibited wonderful stability under bending and excellent insulating properties with low leakage current, high dielectric constant, and high breakdown field. The device exhibited a mobility of 3.9 cm²/V · s after annealing at 300 °C. In addition, the flexible device was able to maintain the electricity performance under various degrees of bending, which was attributed to the ultra‐thin polyimide substrate.     

Uniformity and bias‐temperature instability of bottom‐gate zinc oxide thin‐film transistors (ZnO TFTs)

Abstract— Short‐range uniformity and bias‐temperature (BT) instability of ZnO TFTs with SiO^x/SiN^x stacked gate insulators which have different surface treatments have been investigated. The short‐range uniformity of ZnO TFTs was drastically improved by N²O plasma treatment of the gate insulator. The variation in the gate voltage where a drain current of 1‐nA flows (Vgs at an Ids of 1 nA) was dramatically reduced from ±1.73 V to ±0.07 V by N²O plasma treatment of the gate insulator. It was clarified that the variations in the subthreshold characteristics of the ZnO TFTs could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the variation of trap densities in deep energy levels from 0.9–2.0 × 10¹⁷ to 1.2–1.3×10¹⁷ cm^?3‐eV^?1. From the BT stress tests, a positive shift of Vgs at an Ids of 1 nA could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the charge traps in the gate insulator. When the gate‐bias stress increases, state creation occured in the ZnO TFTs in addition to the charge trapping in the gate insulator. However, N²O plasma treatment of the gate insulator has little effect on the suppression of the state creation in ZnO TFTs under BT stress. The surface treatment of the gate insulator strongly affects the short‐range uniformity and the BT instability of Vth in the ZnO TFTs.     

100‐MHz CMOS circuits directly fabricated on plastic using sequential laterally solidified silicon

Abstract— CMOS TFT circuits were fabricated on plastic using sequential laterally solidified silicon combined with a low‐temperature CMOS process. The unity‐gain frequencies of the best of NMOS TFTs are greater than 250 MHz, and the CMOS ring oscillators operate at 100 MHz. To the best of the authors' knowledge, these are the highest‐frequency circuits ever fabricated directly on plastic. This high‐performance CMOS‐on‐plastic process can be applied to the fabrication of AMLCD integrated drivers and AMOLED pixels on plastic substrates.     

Circuits using uniform TFTs based on amorphous In‐Ga‐Zn‐O

Abstract— High‐performance and excellent‐uniformity thin‐film transistors (TFTs) having bottom‐gate structures are fabricated using an amorphous indium‐gallium‐zinc‐oxide (IGZO) film and an amorphous‐silicon dioxide film as the channel layer and the gate insulator layer, respectively. All of the 94 TFTs fabricated with an area 1 cm² show almost identical transfer characteristics: the average saturation mobility is 14.6 cm²/(V‐sec) with a small standard deviation of 0.11 cm²/(V‐sec). A five‐stage ring‐oscillator composed of these TFTs operates at 410 kHz at an input voltage of 18 V. Pixel‐driving circuits based on these TFTs are also fabricated with organic light‐emitting diodes (OLED) which are monolithically integrated on the same substrate. It is demonstrated that light emission from the OLED cells can be switched and modulated by a 120‐Hz ac signal input. Amorphous‐IGZO‐based TFTs are prominent candidates for building blocks of large‐area OLED‐display electronics.     

In‐pixel temperature sensor for high‐luminance active matrix micro‐light‐emitting diode display using low‐temperature polycrystalline silicon and oxide thin‐film‐transistors

We propose an in‐pixel temperature sensor using low‐temperature polycrystalline silicon and oxide (LTPO) thin‐film transistor (TFTs) for high‐luminance active matrix (AM) micro‐light‐emitting diode (LED) displays. By taking advantage of the different off‐current characteristics of p‐type LTPS TFTs and n‐type a‐IGZO TFTs under temperature change, we designed and fabricated a temperature sensor consists of only LTPO TFTs without additional sensing component or material. The fabricated sensor exhibits excellent temperature sensitivity of up to 71.8 mV/°C. In addition, a 64 × 64 temperature sensor array with 3T sensing pixel and integrated gate driver has also been fabricated, which demonstrates potential approach for maxing out the performance of high‐luminance AM micro‐LED display with real‐time in‐pixel temperature monitoring.     

Letter: A new compensation pixel circuit with metal oxide thin‐film transistors for active‐matrix organic light‐emitting diode displays

This paper presents a novel compensation pixel circuit for active‐matrix organic light‐emitting diode displays, in which the coupling effect mask technology is developed to compensate the threshold voltage of driving thin‐film transistor whether it is positive or negative. Twenty discrete compensation pixel circuits have been fabricated by In‐Zn‐O thin‐film transistors process. It is measured that the non‐uniformity of the proposed pixel circuit is significantly reduced with an average value of 8.6%. Furthermore, the organic light‐emitting diode emission current remains constant during 6 h continuous operation, which also confirms the validity of the proposed pixel circuit.     

Multioutputs single‐stage gate driver on array with wide temperature operable thin‐film‐transistor liquid‐crystal display for high resolution application

A hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) gate driver with multioutputs (eight outputs per stage) for high reliability, 10.7‐inch automotive display has been proposed. The driver circuit is composed of one SR controller, eight driving TFTs (one stage to eight outputs) with bridging TFTs. The SR controller, which starts up the driving TFTs, could also prevent the noise of gate line for nonworking period. The bridging TFT, using width decreasing which connects between the SR controller and the driving TFT, could produce the floating state which is beneficial to couple the gate voltage, improves the driving ability of output, and reaches consistent rising time in high temperature and low temperature environment. Moreover, 8‐phase clocks with 75% overlapping and dual‐side driving scheme are also used in the circuit design to ensure enough charging time and reduce the loading of each gate line. According to lifetime test results, the proposed gate driver of 720 stages pass the extreme temperature range test (90°C and ?40°C) for simulation, and operates stably over 800 hours at 90°C for measurement. Besides, this design is successfully demonstrated in a 10.7‐inch full HD (1080 × RGB×1920) TFT‐liquid‐crystal display (LCD) panel.     

Design of dual‐outputs‐single‐stage a‐Si:H TFT gate driver for high resolution TFT‐LCD application

A new gate driver has been designed and fabricated by amorphous silicon technology. With utilizing the concept of sharing the noise free block in a single stage for gate driver, dual‐outputs signals could be generated in sequence. By increasing the number of output circuit block in proposed gate driver, number of outputs per stage could also be adding that improves the efficiency for area reduction. Besides, using single driving thin‐film‐transistor (TFT) for charging and discharging, the area of circuit is also decreased by diminishing the size of pulling down TFT. Moreover, the proposed gate driver has been successfully demonstrated in a 5.5‐inch Full HD (1080xRGBx1920) TFT‐liquid‐crystal display panel and passed reliability tests of the supporting foundry.     

Solution‐processed and low‐temperature metal oxide n‐channel thin‐film transistors and low‐voltage complementary circuitry on large‐area flexible polyimide foil

High‐performance solution‐based n‐type metal oxide thin‐film transistors (TFTs), fabricated directly on polyimide foil at a post‐annealing temperature of only 250 °C, are realized and reported. Saturation mobilities exceeding 2 cm²/(Vs) and on‐to‐off current ratios up to 10⁸ are achieved. The usage of these oxide n‐type TFTs as the pixel drive and select transistors in future flexible active‐matrix organic light‐emitting diode (AMOLED) displays is proposed. With these oxide n‐type TFTs, fast and low‐voltage n‐type only flexible circuitry is demonstrated. Furthermore, a complete 8‐bit radio‐frequency identification transponder chip on foil has been fabricated and measured, to prove that these oxide n‐type TFTs have reached already a high level of yield and reliability. The integration of the same solution‐based oxide n‐type TFTs with organic p‐type TFTs into hybrid complementary circuitry on polyimide foil is demonstrated. A comparison between both the n‐type only and complementary elementary circuitry shows the high potential of this hybrid complementary technology for future line‐drive circuitry embedded at the borders of flexible AMOLED displays.     

Flexible active‐matrix OLED displays: Challenges and progress

Abstract— Organic light‐emitting‐device (OLED) devices are very promising candidates for flexible‐display applications because of their organic thin‐film configuration and excellent optical and video performance. Recent progress of flexible‐OLED technologies for high‐performance full‐color active‐matrix OLED (AMOLED) displays will be presented and future challenges will be discussed. Specific focus is placed on technology components, including high‐efficiency phosphorescent OLED technology, substrates and backplanes for flexible displays, transparent compound cathode technology, conformal packaging, and the flexibility testing of these devices. Finally, the latest prototype in collaboration with LG. Phillips LCD, a flexible 4‐in. QVGA full‐color AMOLED built on amorphous‐silicon backplane, will be described.     

Implementation of delta—sigma analog‐to‐digital converter in LTPS process

Abstract— An on‐panel delta—sigma analog‐to‐digital converter (ADC) has been implemented and verified for 3‐μm low‐temperature polysilicon (LTPS) technology with two basic blocks: a delta—sigma modulator and a decimation filter. From the experimental results, the digital output from the delta—sigma modulator is correctly matched with the analog input voltage ratio such that the digital output can be converted into 8‐bit digital code successfully under a supply voltage of 10 V from the decimation filter. The implemented on‐panel delta—sigma ADC can be used for the application of temperature‐to‐digital converter on glass substrate.     

a‐InGaZnO thin‐film transistors for AMOLEDs: Electrical stability and pixel‐circuit simulation

Abstract— Inverted‐staggered amorphous In‐Ga‐Zn‐O (a‐InGaZnO) thin‐film transistors (TFTs) were fabricated and characterized on glass substrates. The a‐InGaZnO TFTs exhibit adequate field‐effect mobilities, sharp subthreshold slopes, and very low off‐currents. The current temperature stress (CTS) on the a‐InGaZnO TFTs was performed, and the effect of stress temperature (TSTR), stress current (ISTR), and TFT biasing condition on their electrical stability was investigated. Finally, SPICE modelling for a‐InGaZnO TFTs was developed based on experimental data. Several active‐matrix organic light‐emitting‐display (AMOLED) pixel circuits were simulated, and the potential advantages of using a‐InGaZnO TFTs were discussed.     

Design and implementation of readout circuit on glass substrate with digital correction for touch‐panel applications

Abstract— A readout circuit on glass substrate with digital correction, which contains a transconductance amplifier, counter, and digital correction circuit, has been designed for touch‐panel applications for 3‐μm low‐temperature polysilicon (LTPS) technology. The voltage difference as a result of a change in capacitance due to a touch event is converted to current by a transconductance amplifier. By charging and discharging the capacitor in the counter, the counter displays different digital‐output codes according to touch or non‐touch events. Furthermore, not only can the touch or non‐touch event be distinguished, but also the influence of LTPS process variation can be compensated by a digital correction circuit in the proposed readout circuit.