红外热像的初始化诊断法

简述通常采用的热平衡后摄取红外热像进行故障诊断所带来的问题和针对该问题所作的试验，试验结果表明初始化诊断法可以有效地抑制通过热传导、热辐射、热对流方式对被测元器件相互间的影响，从而使诊断准确、迅速。     

网络故障诊断法的综合应用

国际标准化组织ISO在ISO／IEC7498-4文档中定义了网络管理的5大功能，即故障管理、配置管理、性能管理、记账管理和安全管理，故障管理是其中最基本的功能之一，它包括诊断故障、孤立故障和恢复故障3个方面，其中，诊断故障是网络故障管理的先决条件。网络故障现象可以说形形色色，几乎没有任何一种检测方法或工具可以诊断出所有的网络问题。笔者总结了多年的网络管理实践经验，认为采用网络故障综合诊断法是解决网络故障的有效途径，它融合了分层诊断、分段诊断和“望闻问切”诊断，这3种方法综合使用就构成了一个立体的网络故障诊断模型，如图1所示。下面，先分别介绍这3种网络故障诊断方法，     

光伏阵列故障诊断算法研究综述

有效对光伏阵列进行快速、准确的故障诊断是保证光伏发电系统安全稳定运行的必要条件.本文结合国内外的研究成果,分析了光伏阵列故障的主要类型及形成原因,并从传统诊断法和智能算法两个方面对光伏阵列故障诊断进行阐述,分析了各种算法的原理以及优缺点.结合目前已取得的研究成果,对未来光伏阵列故障诊断的方法进行了初步的展望.     

“感官诊断法”在电动机故障检修中的应用

电动机是当前应用最广、使用最多的电气设备,通过科学合理的维护和检修,可以提高其使用寿命和效率。"感官诊断法"是广泛使用且行之有效的电动机检修方法,特点是简单实用、简捷高效,文中重点介绍"感官诊断法"在电动机常见故障检修中的应用。     

维修电工的“诊断四法”

我们的维修电工师傅就好比电气设备的医生。分析判断故障点与医生诊断病情有多处相似。笔者在多年维修实践工作中，逐渐摸索出一套查找故障的快速方法，为了便于速记，笔者把它合成概括为四个字：问、看、听、测。并称作维修电工的“诊断法”。只要灵活运用这“诊断法”，就能快速准确地查到故障部位，时常收到事半功倍的特效。     

大规模模拟电路子网络级故障诊断的神经网络方法

本文提出了一种采用双向联想记忆神经元网络诊断法诊断子网络级故障的新方法。在对含不可及节点的子网络级故障诊断的互测试条件检验的基础上，用神经元网络诊断法代替逻辑分析来快速而有效地定位故障子网络，并给出了诊断实例。     

输电网故障诊断方法研究

针对输电网故障诊断,对当前在湖南地区经常使用的专家系统诊断法和人工神经网络诊断法进行分析,在明确诊断方法所具有的特点与优势的基础上,提出了现存的问题及其改进、发展方向,为进一步丰富输电网故障诊断理论储备,提供更多有效诊断方法奠定基础.     

模拟电路的故障回路和故障网孔的诊断

文中给出了模拟电路多故障诊断的回路法和网孔法,使K故障诊断理论内容完整,在某些情况下,回路诊断法具有一定的优越性。     

一种模数混合电路故障诊断新方法

把模拟电路故障诊断的子网络撕裂诊断法与数字电路故障诊断的伪穷举测试法相结合．提出了一种应用于模数混合电路的故障诊断方法。其诊断思想是把串联形式的混合电路，划分成模拟和数字电路两部分．并分别进行诊断。该方法计算量小、诊断定位精度高，适合于工程应用。     

基于T-S模糊故障树的系统故障诊断研究

针对传统的故障树分析法在故障诊断中存在的缺点和不足,文中将模糊理论运用到故障诊断中,提出基于T-S的模糊故障树的故障诊断法.介绍了T-S模糊模型及算法,建立了诊断系统的故障库和推理机.使设备操作和维修人员可及时发现故障,降低系统故障率,提高了保障的能力.     

Low cost design of microprocessor EDAC circuit

An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies.     

Built-in testable error detection and correction

A method for design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented that uses up to 65% less test hardware than customary BIT implementations. A 1-μm CMOS, 16-bit EDAC designed and fabricated with this technique exhibits >99% fault coverage in 10 μs at 25 MHz. Built-in test impacts the speed performance by only one gate delay regardless of the size of the EDAC. Various faults are injected into the chip to verify the effectiveness of built-in test     

Software-implemented EDAC protection against SEUs

In many computer systems, the contents of memory are protected by an error detection and correction (EDAC) code. Bit-flips caused by single event upsets (SEU) are a well-known problem in memory chips; EDAC codes have been an effective solution to this problem. These codes are usually implemented in hardware using extra memory bits and encoding/decoding circuitry. In systems where EDAC hardware is not available, the reliability of the system can be improved by providing protection through software. Codes and techniques that can be used for software implementation of EDAC are discussed and compared. The implementation requirements and issues are discussed, and some solutions are presented. The paper discusses in detail how system-level and chip-level structures relate to multiple error correction. A simple solution is presented to make the EDAC scheme independent of these structures. The technique in this paper was implemented and used effectively in an actual space experiment. We have observed that SEU corrupt the operating system or programs of a computer system that does not have any EDAC for memory, forcing the system to be reset frequently. Protecting the entire memory (code and data) might not be practical in software. However this paper demonstrates that software-implemented EDAC is a low-cost solution that provides protection for code segments and can appreciably enhance the system availability in a low-radiation space environment     

Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors

In this paper, we propose a diagnose strategy based on built-in current sensors able to detect the effects of single event transients (SETs) in SRAM memory decoders. By analyzing the effects, it is possible to mitigate the error by warning the system about the erroneous write and read operation or by circuit error correction avoiding catastrophic multiple bit upset errors. While EDAC can only protect faults in the memory cell array, the proposed method can cope with faults in the combinational memory circuitry. This BICS-based technique can be used in combination with EDAC to achieve high reliability in memories fabricated in nanometer technologies. Our methodology has been validated by Spice simulation and results show that our approach presents a low area, performance and power dissipation penalty.     

Multi-bit upset aware hybrid error-correction for cache in embedded processors

For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multi-bit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.     

一种改进的对抗软错误电路结构设计

给出了一种改进的基于时钟沿的自我检测和纠正的电路结构,以纠正由单粒子翻转（SEU）引起的数据错误。简单概述了已有的检测和纠正SEU的电路结构,并在该电路的基础上提出了改进的电路结构,以实现对触发器以及SRAM等存储器的实时监控,并可以及时纠正其由于SEU引起的数据错误。采用内建命令进行错误注入模拟单粒子翻转对电路的影响。改进的电路与原来的电路相比,以微小的面积和较少的资源换取更高的纠错率。     

Logic design error diagnosis and correction

Logic verification tools are often used to verify a gate-level implementation of a digital system in terms of its functional specification. If the implementation is found not to be functionally equivalent to the specification, it is important to correct the implementation automatically. This paper describes a formal method for the diagnosis and correction of logic design errors in an incorrect gate-level implementation. We use Boolean equation techniques to search for potential error locations. An efficient search and pruning algorithm is developed by introducing the notion of immediate dominator set. Two correction procedures are proposed. Gate correction corrects errors such as wrong gate type, missing inverters, etc.; line correction corrects errors such as missing wires and wrong connections. Our method is robust and covers all, simple design errors described by Abadir et al. (1988). Experimental results for a set of ISCAS and MCNC benchmark circuits demonstrate the effectiveness of the proposed techniques     

DSP错误检测与纠正功能在基站中的应用

通信系统要求高稳定性,但外部恶劣的电磁环境会导致基带板所使用DSP中的存储器发生单粒子翻转(SEU),从而导致系统异常复位。针对该问题,着重介绍了如何应用DSP的错误检测与纠正(EDAC)功能,以及如何解决EDAC应用与cache操作之间的冲突。通过实际应用,基站出现SEU异常的机率明显降低,系统稳定性得到提高。     

ADS—B系统接收处理的关键算法研究与实现

在高A／C应答fruit交迭的环境下,可能使ADS—B信号被ADS—B系统接收后。产生一些错误位,从而必须对ADS—B信号进行检错与纠错处理。首先介绍了基于模式S的ADS-B系统的组成原理,给出了置信度判定的基本思想,阐述了循环冗余编码（CRC）校验的基本理论与纠错技术的基本原理;然后在此基础上,提出了一种基于ADS—B系统的纠检错算法,并给出了纠检错算法的信号处理流程图与FPGA逻辑设计方案;最后采用VerilogHDL语言完成了所有功能模块的设计。并联合ISE与ModlSim两个软件进行了仿真验证实验。实验结果表明,该算法能够有效地对ADS。B信号进行检错与纠错。     

软件错误检测与纠正技术可靠性研究

基于信息冗余的错误检测与纠正（Error Detection and Correction,EDAC）技术是常见的系统级抗单粒子翻转（Single Event Upsets,SEU）的容错方法,软件实现的EDAC技术是硬件EDAC技术的替代方案,通过软件编程,在现有存储段上增加具有纠错功能的编码（Error-correcting Codes,ECC）来实现存储区错误的检测和纠正。分析了软件EDAC方案中,纠错编码的纠错能力及编码效率、刷新间隔、需保护代码量等因素对可靠性的影响,分析和仿真实验结果表明,对于单个粒子引起的存储器随机错误,提高单个码字的纠错能力及编码效率、增大刷新间隔对可靠性的影响不大,而通过缩短任务执行的代码量来提高刷新间隔,以及压缩需保护代码的总量,对可靠性有较大改进。分析结论能够指导工程实践中,在实现资源、实时性、可靠性之间进行优化选择。