次表面横向PNP管制作及辐射效应研究

依据总剂量辐射对横向PNP(LPNP)管的损伤机理,设计了一种辐射加固的次表面LPNP管。开发了通过高能离子注入工艺实现LPNP管的工艺方法,该工艺与常规双极工艺兼容。总剂量辐射试验结果表明,采用次表面LPNP管制作的LW5101线性稳压器的抗辐射能力显著提高。     

一种新型4H-SiC双极结型晶体管的研究

研制了一种功率型4H-SiC双极结型晶体管。通过采用深能级降低工艺和一氧化氮退火钝化工艺,提高了电流增益。详细研究了发射极-基极几何结构与电流增益的关系,发现随着发射极线宽或发射极-基极间距的逐渐增加,最大电流增益也逐渐提高并趋于饱和。器件在反向阻断电压1 200 V时漏电流为5.7 μA。在基极电流为160 mA时集电极电流达11 A,电流增益达到68。     

双极晶体管发射极电阻的提取方法及应用研究

以双多晶自对准互补双极器件中NPN双极晶体管为例,阐述了发射极电阻提取的基本原理和数学方法。在大电流情况下,NPN管的基极电流偏离理想电流是发射极串联电阻效应引起的。该提取方法综合考虑了辐照过程中NPN管的电流增益退化特性,分析了总剂量辐照效应对NPN管的损伤机理和模式。该提取方法适用于多晶硅发射极器件,也适用于SiGe HBT器件。     

多晶硅发射极NPN管的辐射效应研究

为了研究多晶硅发射极双极晶体管的辐射可靠性,对多晶硅发射极NPN管进行了不同偏置条件下⁶⁰Co γ射线的高剂量率辐照试验和室温退火试验。试验结果表明,辐射后,基极电流IB显著增大,而集电极电流IC变化不大;反偏偏置条件下,IB的辐射损伤效应在辐射后更严重;室温退火后,IB有一定程度的持续损伤。多晶硅发射极NPN管与单晶硅发射极NPN管的辐射对比试验结果表明,多晶硅发射极NPN管的抗辐射性能较好。从器件结构和工艺条件方面,分析了多晶硅发射极NPN管的辐射损伤机理。分析了多晶硅发射极NPN管与单晶硅发射极NPN管的辐射损伤区别。     

一种低失调高压大电流集成运算放大器

基于结型场效应晶体管(JFET)和双极型晶体管(BJT)兼容工艺,设计了一种低失调高压大电流集成运算放大器。电路输入级采用p沟道JFET (p-JFET)差分对共源共栅结构;中间级以BJT作为放大管,采用复合有源负载结构;输出级采用复合npn达林顿管阵列,与常规推挽输出结构相比,在输出相同电流的情况下,节省了大量芯片面积。基于Cadence Spectre软件对该运算放大器电路进行了仿真分析和优化设计,在±35 V电源供电下,最小负载电阻为6Ω时的电压增益为95 dB,输入失调电压为0.224 5 mV,输入偏置电流为31.34 pA,输入失调电流为3.3 pA,单位增益带宽为9.6 MHz,具有输出9 A峰值大电流能力。     

一种基于双极工艺的大电流高输出电阻恒流源

基于双极工艺,设计了一种同时具备大电流和高输出电阻特性的恒流源电路。该恒流源采用发射极输出的结构,使恒流源的输出电阻对输出电流不敏感,从而在大电流情况下保持较大的输出电阻。该结构适用于需要提供稳定大电流的集成电路,例如功率运算放大器的驱动级前级恒流源有源负载等。     

一种峰值电流模式DC-DC转换器控制电路设计

基于中科渝芯40 V双极型工艺,完成了一种峰值电流模式DC-DC电压转换器控制电路的模块设计、芯片版图设计和流片验证,其通用于升压、降压、反相的场景,并可以实现输出电压可调。电路采用峰值电流模式的PWM控制方式,能够更好的提供瞬态特性以及重载下的输出性能。芯片集成功率开关管,采用类三角形分布式发射极版图设计,保证足够发射区面积的同时有效降低了基极电阻,减弱了电流集边效应,弥补了发射极去偏置效应,并且不增加额外面积。实测数据表明：外接1 nF的定时电容可产生约32 kHz的振荡频率,功率开关管关态集电极电流低至52 nA,功率管直流电流增益约为131,基准电压温度系数约为0.09 mV/℃,静态电源电流低,约为2.7 mA。     

电流自适应高寿命低功耗LED驱动器

基于CSMC 0.5μm混合信号工艺,设计了一款电流自动可调的LED驱动芯片。该芯片是根据PN结电压的负温度系数特性,以及CMOS管处在深三极管区时的线性特性来设计的。测试结果显示:当芯片温度未达到过温保护点80°C时,芯片可实现电流在0～1.25A范围内任意值恒定输出;当温度达到过温保护点时,电流随芯片温度的上升按反比例函数的趋势降低。当芯片输出电流为350mA时,外加在功率CMOS管源漏两端的电压VSEN可低至0.1V,功耗可低至93.5mW。     

双极器件EB结击穿测试对HFE的影响

三极管测试发现,发射极和基极EB结击穿测试会降低三极管放大倍数HFE。理论表明,HFE和注入效率γ、基区输运系数αT、复合系数δ相关。文章模拟EB结击穿应力,同时设计三种测试方法,测试应力前后三极管HFE、IC、IB等参数的变化,认为HFE降低是由于IB的增大造成。同时根据上面三个系数对应的物理区域分析认为,电流应力造成了缺陷,缺陷引起的EB结复合电流和基区传输复合电流的增大是IB增大的原因,但EB结复合电流是主要的,是HFE降低的原因。最后指出流片工艺过程中的损伤也会造成类似HFE降低的问题。     

简易宽带线性电压——频率变换器

该变换器电路示于图1。电路基本上是一变型的普通非稳态多谐振荡器,其中晶体管 VT_1和 VT_2为主要振荡管。为保证定时电容器能线性充电,原来的两充电电阻换成用 VT_3和 VT_4构成的两个电流源。VT_5和VT_6为发射极输出器,用来使定时电容器     

1.2～1.4GHz 300W宽带硅微波脉冲大功率管

介绍了L波段宽带硅微波脉冲300W大功率晶体管研制结果。该器件采用微波功率管环台面集电极结终端结构、非线性镇流电阻和热稳定等新工艺技术,在1.2～1.4GHz频带内,脉宽150μs,占空比10%和40V工作电压下,全带内脉冲输出功率大于300W,功率增益大于8.75dB,效率大于55%。     

1.46~1.66GHz 250W宽带硅微波脉冲大功率管

报道了L波段高端中脉冲250W宽带硅微波脉冲大功率晶体管研制结果.该器件采用微波功率管环台面集电极结终端结构、非线性镇流电阻等新工艺技术,器件在1.46～1.66GHz频带内,脉宽200μs,占空比10%和40V工作电压下,全带内脉冲输出功率大于250W,功率增益大于7.0dB,效率大于45%.     

不同类型双极晶体管抗辐照性能的研究

时于制作工艺相同的NPN和LPNP两种类型的双极型晶体管进行了辐照实验,研究了不同类型双极晶体管的电离总剂量辐射损伤机理和退火效应。实验结果表明：在相同的辐照总剂量下．LPNP型双极晶体管的归一化电流增益的下降比NPN型双极晶体管的下降多．说明LPNP型双极晶体管的辐照敏感性更强。这与NPN和LPNP这两种类型的双极晶体管的辐射损伤机理的不同有关。对于NPN型双极晶体管,电离辐照总剂照效应主要是造成氧化物正电荷的积累：而对于LPNP型双极晶体管．电离辐照总剂量效应主要是造成界面态密度的增加。     

高压IGBT线性变窄场限环终端设计

为使3300 V及以上电压等级绝缘栅双极型晶体管(IGBT)的工作结温达到150℃以上,设计了一种具有高结终端效率、结构简单且工艺可实现的线性变窄场限环(LNFLR)终端结构。采用TCAD软件对这种终端结构的击穿电压、电场分布和击穿电流等进行了仿真,调整环宽、环间距及线性变窄的公差值等结构参数以获得最优的电场分布,重点对比了高环掺杂浓度和低环掺杂浓度两种情况下LNFLR终端的阻断特性。仿真结果表明,低环掺杂浓度的LNFLR终端具有更高的击穿电压。进一步通过折中击穿电压和终端宽度,采用LNFLR终端的3300 V IGBT器件可以实现4500 V以上的终端耐压,而终端宽度只有700μm,相对于标准的场限环场板(FLRFP)终端缩小了50%。     

Properties of ESFI MOS transistors due to the floating substrate and the finite volume

The specific current-voltage characteristics of epitaxial silicon films on insulator (ESFI®) SOS MOS transistors are shown, discussed in comparison to bulk silicon MOST's, and explained by the differences in geometrical considerations, charge distribution, and operation mode, The ESFI MOST's are produced on silicon islands, in most applications, the electrical substrate is at floating potential. This results in two effects. At first a threshold voltage change occurs with increasing drain voltage, producing a kink in the current curve; if the drain voltage further increases, a parasitic bipolar transistor begins to work and effects another kink or bend in the curve. On the other hand, the finite vo|ume effects a strong dependence of the base width of the parasitic bipolar transistor on the drain voltage and causes a rise of the current amplification with the drain voltage. The finite volume below the gate oxide also limits the bulk-charge magnitudes with subsequent increase in mobile carrier charge, thereby increasing the transconductance. All these effects are also described theoretically; the ID-VDcharacteristics could be simulated by computer model based on the physical effects.     

The effects of interconnect process and snapback voltage on the ESDfailure threshold of NMOS transistors

The electrostatic discharge (ESD) failure threshold of NMOS transistors in a shelf-aligned TiSi₂ process has been identified to be sensitive to both interconnect processes and device structures. For a consistently good ESD protection level, there is a maximum limit of TiSi₂ thickness formed on a shallow junction. The thickness is less than that required to ensure a low junction leakage current. The effect of contact processes on ESD is also studied. Both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the ESD failure threshold of the NMOS transistor. The ESD failure threshold voltage an NMOS transistor is strongly correlated with the snapback voltage of its lateral parasitic bipolar transistor. The ESD pass voltage or the highest current that an NMOS transistor can withstand is a decreasing function of its parasitic bipolar snapback voltage. This finding explains why an abrupt junction device has a higher ESD failure threshold voltage than a graded-junction device. The gate potential of an NMOS transistor also has important effects on its failure threshold voltage     

Floating gates for avalanche suppression in MESFET's

A metal-semiconductor field-effect transistor (MESFET) structure is proposed. It employs one or more uncontacted gate elements between the normal gate and the drain which float in potential in a manner similar to guard rings. These floating gates clamp the maximum electric field at the normal gate and inhibit avalanche breakdown. Numerical modeling of a typical GaAs MESFET with two floating gates demonstrates the field-clamping effect and shows a substantial increase in avalanche breakdown voltage and maximum output power relative to a similar conventional device     

An NMOS input merged bipolar/sidewall-MOS transistor with a bypasssidewall MOS transistor (NBiBMOS transistor)

The concept of merging a vertical n-p-n bipolar and two sidewall NMOS transistors into an NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall NMOS transistor structure (NBiBMOS transistor) is described. The output current of this structure, unlike that of NBiMOS transistors, is significant even when the output voltage (V_CE or V_DE) is less than the turn-on voltage of the n-p-n bipolar transistor (V_BE=~0.8 V). This structure, when used in BiCMOS logic gates, will allow the output voltage to swing all the way to 0.0 V rather than to 0.8 V. The feasibility of this concept was demonstrated by fabricating and DC characterizing the NBiBMOS transistor structures, which occupy ~1.2 times the area of a single n-p-n bipolar transistor. The NBiBMOS transistor has a higher drive capability than that of a structure consisting of an NBiMOS and a separate bypass transistor, because the body-source junction of the bypass NMOS transistor is forward biased