Design and implementation of a high level programming environmentfor FPGA-based image processing

Reconfigurable hardware in the form of field programmable gate arrays (FPGAs) has been proposed as a way of obtaining high performance for computationally intensive DSP applications such as image processing (IP), even under real time requirements. The inherent reprogrammability of FPGAs gives them some of the flexibility of software while keeping the performance advantages of an application specific solution. However, a major disadvantage of FPGAs is their low level programming model. To bridge the gap between these two levels, the authors present a high level software environment for FPGA-based image processing, which aims to hide hardware details as much as possible from the user. Their approach is to provide a very high level image processing coprocessor (IPC) with a core instruction set based on the operations of image algebra. The environment includes a generator which generates optimised architectures for specific user-defined operations     

An efficient logic emulation system

The Realizer, is a logic emulation system that automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. Its interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales linearly with pin count, and allows hierarchical expansion to systems with hundreds of thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 Xilinx XC3090 FPGAs for logic. Several designs, including a 32-b CPU datapath, have been automatically realized and operated at speed. They demonstrate very good FPGA utilization. The Realizer has applications in logic verification and prototyping, simulation, architecture development, and special-purpose execution     

Routability of Network Topologies in FPGAs

A fundamental difference between application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) is that the wires in ASICs are designed to match the requirements of a particular design. Conversely, in an FPGA, the area is fixed and the routing resources exist whether or not they are used. In this paper, we investigate how well several common network topologies map onto a modern FPGA routing fabric. Different multiprocessor network topologies with between 8 and 64 nodes are mapped to a single large FPGA. Except for the fully-connected networks, it is observed that the difference in logic resources used and routing overhead among these topologies is insignificant for the systems tested. Fully-connected networks up to about 22 nodes are also feasible on the same FPGA although the logic and routing utilization clearly grows much faster. The conclusion is that a modern FPGA fabric is very rich in resources and capable of supporting highly interconnected topologies. For systems with a modest number of nodes implemented on current large FPGAs, it is not necessary to use the connectivity-limited topologies typically used for networks-on-chip. Rather, direct point-to-point connections between all communicating nodes can be considered.     

FPGA implementation of multiplierless M-QAM modulator

Adaptive multilevel QAM (M-QAM) modulation can increase throughput in a wireless packet data network. A technique is discussed for efficiently realising M-QAM modulators on field programmable gate arrays (FPGAs) using 'multiplierless' finite impulse response (FIR) filters with carry-save addition and canonic signed-digit coefficients. An adaptive M-QAM modulator supporting 4, 16, 64 and 256-QAM is presented     

Run-Time Reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs

One way to further exploit the reconfigurable resources of SRAM FPGAs and increase functional density is to reconfigure them during system operation. This proces is referred to as Run-Time Reconfiguration (RTR). RTR is an approach to system implementation that divides an application or algorithm into time-exclusive operations that are implemented as separate configurations. The Run-Time Reconfiguration Artificial Neural Network (RRANN) is a proof-of-concept system that demonstrates the effectiveness of RTR for implementing neural networks. It implements the popular backpropagation training algorithm as three distinct time-exclusive FPGA configurations: feed-forward, backpropagation and update. System operation consists of sequencing through these three reconfigurationsat run-time, one configuration at a time. RRANN has been fully implemented with Xilinx FPGAs, tested and shown to increase the functional density of a network up to 500% when compared to FPGA-based implementations that do not use RTR.     

Optimization of Pattern Matching Circuits for Regular Expression on FPGA

Regular expressions are widely used in the network intrusion detection system (NIDS) to represent attack patterns. Previously, many hardware architectures have been proposed to accelerate regular expression matching using field-programmable gate array (FPGA) because FPGAs allow updating of new attack patterns. Because of the increasing number of attacks, we need to accommodate a large number of regular expressions on FPGAs. Although the minimization of logic equations has been studied intensively in the area of computer-aided design (CAD), the minimization of multiple regular expressions has been largely neglected. This paper presents a novel sharing architecture allowing our algorithm to extract and share common subregular expressions. Experimental results show that our sharing scheme significantly reduces the area of pattern matching circuits for regular expression.     

A Routability-Aware Algorithm for Both Global and Local Interconnect Resource Test and Diagnosis of Xilinx SRAM-FPGAs

With increasing scale of Field Programmable Gate Arrays (FPGAs), architecture of interconnect resources (IRs) in FPGA is becoming more and more complicated. IR testing plays an important role to guarantee correct functionality of FPGAs. Usually, architecture of Global IRs is regular, while architecture of Local IRs is more complicated compared to Global IRs. In the paper, a generic IR model revealing the connection relationships for both Global and Local IRs in Xilinx series FPGAs is studied. A routability-aware algorithm based on the generic IR model is also presented. Test configurations (TCs) can be automatically generated by the proposed algorithm. Thus, both Global and Local IRs can be tested with identical method. Further, the algorithm is generic and independent of type and size of FPGAs. The algorithm is evaluated in Virtex series FPGAs. Experimental results demonstrate that the routing algorithm is applicable to Virtex series FPGAs with higher IR coverage achieved.     

Analysis of ageing effects on ARTIX7 XILINX FPGA

FPGAs are considered as an attractive alternative to ASICs, thanks to their reconfigurability and their low development costs. However, since they are the first experiencing new technology nodes, their ability to tackle VLSI ageing mechanisms is crucial, especially in critical applications such as space and avionics ones. This work aims to understand ageing degradation on FPGAs. An experimental approach is adopted in order to characterize the effects of degradation on FPGAs Look up tables (LUTs). Different stress conditions were tested to accelerate ageing process and identify the mechanisms behind. Ageing tests have been executed on a total of 17 FPGAs belonging to Artix7 XILINX family. Results show that Negative-Bias Temperature Instability ageing damage is the main cause of timing degradation on the studied FPGAs.     

Placement and routing tools for the Triptych FPGA

Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniques are often developed specifically for only a single FPGA architecture. In this paper we describe automatic mapping tools for Triptych, an FPGA architecture with improved logic density and performance over commercial FPGAs. These tools include a simulated-annealing placement algorithm that handles the routability issues of fine-grained FPGAs, and an architecture-adaptive routing algorithm that can easily be retargeted to other FPGAs. We also describe extensions to these algorithms for mapping asynchronous circuits to Montage, the first FPGA architecture to completely support asynchronous and synchronous interface applications     

Wiring requirement and three-dimensional integration technology for field programmable gate arrays

In this paper, analytical models for predicting interconnect requirements in field-programmable gate arrays (FPGAs) are presented, and opportunities for three-dimensional (3-D) implementation of FPGAs are examined. The analytical models for two-dimensional FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with more than 20 K four-input look-up tables, the reduction in channel width, interconnect delay and power dissipation can be over 50% by 3-D implementation.     

Hardware/Software Design Considerations for Automotive Embedded Systems

An increasing number of safety-critical functions is taken over by embedded systems in today's automobiles. While standard microcontrollers are the dominant hardware platform in these systems, the decreasing costs of new devices as field programmable gate arrays (FPGAs) make it interesting to consider them for automotive applications. In this paper, a comparison of microcontrollers and FPGAs with respect to safety and reliability properties is presented. For this comparison, hardware fault handling was considered as well as software fault handling. Own empirical evaluations in the area of software fault handling identified advantages of FPGAs with respect to the encapsulation of real-time functions. On the other hand, several dependent failures were detected in versions developed independently on microcontrollers and FPGAs.      

Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering

Modern FPGAs have a great market share in hardware prototyping, massive parallel systems and reconfigurable architectures. Although the field-programmability of FPGAs is an effective feature in the growth and diversity of their applications; it has caused security concerns for IPs/Designs on FPGAs. Recent researches show that a reliable mechanism is required to protect the IPs/applications on FPGAs against malicious manipulations during all stages of design lifecycle, especially when they are operating in the field. In this paper, we propose a new tamper-resistant design methodology (Security Path methodology) and a revised security-aware FPGA architecture. This methodology protects the configured design against tampering attacks in parallel with the normal operation of the circuit. When the attack is discovered, the normal data flow is obfuscated and the circuit is blocked. Experimental results show that this methodology provides near full coverage in tampering detection with overhead of 12.32 % in power, 12 % in delay and 38 % in area.     

FPGA逻辑块管脚分布的研究

通过CAD实验对FPGA的逻辑块管脚分布进行了研究。结果表明,不管是正方形还是矩形FPGA,四周型分布均能获得比上下型分布更好的布线面积,且四周型分布的正方形FPGA有最好的面积有效性。另外一个重要结论是,对于列数／行数位于1．5和3．5之间的矩形FPGA,上下型分布的面积有效性近似于四周型分布。     

ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture

Logic emulation is so far the fastest method to verify the system functionality in the gate level before chip fabrication. Field-programmable gate array (FPGA)-based logic emulator with large gate capacity generally comprises a large number of FPGAs or special processors connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. This paper first describes a new interconnection architecture called TOMi (Time-multiplexed, Off-chip, Multicasting interconnection) and proposes a circuit partitioning algorithm called ATOMi (Algorithm for TOMi) for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi. ATOMi reduces the number of off-chip signal transfers to optimize the performance for multi-FPGA system implemented by TOMi. Experimental results using Partitioning93 benchmarks show that, by adopting the proposed TOMi interconnection architecture along with ATOMi, the pin count is reduced to 14.4%–88.6% while the critical path delay is reduced to 66.1%–90.1% compared to traditional architectures including mesh, crossbar, and VirtualWire architecture.     

A bitstream readback-based automatic functional test and diagnosis method for Xilinx FPGAs

In this paper, a novel bitstream readback-based test and diagnosis method including a bitstream parsing algorithm as well as a corresponding bitstream readback-based fault and diagnosis algorithm for Xilinx FPGAs is presented. The proposed method can be applied to both configurable logic block (CLB) and interconnect resource (IR) test. Further, the algorithm is suitable for all Virtex and Spartan series FPGAs. The issues such as fault coverage, diagnostic resolution, I/O numbers, as well as configuration numbers not addressed well by some previous works can be solved or partly relieved. The proposed method is evaluated by testing several Xilinx series FPGAs, and experimental results are provided.     

Path reuse-aware routing for non-volatile memory based FPGAs

Non-volatile memory-based FPGAs (NV-FPGAs) are expected to replace traditional SRAM-based FPGAs to achieve higher scalability and lower power consumption. Yet the slow write performance of NVMs not only challenges FPGA reconfiguration speed and overhead but also constrains the programming cycles of FPGAs. To efficiently configure switch boxes, the majority component of an FPGA, this paper presents a routing path reuse technique. The reconfiguration cost of routing resources is first modeled mathematically and then minimized through a reuse-aware routing algorithm, which is incorporated into the standard VTR CAD tool. Experiments on standard MCNC and Titan benchmarks show that the proposed scheme is able to achieve as much as 58% path reuse rate and reduce as much as 45% configuration cost for routing resources.     

Multitier Wireless Communications

Next-generation computing systems will be highly integrated using wireless networking. The Rice Everywhere NEtwork (RENÉ) project is exploring the integration of WCDMA cellular systems, high speed wireless LANs, and home wireless networks to produce a seamless multitier network interface. We are currently developing a simulation acceleration testbed and a multitier network interface card (mNIC) consisting of DSP processors, custom VLSI ASICs, and FPGAs for baseband signal processing to interact with the various RF units and the host processor. This testbed will also allow us to explore high performance algorithm alternatives through computer aided design tools for rapid prototyping and hardware/software co-design of embedded systems.     

Optimizing energy efficiency of CNN-based object detection with dynamic voltage and frequency scaling

On the one hand,accelerating convolution neural networks(CNNs)on FPGAs requires ever increasing high energy efficiency in the edge computing paradigm.On the other hand,unlike normal digital algorithms,CNNs maintain their high robustness even with limited timing errors.By taking advantage of this unique feature,we propose to use dynamic voltage and frequency scaling(DVFS)to further optimize the energy efficiency for CNNs.First,we have developed a DVFS framework on FPGAs.Second,we apply the DVFS to SkyNet,a state-of-the-art neural network targeting on object detection.Third,we analyze the impact of DVFS on CNNs in terms of performance,power,energy efficiency and accuracy.Compared to the state-of-the-art,experimental results show that we have achieved 38%improvement in energy efficiency without any loss in accuracy.Results also show that we can achieve 47%improvement in energy efficiency if we allow 0.11%relaxation in accuracy.     

Total Power Modeling in FPGAs Under Spatial Correlation

This work describes a novel approach for total power estimation in field-programmable gate arrays (FPGAs) while considering spatial correlation among the different signals in the design. The signal probabilities under spatial correlations are used to properly model the dynamic power dissipation and the state-dependency of the leakage power dissipation in the logic and routing resources of FPGAs. Moreover, the proposed model accounts for power due to glitches. The accuracy of the developed power estimation technique is compared with that of HSpice simulations and other FPGA power estimation techniques that assume spatial independence. It is found that the spatial independence assumption can overestimate power dissipation in FPGAs by an average of 19%.      

RapidIO总线在组合导航系统中的应用

简要地从 RapidIO 的主要技术特点、体系结构、系统拓扑、协议层次和流量控制等方面对其进行分析,提出了一种基于 RapidIO 总线的组合导航系统的架构方案。通过指定高性能包交换互连技术,在系统内的微处理器、DSP、FPGA、通信和网络处理器以及外设之间进行数据和控制信息传输,RapidIO 架构消除了传统共享总线的瓶颈问题,极大地提高了系统整体性能。