一种基于自偏置技术的低功耗锁相环设计

采用TSMC 0.13 μm CMOS工艺,设计并实现了一种低功耗、具有固定的环路带宽与工作频率之比,以及良好相位噪声性能的自偏置锁相环(PLL)芯片电路。仿真结果表明,该PLL电路工作频率范围为200~800 MHz,在480 MHz输出频率的相位噪声为-108 dBc@1 MHz,1.2 V电源供电下消耗功耗2 mW。芯片核心电路面积仅为0.15 mm²,非常适合应用于系统集成。     

一种自偏置锁相环电路的分析与测试

自偏置锁相环电路结构自提出以来便受到了极大的关注,人们普遍认为其可以改善锁相环的相位噪声。为了验证这种结构能否改善传统锁相环电路的相位噪声性能,根据锁相环的基本理论设计并实现了一种可进行重新配置的锁相环电路结构,电路中的锁相环结构可以在传统锁相环、自偏置锁相环和普通偏置锁相环之间进行切换。使用信号源分析仪分别测试得到了这3种结构的相位噪声性能：自偏置锁相环的带内相位噪声比普通锁相环恶化了约6 dB,而采用普通偏置锁相环使环路等效分频比减小5的相位噪声比普通锁相环改善了约14 dB。理论与测试结果均表明,自偏置锁相环和普通锁相环相比,环路反馈回路中的分频比并没有有效降低,因此自偏置锁相环的相位噪声性能并没有得到改善。     

一种固定延时的宽频带延迟锁相环

本文提出的延迟锁相环结构能够提供比较宽的工作频率范围，并且可以实现延迟时间固定为一个输入时钟的周期。为了提高工作频率和避免错锁现象，该电路采用了相位选择电路和启动控制电路。这种延迟锁相环从理论上来说，工作频率范围可以达到1／(n×Tdmax）-1/Tdmin,Tdmax是延迟单元的最大延迟时间，n为延迟线中延迟单元的数目，Tdmin是延迟单元最小的延迟时间。设计采用了2．5V，0．25μ m First Silicon CMOS工艺来实现，通过仿真测得该延迟锁相环的工作频率范围为200MHz～1GHz，并且输入和输出之间的总延时恰好为一个输入时钟周期。     

一种超高频RFID阅读器中的双环锁相环

采用GF 130 nm CMOS工艺,设计了一种低功耗低噪声的电荷泵型双环锁相环,该锁相环可应用于符合国际及中国标准的超高频射频识别阅读器芯片。通过对双环锁相环在带宽和工作频率上的合理设置,以及对压控振荡器中变容二极管偏置电阻及电荷泵中参考杂散的理论分析和优化设计,改进了锁相环电路功耗和噪声性能。仿真结果表明,该锁相环在输出工作频率范围为840~960 MHz时,功耗为31.21 mW,在距中心频率840.125 MHz频偏100 kHz处的相位噪声为 -108.5 dBc/Hz,频偏1 MHz处的相位噪声为 -132.3 dBc/Hz。与同类锁相环相比较,本文电路在噪声和功耗方面具有一定优势。     

自偏置锁相环的相位噪声分析

自偏置锁相环被提出以来,被认为能够以简单的电路结构降低锁相环的环内分频比从而改善环路带宽内的相位噪声。从噪声的相关性出发,分析了信号经过自偏置电路后对相位噪声的影响,并通过计算自偏置锁相环的相位传递函数得到其相位噪声模型,对比于传统单环式锁相环结构,其环内分频比并未降低。通过设计一2. 28～2. 52GHz 的自偏置锁相环,对其相位噪声进行测试并与传统单环和偏置式锁相环进行比较,测试结果也表明自偏置锁相技术并不能降低锁相环的带内相位噪声。     

一种可快速锁定的低抖动自偏置锁相环设计

设计了一种可快速锁定、具有固定带宽比和良好抖动性能的自偏置锁相环.采用增加VCO延迟单元输出节点放电时间常数的方法,对VCO进行优化设计,获得良好的抖动性能.基于0.25μm混合信号CMOS工艺进行设计和仿真,在2.5 V电源供电条件下,锁相环的工作频率范围为600～1500MHz,在1250 MHz输出频率的峰峰值抖动为14.3 ps,核心电路功耗为44mW.在不同工艺条件下的仿真结果表明,PLL在不同工艺条件下均具有良好的抖动性能.     

一种高性能CMOS电荷泵的设计

设计了一种用于电荷泵锁相环的CMOS电荷泵电路。电路中采用3对自偏置高摆幅共源共栅电流镜进行泵电流镜像,增大了低电压下电荷泵的输出电阻,实现了上下两个电荷泵的匹配。为消除单端电荷泵存在的电荷共享问题,引入了带宽幅电压跟随的半差分电流开关结构,使电荷泵性能得以提高。设计采用0.18μm标准CMOS工艺。电路仿真结果显示,在0.35～1.3V范围内泵电流匹配精度达0.9%,电路工作频率达250MHz。     

一种自适应带宽低抖动PLL设计

设计了一种宽调节范围自适应带宽的低抖动锁相环倍频器(PLL)。通过采用自偏置技术,使得电荷泵电流和运算放大器的输出阻抗随工作频率成比例变化,从而使阻尼因子保持固定、环路带宽跟随输入参考频率自动调整,以及PLL在整个输出频率范围内保持最佳的抖动性能。电路采用SMIC 0.18 μm CMOS工艺进行设计,后仿真验证表明,该PLL电路能够在0.35~2.1 GHz的输出频率范围内输出良好的低抖动信号,输出频率为2.1 GHz时,均方根抖动为2.47 ps。     

一种单片低相噪宽带频率合成器

基于0.18 μm SiGe BiCMOS工艺,设计实现了一种低相噪宽带锁相环型频率合成器电路,分析了锁相环型频率合成器中优化相噪和拓宽工作频率的途径和方法。提出了一种低输出噪声参考缓冲电路和高速Delta-sigma调制器结构,改进了MOS管结构的电荷泵电路,采用÷2/3级联可编程分频器结构,实现了宽工作频带。流片测试结果表明,归一化底板相位噪声达到-232.2 dBc/Hz,工作频率可覆盖1~20 GHz。     

基于0.18μm CMOS工艺2.5GHz电荷泵锁相环的设计

主要设计一个基于标准0.18μm CMOS工艺的电荷泵锁相环电路,首先从理论上分析了锁相环的工作原理,进而分析了鉴相器、电荷泵、压控振荡器的结构和性能。在理论研究的基础上,再由IC设计软件Cadence进行设计优化,最终实现了工作频率在2.5 GHz,输出波形占空比达到50%电荷泵锁相环电路,并给出了仿真结果。     

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators

A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm²     

A 1.41–1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler

A 1.41–1.72 GHz fractional-N phase-locked loop (PLL) frequency synthesizer with a PVT insensitive voltage-controlled oscillator (VCO) is presented. In this PLL, a VCO with process, voltage, and temperature (PVT) insensitive bias circuit, and a divided-by-7/8 prescaler with improved multi-phase frequency divider are adopted. A novel multi-stage noise shaping (MASH) sigma-delta modulator (SDM) is adopted here. A new combination of low-current-mismatch charge pump (CP) and a phase/frequency detector (PFD) is proposed in this paper. Using Hejian Technology CMOS 0.18 μm analog and digital mixed-mode process, a fractional-N PLL prototype circuit is designed, the VCO in the prototype circuit can operate at a central frequency of 1.55 GHz, and its phase noise is −121 dBc/Hz at 1.0 MHz, the variety of phase noise is depressed by about 1.4 dB with the help of PVT insensitive bias. Under a 1.8-V supply voltage, the phase noise of the PLL is −113 dBc/Hz at 1.0 MHz.     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

Low-jitter process-independent DLL and PLL based on self-biasedtechniques

Delay-locked loop (DLL) and phase-locked loop (PLL) designs based upon self-biased techniques are presented. The DLL and PLL designs achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly, low input tracking jitter. Both the damping factor and the bandwidth to operating frequency ratio are determined completely by a ratio of capacitances. Self-biasing avoids the necessity for external biasing, which can require special bandgap bias circuits, by generating all of the internal bias voltages and currents from each other so that the bias levels are completely determined by the operating conditions. Fabricated in a 0.5-μm N-well CMOS gate array process, the PLL achieves an operating frequency range of 0.0025 MHz to 550 MHz and input tracking jitter of 384 ps at 250 MHz with 500 mV of low frequency square wave supply noise     

Ring voltage controlled oscillator for high-speed PLL systems

A circuit of a ring voltage controlled oscillator (VCO), which is to be used in high-speed phase-locked loop (PLL) systems integrated into programmable logic integrated circuits, is proposed. The maximum operating frequency of a VCO in 180 nm CMOS is shown by simulation to be able to reach 2 GHz in all operating conditions with the phase noise being ?99 dB/Hz and detuning frequency being 1 MHz.     

A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 Voperation

This paper describes a phase-locked loop (PLL) based frequency synthesizer. The voltage-controlled oscillator (VCO) utilizing a ring of single-ended current-steering amplifiers (CSA) provides low noise, wide operating frequencies, and operation over a wide range of power supply voltage. A programmable charge pump circuit automatically configures the loop gain and optimizes it over the whole frequency range. The measured PLL frequency ranges are 0.3-165 MHz and 0.3-100 MHz at 5 V and 3 V supplies, respectively (the VCO frequency is twice PLL output). The peak-to-peak jitter is 81 ps (13 ps rms) at 100 MHz. The chip is fabricated with a standard 0.8-μm n-well CMOS process     

Frequency presetting and phase error detection technique for fast-locking phase-locked loop

A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35 μm CMOS process, with a supply voltage of 3.3 V.     

Design of a PLL with improved locking range and its biomedical applications

This paper describes a phase locked loop employing a low voltage VCO using modified ECL inverter cells. The VCO circuit employed, features a positive feed back scheme to improve the operating frequency. The phase detector used in the PLL also uses a positive feedback scheme to improve the locked range and to reduce supply voltage of operation of the entire circuit. An improvement of locked range of around 35% was obtained from circuit simulation (using PSPICE) as well as from practical circuit, using discrete components. The minimum supply voltage required here is 2.5 volts. Some biomedical applications of this PLL are also proposed.     

A calibration-less low error two-point modulation transmitter for 802.15.4 application

A low power phase locked loop (PLL) based transmitter for wireless sensor application is presented in this paper. The transmitter adopts two-point modulation architecture in high-pass and low-pass paths of PLL; it modulates the divide ratio through sigma-delta modulator and voltage controlled oscillator (VCO) frequency tuning port simultaneously. An interleave-biased varactor pair is used to linearize the frequency tuning curve of the VCO. Besides, to achieve the desired frequency deviation of 500 kHz, we use a capacitance desensitization technique through combined parallel and serial capacitances with tuning varactors. This topology does not need the minimum size varactor, which is sensitive to process variation and mismatch. Implemented in standard 0.18-μm CMOS process, the transmitter achieves a 5.2 % FSK error for 2 Mbps data rate without using any auto-calibration circuit, consuming 7.8 mW power. Loop filter and crystal are the only off-chip components.     

A self-calibration technique for wide tuning range PLLs

This paper presents a new calibration technique applicable for wide tuning range phase locked loops (PLLs) using very low gain voltage controlled oscillators (VCO). This technique uses the PLL main loop for the coarse and fine tuning of the VCO. Instead of using two loops which has been reported in previous works, in this work the VCO tuning voltage is used to calibrate the VCO switch capacitor array. Since the proposed calibration circuit operates in a closed loop form, it can be used for channel selection as well as adjusting for process, voltage and temperature variations. In addition, the calibration circuit has been used to set the VCO tail current in order to optimize VCO phase noise. A prototype frequency synthesizer has been designed in 0.18-μm CMOS process to work for a frequency range from 2.4 to 2.72 GHz. Simulation results show that using the proposed technique, a spur level of ?60 dB at 5 MHz offset from carrier was achieved while having negligible power overhead.