Jitter requirements of the sampling clock in software radio receivers

The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers.     

A 64-MHz clock-rate /spl Sigma//spl Delta/ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.     

下一代光传输系统中超高速ADC芯片性能测试方法

针对下一代光传输系统对模数转换器（ADC）高采样率、大带宽的要求,提出一种针对该类ADC动态性能的测试方法.通过分析光传输系统中ADC芯片的特点,解决了采样时钟无法直接测量,输出数据难以捕获,分辨率不易统计,插损非线性导致带宽测量偏差等问题,并将该方法应用于光传输、雷达、卫星等高数据率场景所用超高速ADC芯片的评测中.测试结果表明,该方法解决了最高采样率70GSPS带宽16GHz的超高速ADC测试的关键问题,基本满足下一代400Gbps光传输系统对ADC动态性能测试的要求.     

A 20-mW 640-MHz CMOS Continuous-Time Σ∆ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply     

Software-synchronized all-optical sampling for fiber communication systems

This paper describes a software-synchronized all-optical sampling system that presents synchronous eye diagrams and data patterns as well as calculates accurate Q values without requiring clock recovery. A synchronization algorithm is presented that calculates the offset frequency between the data bit rate and the sampling rate, and as a result, synchronous eye diagrams can be presented. The algorithm is shown to be robust toward poor signal quality and adds less than 100-fs timing drift to the eye diagrams. An extension of the software synchronization algorithm makes it possible to automatically find the pattern length of a periodic data pattern in a data signal. As a result, individual pulses can be investigated and detrimental effects present on the data signal can be identified. Noise averaging can also be applied. To measure accurate Q values without clock recovery, a high sampling rate is required in order to establish the noise statistics of the measured signal before any timing drift occurs. This paper presents a system with a 100-MHz sampling rate that measures accurate Q values at bit rates as high as 160 Gb/s. The high bandwidth of the optical sampling system also contributes to sampling more noise, which in turn results in lower Q values compared with conventional electrical sampling with a lower bandwidth. A theory that estimates the optically sampled Q values as a function of the sampling gate width is proposed and experimentally verified.     

Optical Spatial Quantization for Higher Performance Analog-to-Digital Conversion

A novel optical spatial quantized analog-to-digital conversion scheme for real-time conversion at ultrahigh sampling frequencies is presented. At each sampling instant, the analog input voltage deflects an optical sampling pulse onto an array of photodetectors. The output code is derived from the output voltages of the photodetectors on which the optical beam lands. Particular benefits of the proposed architecture are significant reduction in jitter through the use of a mode-locked laser to generate the sampling pulses, high quantization bandwidth through a fully optical quantization scheme, and the system simplicity through the use of just one phase modulator and an embedded binary encoder in the binary-connected photodetector arrays. We experimentally demonstrate an eight-level quantization consuming only 7.2 pJ per quantization with 18-GHz bandwidth, projected to an estimated bandwidth of 30 GHz. Measured 8-ps full-width half-maximum photodetector output voltages promise the potential of realizing a 3-bit 125-GS/s analog-to-digital converter.      

Very-high-speed fibre-optic networks for broadband communications

Single-mode optical fibres have an enormous transmission bandwidth which can support ultra-high-speed digital transmission and networking. The use of electrical signal-processing, however, ultimately limits the network capacity. To eliminate the throughput bottleneck, all-optical processing techniques should be employed in a fibre-optic network. This paper discusses several schemes for implementing optical time division multiple access (OTDMA) networks with the emphasis on optical clock distribution, synchronisation and all-optical detection. The use of a fast-switching bistable laser diode as an all-optical threshold detector and data regenerator is suggested. A dual-wavelength OTDMA technique is investigated, which can be used for digital TV or future HDTV distributions. Moreover, an efficient multiple access scheme, called wavelength division multiple access with optical time division multiplexing (WDMA-OTDM), is proposed for broadband communication services. It is shown that WDMA-OTDM has all the advantages possessed by the individual OTDMA and WDMA schemes but offers improved flexibility and capacity     

一种具有采样带宽补偿的高性能采样/保持电路

针对中频采样模数装换器中的宽带采样/保持电路,提出了一种新颖的电荷交换补偿（CEC）技术.该技术通过消除采样开关有限导通电阻的影响,补偿了采样带宽,并避免了时钟馈通和电荷注入的加剧.同时设计了具有AB类输出的低功耗两级运放,在1.8V电源下为该采样/保持提供了3V峰-峰值的输入范围.该采样/保持电路在100Ms/s的采样率下,对于200MHz输入信号达到了94dB的无杂散动态范围.在5.5pF的负载下,功耗仅为26mW.     

一种具有采样带宽补偿的高性能采样/保持电路

针对中频采样模数装换器中的宽带采样/保持电路,提出了一种新颖的电荷交换补偿(CEC)技术.该技术通过消除采样开关有限导通电阻的影响,补偿了采样带宽,并避免了时钟馈通和电荷注入的加剧.同时设计了具有AB类输出的低功耗两级运放,在1.8V电源下为该采样/保持提供了3V峰-峰值的输入范围.该采样/保持电路在100Ms/s的采样率下,对于200MHz输入信号达到了94dB的无杂散动态范围.在5.5pF的负载下,功耗仅为26mW.     

A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibitdelta-sigma modulation at 8× oversampling ratio

A 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications and high-speed instrumentation has been developed. A 2-1-1 cascaded delta-sigma modulator (DSM) employing 4-b quantizers in every stage makes all quantization noise sources negligible at 8× oversampling ratio, Data weighted averaging with bi-directional rotation eliminates tones generated by multibit digital-to-analog converter (DAC) nonlinearity to increase the spurious-free dynamic-range (SFDR). Switched-capacitor design techniques using low-threshold transistors reduce front-end sampling distortion. The 24.8 mm² chip in 0.5-μm CMOS also integrates the decimation filter and voltage reference. The ADC achieves 90-dB signal-to-noise ratio (SNR) in the 1.25-MHz bandwidth and 102-dB SFDR with 270-mW power dissipation     

Experimental Demonstration of All-Optical Analog-to-Digital Conversion With Balanced Detection Threshold Scheme

A novel balanced detection threshold scheme for all-optical analog-to-digital conversion is experimentally demonstrated. A 4-bit 10-GSamples/s all-optical analog-to-digital converter based on phase-shifted optical quantization and a balanced detection threshold scheme is realized to quantize a 9.9-GHz sinusoidal electrical signal, achieving a spur-free dynamic range of 24.2 dB. Compared with single-ended detection, the quantization result is improved with the balanced threshold scheme due to reducing the influence of the power fluctuation and improving the receiver sensitivity.      

Design and analysis of a CMOS passive Σ∆ ADC for low power RF transceivers

Design and analysis of a Σ∆ modulator with a passive switched capacitor loop filter is presented. Design steps for optimum loop filter design for quantization noise suppression and thermal noise reduction is outlined. Design specifications for sampling clock phase noise, reference buffer and input buffer settling is analyzed. Presented design has a 2nd-order loop filter and uses only metal-metal capacitors and thin oxide digital transistors with no additional components occupying less than 0.1 mm² silicon area in 0.13 μm CMOS digital process. Measurement results show that the ADC achieves 80 dB peak SNR at a 100 kHz integration bandwidth with 1 pJ/sample conversion efficiency. With decimation filter power consumption of 0.22 mW at 104 MHz sampling rate, the ADC consumes only about 1 mA at 1.5 V for each channel.     

一种全集成8位2.16 GS/s SAR ADC

设计了一种8位2.16 GS/s四通道、时间交织逐次逼近型模数转换器(TI-SAR ADC)。单通道SAR ADC采用数据环、异步时钟环的双环结构实现高速工作。采用带复位开关的动态比较器缩短量化时间,提高比较精度。结合反向单调切换时序,逐步增大共模电压,提升量化速度。基于55 nm CMOS工艺设计,后仿真结果表明,在1.2 V电源电压下,该TI-SAR ADC消耗 42.6 mA 电流,在奈奎斯特输入频率下,FOM值为212 fJ/(conv.step),信噪失真比(SNDR)为42.7 dB,无杂散动态范围(SFDR)为53 dB。芯片整体版图面积为3.4 mm²。     

High-performance optical-fiber-nonlinearity-based optical waveform monitoring

An all-optical waveform sampling system with simultaneous submilliwatt optical signal sensitivity (20-dB signal-to-noise ratio) and subpicosecond temporal resolution over more than 60-nm optical bandwidth is demonstrated in this paper. The optical sampling was implemented by four-wave mixing in a 10-m highly nonlinear fiber using a sampling pulse source with a sampling pulse peak power of only 16 W. The sampling performance was evaluated in terms of sensitivity, temporal resolution, and optical bandwidth with respect to fiber length, sampling pulse source wavelength offset from the zero-dispersion wavelength of the highly nonlinear fiber, sampling pulse peak power, and walk-off due to chromatic dispersion. This paper also presents a summary of the available methods to achieve polarization-independent optical sampling as well as a brief summary of the available sampling pulse sources viable for optical sampling.     

过采样技术在扭矩扳子检定仪中的研究

过采样技术能够有效减小模数转换过程的噪声功率,从而提高模数转换器的分辨率。基于奈奎斯特采样定理,对模数转换器的采样频率和量化误差进行分析。通过理论分析得出,每增加一位分辨率需要增加4倍采样频率,并提出了3个影响过采样技术有效性的因素。通过在扭矩扳子检定仪中的应用过采样技术,使扭矩扳子检定仪的模数转换器提高了4位分辨率。在此基础上,对过采样技术进行了改进,使扭矩扳子检定仪的精度提高到0.3%以上。     

All-optical enhancement of clock and clock-to-data suppressionratio of NRZ data

A scheme for all-optical enhancement of clock and clock-to-data suppression ratio of nonreturn-to-zero (NRZ) data based on self-phase modulation is proposed and demonstrated. More than 3-dB clock enhancement and 11-dB clock-to-data suppression ratio enhancement has been realized by a semiconductor optical amplifier (SOA) and fiber Bragg grating (FBG) in reflection. Clock enhancement of more than 6 dB is possible using a FBG in transmission. Using this technique, all-optical clock recovery from NRZ data has been demonstrated     

A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/sADC array in 1.2-μm CMOS

A 10-bit 5-MS/s successive approximation ADC cell and a 70-MS/s parallel ADC array based on this cell, designed and fabricated in a 1.2-μm CMOS process, are presented. The ADC cell was designed to have an input bandwidth of more than 35 MHz and a sampling time of 14 nS at a clock rate of 70 MHz. The parallel ADC array consists of 14 such cells which are timed in one clock cycle skew successively in order to obtain digitized data every clock cycle. A two-step principle based on unsymmetrical dual-capacitor charge-redistribution-coupling has been used. With the help of a reset function, the comparator presents a fast response to the successive comparison. Each successive approximation ADC cell occupies an area of 0.6 mm² and the core of the parallel ADC array occupies an area of 2.7×3.3 mm². The power consumptions for the cell and the parallel ADC array are 18 mW and 267 mW respectively     

0.13 μm CMOS 60 dB SFDR的8 bit 250 MS/s模数转换器

论述了一种高速度低功耗的8位250 MHz采样速度的流水线型模数转换器(ADC).在高速度采样下为了实现大的有效输入带宽,该模数转换器的前端采用了一个采样保持放大器(THA).为了实现低功耗,每一级的运放功耗在设计过程中具体优化,并在流水线上逐级递减.在250 MHz采样速度下,测试结果表明,在1.2 V供电电压下,所有模块总功耗为60 mw.在19 MHz的输入频率下,SFDR达到60.1 dB,SNDR为46.6 dB,有效比特数7.45.有效输入带宽大于70 MHz.该ADC采用TSMC 0.13μm CMOS 1P6M工艺实现,芯片面积为800 μm×700μm.     

All-Optical 3R Burst-Mode Reception at 40 Gb/s Using Four Integrated MZI Switches

We demonstrate an all-optical retime, reshape, reamplify (3R) burst-mode receiver (BMR) operating error-free with a 40-Gb/s variable-length asynchronous optical data packets that exhibit up to 9-dB packet-to-packet power variation. The circuit is completely based upon hybrid integrated Mach-Zehnder interferometric (MZI) switches as it employs four cascaded MZIs, each one performing a different functionality. The 3R burst-mode reception is achieved with the combination of two discrete all-optical subsystems. A reshape, reamplify BMR employing a single MZI is used first to perform power equalization of the incoming bursts and provide error-free data reception. This novel approach is experimentally demonstrated to operate error-free, even for a 9-dB dynamic range of power variation between bursty data packets and for a wide range of average input power. The obtained power-equalized data packets are then fed into a 3R regenerator to improve the signal quality by reducing the phase and amplitude jitter of the incoming data. This packet-mode 3R regenerator employs three MZIs that perform wavelength conversion, clock extraction, and data regeneration for every packet separately and operates at 40 Gb/s, exhibiting rms timing jitter reduction from 4 ps at the input to 1 ps at the output and a power penalty improvement of 2.5 dB     

一种具有采样时间扩展功能的异步SAR ADC

SAR ADC每个转换周期的大部分时间被分配给ADC的量化操作,而只剩下少量的时间用来进行信号采样。在短时间内完成高精度的采样,需要前级电路具有更大驱动能力,同时要求ADC的采样开关具有更低的导通电阻。提出了一种交替采样结构,可以在不减少ADC量化时间的前提下,使得SAR ADC的采样时间等于量化时间,由此极大地降低ADC驱动电路的功耗。本文采用上述技术基于Fujitsu 55 nm工艺,实现了40 Msps 10 bit的异步SAR ADC,测试显示ADC有效位可达9.7 bit。