Rubrene thin-film transistors with crystalline channels achieved on optimally modified dielectric surface

We report on the fabrication of rubrene thin-film transistors (TFTs) with surface-modified dielectrics adopting several kinds of self-assembled-monolayer (SAM) on SiO₂/p⁺?Si substrate. With the dielectric of lower surface energy, the crystalline rubrene growth or amorphous-to-crystalline transformation kinetics is faster during in-situ vacuum post-annealing, which was performed after rubrene vacuum deposition. In the present study, hexamethyldisilazane (HMDS) was finally determined to be the most effective SAM interlayer for polycrystalline rubrene channel formation. Our rubrene TFT with HMDS-coated SiO₂ dielectric showed quite a high field mobility of ～10^?2 cm²/V s and a high on/off current ratio of ～10⁵ under 40 V.     

Voltage-tunable SiO2-isolated a-SiC:H and/or a-SiN:H p–i–n thin-film LEDs fabricated on c-Si

A voltage-tunable amorphous p–i–n thin-film light emitting diodes (TFLEDs) with SiO₂-isolation on n⁺-type crystalline silicon (c-Si) has been proposed and fabricated successfully. The structure of the device with i-a-SiC:H and i-a-SiN:H luminescent layers is indium–tin–oxide (ITO)/p⁺-a-Si:H/p⁺-a-SiC:H/i-a-SiC:H/i-a-SiN:H/n⁺-a-SiCGe: H/n⁺-a-SiC:H/n⁺-c-Si/Al. This device revealed a brightness of 695 cd/m² at an injection current density of 300 mA/cm². Its EL (electroluminescence) peak wavelength exhibited blue-shift from 655 to 565 nm with applied forward-bias (V) increasing from 15 to 19 V, but the EL peak wavelength was red-shifted from 565 to 670 nm with further increase of V from 19 to 23 V. By comparing with the EL spectra from p–i–n TFLEDs with i-a-SiC:H or i-a-SiN:H luminescent layer only, the EL spectrum of this TFLED could consist of three bands of radiations from the tail-to-tail-state recombinations in (1) i-a-SiC:H layer, (2) i-a-SiN:H layer, and (3) i-a-SiC:H/p⁺-a-SiC:H junction.     

The effects of surface states and series resistance on the performance of Au/SnO2/n-Si and Al/SnO2/p-Si (MIS) Schottky barrier diodes

We have fabricated two types of Schottky barrier(SBDs),Au/SnO₂/n-Si (MIS1) and Al/SnO₂/p-Si (MIS2), to investigate the surface (N_ss) and series resistance (R_s) effect on main electrical parameters such as zero-bias barrier height (Φ_Bo) and ideality factor (n) for these SBDs. The forward and reverse bias current–voltage (I–V) characteristics of them were measured at 200 and 295 K, and experimental results were compared with each other. At temperatures of 200 and 295 K, Φ_Bo, n, N_ss and R_s for MIS1 Schottky diodes (SDs) ranged from 0.393 to 0.585 eV, 5.70 to 4.75, 5.42×10¹³ to 4.27×10¹³ eV^?1 cm^?2 and 514 to 388 Ω, respectively, whereas for MIS2 they ranged from 0.377 to 0.556 eV, 3.58 to 2.1, 1.25×10¹⁴ to 3.30×10¹⁴ eV^?1 cm^?2 and 312 to 290 Ω, respectively. The values of n for two types of SBDs are rather than unity and this behavior has been attributed to the particular distribution of N_ss and interfacial insulator layer at the metal/semiconductor interface. In addition, the temperature dependence energy density distribution profiles of N_ss for both MIS1 and MIS2 SBDs were obtained from the forward bias I–V characteristics by taking into account the bias dependence of effective barrier height (Φ_e) and R_s. Experimental results show that both N_ss and R_s values should be taken into account in the forward bias I–V characteristics. It has been concluded that the p-type SBD (MIS2) shows a lower barrier height (BH), lower R_s, n and N_ss compared to n-type SBD (MIS1), which results in higher current at both 200 and 295 K.     

Ultra-violet photo-response characteristics of p-Si/i-SiO2/n-ZnO heterojunctions based on hydrothermal ZnO nanorods

Hydrothermal zinc oxide (ZnO) nanorod (NR)-based p-Si/n-ZnO and p-Si/i-SiO₂/n-ZnO heterojunctions were fabricated, and the effects of interfacial native SiO₂ (~4 nm) on the I-V characteristics of heterojunctions under dark and ultra-violet illumination conditions were investigated. First, the structural and optical properties of ZnO seed crystals grown by sol-gel method and hydrothermal ZnO NRs on two different substrates of p-Si and p-Si/i-SiO₂ were examined, and more improved optical and crystalline quality was obtained as revealed by photoluminescence and X-ray diffraction. The p-i-n heterojunctions showed ~3 times greater forward-bias currents and enhanced rectifying property than those of p-n junctions, which is attributed to the role of native SiO₂ in carrier confinement by promoting the electron-hole recombination current through the deep level states of ZnO crystal. The measured ratios of photocurrent to dark current of the p-i-n structure were also greater under reverse bias (92–260) and forward bias (2.3–7.1) conditions than those (28–225 for reverse bias, 1.6–6.8 for forward bias) of p-n structure, and the improved photosensitivity of the p-i-n structure under reverse bias is due to lower density of recombination centers in the ZnO NR crystals. Fabricated ZnO NR heterojunction showed repeatable and fast photo-response transients under forward bias condition of which response and recovery times were 7.2 and 3.5 s for p-i-n and 4.3 and 1.7 s for p-n structures, respectively.     

Characteristics of RF reactive sputter-deposited Pt/SiO2/n-InGaN MOS Schottky diodes

All RF sputtering-deposited Pt/SiO₂/n-type indium gallium nitride (n-InGaN) metal–oxide–semiconductor (MOS) diodes were investigated before and after annealing at 400 °C. By scanning electron microscopy (SEM), the thickness of Pt, SiO_2, n-InGaN layer was measured to be ~250, 70, and 800 nm, respectively. AFM results also show that the grains become a little bigger after annealing, the surface topography of the as-deposited film was smoother with the rms roughness of 1.67 nm and had the slight increase of 1.92 nm for annealed sample. Electrical properties of MOS diodes have been determined by using the current–voltage (I–V) and capacitance–voltage (C–V) measurements. The results showed that Schottky barrier height (SBH) increased slightly to 0.69 eV (I–V) and 0.82 eV (C–V) after annealing at 400 °C for 15 min in N₂ ambient, compared to that of 0.67 eV (I–V) and 0.79 eV (C–V) for the as-deposited sample. There was the considerable improvement in the leakage current, dropped from 6.5×10⁻⁷ A for the as-deposited to 1.4×10⁻⁷ A for the 400 °C-annealed one. The annealed MOS Schottky diode had shown the higher SBH, lower leakage current, smaller ideality factor (n), and denser microstructure. In addition to the SBH, n, and series resistance (R_s) determined by Cheungs׳ and Norde methods, other parameters for MOS diodes tested at room temperature were also calculated by C–V measurement.     

Model based precise analysis of the injection currents in Al/ZrO2/Al2O3/ZrO2/SiO2/Si structures for use in charge trapping non-volatile memory devices

Metal/insulator/Silicon (MIS) capacitors containing multilayered ZrO₂/Al₂O₃/ZrO₂/SiO₂ dielectric were investigated in order to evaluate the possibility of their application in charge trapping non-volatile memory devices. The ZrO₂/Al₂O₃/ZrO₂ stacks were deposited by reactive rf magnetron sputtering on 2.4 nm thick SiO₂ thermally grown on p-type Si substrate. C–V characteristics at room temperature and I–V characteristics recorded at temperatures ranging from 297 K to 393 K were analyzed by a comprehensive model previously developed. It has been found that Poole-Frenkel conduction in ZrO₂ layers occurs via traps energetically located at 0.86 eV and 1.39 eV below the bottom of the conduction band. These levels are identified as the first two oxygen vacancies related levels in ZrO₂, closest to its conduction band edge, whose theoretical values reported in literature are: 0.80 eV, for fourfold, and 1.23 eV, for threefold coordinated oxygen vacancies.     

Resistive switching properties of a thin SiO2 layer with CeOx buffer layer on n+ and p+ Si bottom electrodes

Resistive switching properties of a 2-nm-thick SiO₂ with a CeO_x buffer layer on p⁺ and n⁺ Si bottom electrodes were characterized. The distribution of set voltage (V_set) with the p⁺ Si bottom electrode devices reveals a Gaussian distribution centered in 4.5 V, which reflects a stochastic nature of the breakdown of the thin SiO₂. Capacitance–voltage (C–V) measurements indicate the trapping of electrons by positively shifting the C–V curve by 0.2 V during the first switching cycle. On the other hand, devices with the n⁺ Si bottom electrodes showed a broad distribution in V_set with a mean value higher than that of p⁺ Si bottom electrode devices by 0.9 V. Although no charge trapping was observed with n⁺ Si bottom electrode devices, a degradation in interface states was confirmed, causing a tail in the lower side of the V_set distribution. Based on the above measurements, the difference in the V_set can be understood by the work function difference and the contribution of electron trapping.     

High-performance pentacene field-effect transistors using Al2O3 gate dielectrics prepared by atomic layer deposition (ALD)

High-performance pentacene field-effect transistors have been fabricated using Al₂O₃ as a gate dielectric material grown by atomic layer deposition (ALD). Hole mobility values of 1.5 ± 0.2 cm²/V s and 0.9 ± 0.1 cm²/V s were obtained when using heavily n-doped silicon (n⁺-Si) and ITO-coated glass as gate electrodes, respectively. These transistors were operated in enhancement mode with a zero turn-on voltage and exhibited a low threshold voltage (< −10 V) as well as a low sub-threshold slope (<1 V/decade) and an on/off current ratio larger than 10⁶. Atomic force microscopy (AFM) images of pentacene films on Al₂O₃ treated with octadecyltrichlorosilane (OTS) revealed well-ordered island formation, and X-ray diffraction patterns showed characteristics of a “thin film” phase. Low surface trap density and high capacitance density of Al₂O₃ gate insulators also contributed to the high performance of pentacene field-effect transistors.     

Fabrication of NbN/AlN/NbN junctions with Al embedding circuits on Si membrane for 1.5 THz SIS mixers

A process has been developed to fabricate NbN tunnel junctions and 1.5 THz SIS mixers with Al electrodes and Al/SiO₂/Al microstrip tuning circuits on thin Si membranes patterned on silicon on insulator wafers (SIMOX). High Josephson current density (J_c up to 2×10⁴ A/cm²) NbN/AlN/NbN and NbN/MgO/NbN SIS junctions have been fabricated with a reasonably good V_m quality factor and energy gap values close to 5 meV at 4.2 K on (100) oriented 3 inches SIMOX wafers covered by a thin (∼8 nm) MgO buffer layer. The sputtering conditions critically influence the dielectric quality of both AlN and MgO tunnel barriers as well as the surface losses of NbN electrodes. 0.6-μm Si/SiO₂ membranes are obtained after processing of a whole wafer and etching the individual chips in EDP. Such a technology is applied to the development of a waveguide/membrane SIS mixer for use around 1.5 THz.     

Electrical properties and barrier modification of GaAs MIS Schottky device based on MEH-PPV organic interfacial layer

We report fabrication and electrical characterization of GaAs based metal-interfacial layer-semiconductor (MIS) device with poly[2-methoxy-5-(2^/-ethyl-hexyloxy)-1,4-phenylene vinylene] (MEH-PPV), as an interfacial layer. MEH-PPV raises the barrier height in Al/MEH-PPV/p-GaAs MIS device as high as to 0.87 eV. A Capacitance-Voltage (C–V) characteristic exhibits a low hysteresis voltage with an interface states density of 1.69×10¹¹ cm⁻² eV⁻¹. Moreover, a high transition frequency (f_c) of about 50 kHz was observed in the accumulation mode. The photovoltaic response of Al/MEH-PPV/p-GaAs device was measured under the air masses (AM) 1.0 and 1.5. The open circuit voltage (V_OC), short circuit current (I_SC), fill factor and the efficiency of the Al/MEH-PPV/p-GaAs device were found to be 1.10 V, 0.52 mA, 0.65, and 5.92%, respectively, under AM 1.0 condition.     

Optical and electrical characteristics of 17 keV X-rays exposed TiO2 films and Ag/TiO2/p-Si MOS device

This work presents the effect of varied doses of X-rays radiation on the Ag/TiO₂/p-Si MOS device. The device functionality was observed to depend strongly on the formation of an interfacial layer composed of SiO_x and TiO_y, which was confirmed by the spectroscopic ellipsometry. The XRD patterns showed that the as prepared TiO₂ films had an anatase phase and its exposure to varied doses of 17 keV X-rays resulted in the formation of minute rutile phase. In the X-rays exposed films, reduced Ti³⁺ state was not observed; however a fraction of Ti–O bonds disassociated and little oxygen vacancies were created. It was observed that the device performance was mainly influenced by the nature and composition of the interfacial layer formed at the TiO₂/Si interface. The spectroscopic ellipsometry was used to determine the refractive indices of the interfacial layer, which was 2.80 at λ=633 nm lying in between that of Si (3.87) and TiO₂ (2.11). The dc and frequency dependent electrical measurements showed that the interface defects (traps) were for both types of charge carriers. The presence of SiO_x was responsible for the creation of positive charge traps. The interface trap density and relaxation time (τ) were determined and analyzed by dc and frequency dependent (100 Hz–1 MHz) ac-electrical measurements. The appearance of peak in G/ω vs log (f) confirmed the presence of interface traps. The interface traps initially increased up to exposure of 10 kGy and then decreased at high dose due to compensation by the positive charge traps in SiO_x part of the interface layer. It was observed that large number of interface defects was active at low frequencies and reduced to a limiting value at high frequency. The values of relaxation time, τ ranged from 4.3±0.02×10⁻⁴ s at 0 V and 7.6±0.2×10⁻⁵ s at −1.0 V.     

Frequency and voltage dependency of interface states and series resistance in Al/SiO2/p-Si MOS structure

The capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of Al/SiO₂/p-Si metal-oxide-semiconductor (MOS) Schottky diodes have been measured in the voltage range from ?3 to +3 V and frequency range from 5 KHz to 1 MHz at room temperature. It is found that both C and G/ω of the MOS capacitor are very sensitive to frequency. The fairly large frequency dispersion of C–V and G/ω–V characteristics can be interpreted in terms of the particular distribution of interface states at SiO₂/Si interface and the effect of series resistance. At relatively low frequencies, the interface states can follow an alternating current (AC) signal that contributes to excess capacitance and conductance. This leads to an anomalous peak of C–V curve in the depletion and accumulation regions. In addition, a peak at approximately ?0.2 V appears in the R_s–V profiles at low frequency. The peak values of the capacitance and conductance decrease with increasing frequency. The density distribution profile of interface state density (N_ss) obtained from C_HF–C_LF capacitance measurement also shows a peak in the depletion region.     

Phase transition and surface morphology effects on optical,electrical and lithiation/delithiation behavior of nanostructured Ce-doped V2O5 thin films

Cerium doped V₂O₅ thin films were prepared by the sol−gel process. X-ray diffraction analysis revealed the phase transition from α-V₂O₅ orthorhombic to β-V₂O₅ tetragonal structure by annealing at 400 °C. The SEM and AFM images revealed that annealing temperature changed the surface morphology of the V₂O₅ films from fiber like wrinkle network to elongated sheets. Also, the particle shape was significantly influenced by Ce doping and a nanorod-like morphology was formed at 1.5 mol% Ce−doped V₂O₅. Power spectral density analysis indicated that surface roughness and fractal dimension of β−V₂O₅ increase by Ce doping. Optical measurement showed that the band gap narrowing (from 2.68 to 2.28 eV) occurred when the annealing temperature and dopant concentration increased. The variation of activation energy of the films was explained based on the small polaron hopping mechanism. The α−V₂O₅ film showed enhanced lithium−ion storage capacity compared to pristine β−V₂O₅ film and 1 mol% Ce−doped α−V₂O₅ thin film revealed the best ion storage capacity (Q_a=207.19 mC/cm², I_max=4.13 mA/cm² at scan rate of ν=20 mV/s).     

Evaluation of different oxidation methods for silicon for scanning capacitance microscopy

Different oxides, namely, native, thermal, and wet-chemical (H₂SO₄+H₂O₂ based) oxides on Si are evaluated in the context of scanning capacitance microscopy (SCM). The samples investigated consisted of uniformly doped Si substrates and p-type epitaxial doping-staircase structures with concentrations ranging from 5×10¹⁴ to 2×10¹⁹ cm⁻³. The bias for which the SCM signal (dC/dV) is maximised for the lowest doped region was used for comparing the different oxidation methods. It is shown that for a better evaluation of the surface oxide properties, it is essential to obtain dC/dV curves for a sufficiently large doping range. Best results in terms of low values of flat-band voltages (1 V), uniformity, and consistency across a large doping range were obtained for the wet-chemical oxide. For the native oxide case, the difference in the dC/dV peak bias values obtained at regions doped to 5×10¹⁴ to 10¹⁷ cm⁻³ was anomalously large and suggests appreciable distortion of the dC/dV curves. For the same oxidation procedure the full-width at half-maximum of the dC/dV curve obtained on the cleaved surface is typically 2 times larger than that on the planar (1 0 0) surface. It is most likely that interface states are responsible for the observed distortion.     

Fast and accurate method of lifetime estimation for HfSiON/SiO2 dielectric n-MOSFETs under positive bias temperature instability

This paper proposes a fast and accurate method to measure the constants a and n of the power law ∆ V_th = atⁿ for HfSiON/SiO₂ dielectric nMOSFETs under positive bias temperature instability (PBTI), where ∆ V_th is a shift of threshold voltage, and t is stress duration. The proposed method requires one nMOSFET only, uses a voltage ramp stress (VRS), measures ∆ V_th vs. t data during VRS, uses a regression method to fit the data for each VRS pulse to the power law to obtain a and n at each stress voltage V_g,str, then obtains five voltage-independent constants for the power law after fitting the curves of a and n vs. V_g,str to empirical models. The five voltage-independent constants agreed very well with those obtained using the constant voltage stress (CVS) method. After obtaining the voltage-independent constants, the lifetime t_L at an operating voltage V_op was estimated using the power law. The estimated t_L = 1.67 × 10⁸ s was quite close to t_L = 1.74 × 10⁸ s estimated using CVS, and to t_L = 1.72 × 10⁸ s estimated by extrapolating the ΔV_th vs. t curve measured at V_g,str = V_op = 1.2 V to ΔV_th = 200 mV. The time required for measurement was 900 s, compared to 30,000 s for the CVS method. These experimental results show that the proposed VRS-regression method is very useful for screening nMOSFETs under PBTI.     

High performance organic thin film transistors using chemically modified bottom contacts and dielectric surfaces

A compatible process of orthogonal self-assembled monolayers (SAMs) is applied to intentionally modify the bottom contacts and gate dielectric surfaces of organic thin film transistors (OTFTs). This efficient interface modification is first achieved by 4-fluorothiophenol (4-FTP) SAM to chemically treat the silver source–drain (S/D) contacts while the silicon oxide (SiO₂) dielectric interface is further primed by either hexamethyldisilazane (HMDS) or octyltrichlorosilane (OTS-C8). Results show that the field effect mobilities of the bottom-gate bottom-contact PTDPPTFT4 transistors were significantly improved to 0.91 cm² V⁻¹ s⁻¹.     

Fabrication of single crystal field-effect transistors with phenacene-type molecules and their excellent transistor characteristics

Single crystal field-effect transistors (FETs) using [6]phenacene and [7]phenacene show p-channel FET characteristics. Field-effect mobilities, μs, as high as 5.6 × 10^?1 cm² V^?1 s^?1 in a [6]phenacene single crystal FET with an SiO₂ gate dielectric and 2.3 cm² V^?1 s^?1 in a [7]phenacene single crystal FET were recorded. In these FETs, 7,7,8,8-tetracyanoquinodimethane (TCNQ) was inserted between the Au source/drain electrodes and the single crystal to reduce hole-injection barrier heights. The μ reached 3.2 cm² V^?1 s^?1 in the [7]phenacene single crystal FET with a Ta₂O₅ gate dielectric, and a low absolute threshold voltage |V_TH| (6.3 V) was observed. Insertion of 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F₄TCNQ) in the interface produced very a high μ value (4.7–6.7 cm² V^?1 s^?1) in the [7]phenacene single crystal FET, indicating that F₄TCNQ was better for interface modification than TCNQ. A single crystal electric double-layer FET provided μ as high as 3.8 × 10^?1 cm² V^?1 s^?1 and |V_TH| as low as 2.3 V. These results indicate that [6]phenacene and [7]phenacene are promising materials for future practical FET devices, and in addition we suggest that such devices might also provide a research tool to investigate a material’s potential as a superconductor and a possible new way to produce the superconducting state.     

Mechanism of mobility enhancement in Ge p-channel metal-oxide-semiconductor field-effect transistor due to introduction of Al atoms into SiO2/GeO2 gate stack

In this paper, we present comprehensive results on Al-postmetallization annealing (Al-PMA) effect for the SiO₂/GeO₂ gate stack on a Ge substrate, which were fabricated by a physical vapor deposition method. The effective oxide thickness of metal-oxide-semiconductor (MOS) capacitor (CAP) was ~7 nm, and the Al-PMA was performed at a temperature in the range of 300–400 °C. The flat band voltage (V_FB), the hysteresis (HT), the interfacial states density (D_it), and the border traps density (D_bt) for MOSCAPs were characterized by a capacitance–voltage method and a constant-temperature deep-level transient spectroscopy method. The MOSCAP without Al-PMA had an electrical dipole of ~−0.8 eV at a SiO₂/GeO₂ interface, which was disappeared after Al-PMA at 300 °C. The HT, D_it, and D_bt were decreased after Al-PMA at 300 °C and were maintained in the temperature range of 300–400 °C. On the other hand, the V_FB was monotonically shifted in the positive direction with an increase in PMA temperature, suggesting the generation of negatively charged atoms. Structural analyses for MOSCAPs without and with Al-PMA were performed by a time-of-flight secondary ion mass spectroscopy method and an X-ray photoelectron spectroscopy method. It was confirmed that Al atoms diffused from an Al electrode to a SiO₂ film and reacted with GeO₂. The dipole disappearance after Al-PMA at 300 °C is likely to be associated with the structural change at the SiO₂/GeO₂ interface. We also present the device performances of Al-gated p-channel MOS field-effect transistors (FET) with PMA treatments, which were fabricated using PtGe/Ge contacts as source/drain. The peak field-effect mobility (μ_h) of the p-MOSFET was reached a value of 468 cm²/Vs after Al-PMA at 325 °C. The μ_h enhancement was explained by a decrease in the total charge densities at/near the GeO₂/Ge interface.     

Frequency and voltage dependence of negative capacitance in Au/SiO2/n-GaAs structures

The frequency (f) and bias voltage (V) dependence of electrical and dielectric properties of Au/SiO₂/n-GaAs structures have been investigated in the frequency range of 10 kHz–3 MHz at room temperature by considering the presence of series resistance (R_s). The values of R_s, dielectric constant (ε′), dielectric loss (ε″) and dielectric loss tangent (tan δ) of these structures were obtained from capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements and these parameters were found to be strong functions of frequency and bias voltage. In the forward bias region, C–V plots show a negative capacitance (NC) behavior, hence ε′–V plots for each frequency value take negative values as well. Such negative values of C correspond to the maximum of the conductance (G/ω). The crosssection of the C–V plots appears as an abnormality when compared to the conventional behavior of ideal Schottky barrier diode (SBD), metal–insulator–semiconductor (MIS) and metal–oxide–semiconductor (MOS) structures. Such behavior of C and ε′ has been explained with the minority-carrier injection and relaxation theory. Experimental results show that the dielectric properties of these structures are quite sensitive to frequency and applied bias voltage especially at low frequencies because of continuous density distribution of interface states and their relaxation time.     

Solution-processed single-crystal perylene diimide transistors with high electron mobility

We have successfully demonstrated a single-crystal field-effect transistors (FETs) based on an asymmetric perylenetetracarboxylic diimide (a-PDI) compound with polystyrene (PS)/SiO₂ bilayer as gate dielectric. The single crystals are in-situ grown on substrate from simple solution evaporation method, thus may be suitable for large area electronics applications. The PS modified gate dielectric could minimize charge trapping by the hydroxyl groups of the SiO₂ surface. The resulting solution processed single crystals transistors are characterized in ambient air, and exhibited maximum electron mobility of ca. 1.2 cm² V⁻¹ s⁻¹ and high I_on:I_off > 10⁵.