A 1-V 3.5-mW CMOS switched-opamp quadrature IF circuitry for Bluetooth receivers

A 1-V switched-capacitor (SC) quadrature IF circuitry for Bluetooth receivers is demonstrated using switched-opamp technique. To achieve double power efficiency while maintaining low sensitivity to finite opamp gain effects for the SC IF circuitry, half-delay integrator-based filters and /spl Sigma//spl Delta/ modulator have been proposed. The proposed quadrature IF circuitry employs a seventh-order IF filter for channel selection and a third-order /spl Sigma//spl Delta/ modulator for analog-to-digital conversion. A noise-shaping extension technique is employed to enhance the resolution of the low-pass /spl Sigma//spl Delta/ modulator by 16 dB while operating at the same oversampling ratio and power consumption. At a 1-V supply, the quadrature IF circuitry achieves a measured IIP3 of -3 dBm at a nominal gain of 24 dB with a 48-dB variable gain control while consuming a total power dissipation of 3.5 mW.     

An elliptic continuous-time CMOS filter with on-chip automatic tuning

A voice-band continuous-time filter is described which was designed based on the technique of fully balanced networks and was fabrication in a 3.5-/spl mu/ CMOS technology. The filter implements a fifth-order elliptic low-pass transfer function with 0.05-dB passband ripple and 3.4 kHz cutoff frequency. A phase-locked loop control system fabricated on the same chip automatically references the frequency response of the filter to an external fixed clock frequency. The cutoff frequency was found to vary by less than 0.1% for an operating temperature range of 0-85/spl deg/C. The absolute value accuracy of the cutoff frequency was 0.5% (standard deviation). With /spl plusmn/5-V power supplies the measured dynamic range of the filter was approximately 100 dB.     

A practical micropower programmable bandpass filter for use in bionic ears

Subthreshold Gm-C filters offer the low power and wide tunable range required for use in fully implantable bionic ears. The major design challenge that must be met is increasing the linear range. A capacitive-attenuation technique is presented and refined to allow the construction of wide-linear-range bandpass filters with greater than 1 V/sub pp/ swings. For a 100-200 Hz fully differential filter with second-order roll off slopes and greater than 60 dB dynamic range, experimental results from a 1.5-/spl mu/m, 2.8-V BiCMOS chip yield only 0.23 /spl mu/W power consumption; for a 5-10 kHz filter with the same specifications the power only increased to 6.36 /spl mu/W. Fully differential filters with first-order slopes had a dynamic range of 66 dB and power consumptions of 0.12 and 3.36 /spl mu/W in the 100-200 Hz and 5-10 kHz cases, respectively. We show that our experimental results of noise and linear range are in good accord with theoretical estimates of these quantities.     

A 2.7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators

A low-voltage fourth-order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled inductors, thus providing bandwidth tuning with small passband ripple. Each resonator is built using on-chip spiral inductors and accumulation-mode pMOS capacitors to provide center frequency tuning. The filter has been implemented in HP 0.5-/spl mu/m CMOS process and occupies an area of 0.15 mm/sup 2/. It consumes 16 mA from a single 2.7-V supply at a center frequency of 1.84 GHz and a bandwidth of 80 MHz while providing a passband gain of 9 dB and more than 30 dB of image attenuation for an IF frequency of 100 MHz. The measured output 1-dB compression point and output noise power spectral densities are -16 dBm and -137 dBm/Hz, respectively. This results in a 1-dB compression dynamic range of 42 dB. The filter minimum power supply voltage for proper operation is 2 V. The chip experimental results are in good agreement with theoretical results.     

A 1.5-V 12-bit power-efficient continuous-time third-order /spl Sigma//spl Delta/ modulator

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall /spl Sigma//spl Delta/ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-/spl mu/m CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT /spl Sigma//spl Delta/ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 /spl mu/W from a single 1.5-V power supply.     

New high-efficiency 2.5 V/0.45 W RWDM class-D audio amplifier for portable consumer electronics

A single-chip of Class-D audio amplifier with high-power efficiency is presented. It includes a rectangular wave delta modulator (RWDM) and bridge-tied load output gate-drivers. The RWDM has a multiple inputs floating-gate hysteresis comparator and a feedback integrator formed by the external L-R low-pass filter. This monolithic Class-D audio amplifier with a maximum power efficiency of 92% has a flat frequency response with /spl plusmn/0.3 dB up to 20 kHz, and is capable of delivering up to 0.45 W of continuous average power into an 8-/spl Omega/ load at less than 0.5% total harmonic distortion plus noise from a 2.5-V power supply in the high fidelity range (20 Hz-20 kHz).     

A multipurpose micropower SC filter

A design strategy for micropower switched-capacitor filters is presented and illustrated with the design of a multipurpose second-order section. The filter, realized in a double-poly 6-/spl mu/m CMOS process, consumes 237 /spl mu/W if it is used as an equalizer (f/SUB c/=90 kHz, -V/SUB DD/=3 V) and only 72 /spl mu/W if it is used as a bandpass filter for 8 channels (f/SUB c/=192 kHz, V/SUB DD/=3 V). The dynamic range of the filter is over 60 dB and the total chip area is 3.5 mm/SUP 2/, including bonding pads.     

A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

A sixth-order 10.7-MHz bandpass switched-capacitor filter based on a double terminated ladder filter is presented. The filter uses a multipath operational transconductance amplifier (OTA) that presents both better accuracy and higher slew rate than previously reported Class-A OTA topologies. Design techniques based on charge cancellation and slower clocks are used to reduce the overall capacitance from 782 down to 219 unity capacitors. The filter's center frequency and bandwidth are 10.7 MHz and 400 kHz, respectively, and a passband ripple of 1 dB in the entire passband. The quality factor of the resonators used as filter terminations is around 32. The measured (filter + buffer) third-intermodulation (IM3) distortion is less than -40 dB for a two-tone input signal of +3-dBm power level each. The signal-to-noise ratio is roughly 58 dB while the IM3 is -45 dB; the power consumption for the standalone filter is 42 mW. The chip was fabricated in a 0.35-/spl mu/m CMOS process; filter's area is 0.84 mm/sup 2/.     

Micropower switched capacitor biquadratic cell

The implementation of the double correlated sampling noise reduction technique in conventional strays-insensitive switched capacitor biquad building blocks is described. The function is performed by an offset cancellation circuit which is incorporated into the structure without the use of any additional capacitor, only minor modifications in the switching topology, and one supplementary clock phase. Consequently, a significant reduction of the low-frequency (1/f) noise is made possible and the usual differential amplifiers may be replaced by simple inverting amplifiers operated in class AB, featuring high-speed, low-quiescent power dissipation and low noise. An experimental micropower SC biquadratic filter section designed for `leapfrog' or `follow-the-leader feedback' structures has been developed using high gain (>80 dB) CMOS push/pull inverting amplifiers together with a three-phase clocking sequence. The integrated circuit, implemented in a low-voltage Si-gate CMOS process, achieves excellent accuracy and less than 5 /spl mu/W power dissipation with a 32 kHz sampling rate and /spl plusmn/1.5 V supplies; dynamic range is 66 dB.     

A 28-MHz wideband switched-capacitor bandpass filter with transmission zeros for high attenuation

A 28-MHz wideband switched-capacitor (SC) bandpass filter employs an N-path technique and implements transmission zeros in the transfer function to achieve high attenuation. A modified SC biquadratic filter architecture is proposed to achieve high-speed operation. Implemented in a 0.35-/spl mu/m CMOS process, the bandpass filter operates at 28-MHz center frequency with a 3.84-MHz bandwidth and adjacent-channel attenuation of more than 35 dB. At 3-V supply, the filter measures a dynamic range of 37 dB at the 1% THD3 point while dissipating 19.6-mW per pole and occupying a chip area of 1.65 mm/sup 2/.     

Miniature and tunable filters using MEMS capacitors

Microelectromechanical system (MEMS) bridge capacitors have been used to design miniature and tunable bandpass filters at 18-22 GHz. Using coplanar waveguide transmission lines on a quartz substrate (/spl epsiv//sub r/ = 3.8, tan/spl delta/ = 0.0002), a miniature three-pole filter was developed with 8.6% bandwidth based on high-Q MEMS bridge capacitors. The miniature filter is approximately 3.5 times smaller than the standard filter with a midband insertion loss of 2.9 dB at 21.1 GHz. The MEMS bridges in this design can also be used as varactors to tune the passband. Such a tunable filter was made on a glass substrate (/spl epsiv//sub r/ = 4.6, tan/spl delta/ = 0.006). Over a tuning range of 14% from 18.6 to 21.4 GHz, the miniature tunable filter has a fractional bandwidth of 7.5 /spl plusmn/ 0.2% and a midband insertion loss of 3.85-4.15 dB. The IIP/sub 3/ of the miniature-tunable filter is measured at 32 dBm for the difference frequency of 50 kHz. The IIP/sub 3/ increases to >50 dBm for difference frequencies greater than 150 kHz. Simple mechanical simulation with a maximum dc and ac (ramp) tuning voltages of 50 V indicates that the filter can tune at a conservative rate of 150-300 MHz//spl mu/s.     

A low-distortion BiCMOS seventh-order Bessel filter operating at2.5 V supply

This paper presents the design of a seventh-order continuous-time Bessel filter using a new low-voltage and highly linear BiCMOS transconductor. A high-gain and parasitic-insensitive integrator is obtained by using an active capacitor scheme. The filter has been designed to operate at a 2.5 V supply with a nominal -3 dB cutoff frequency of 600 kHz. It has been fabricated in 1 μm, double-poly 6-GHz BiCMOS process. The inband group delay variation is less than 10 ns. The total harmonic distortion (THD) measured with a 100 kHz input signal is less than -49 dB for a 2 V_pp amplitude and the dynamic range is 77 dB. The filter can be frequency tuned over almost one decade with a gain variation less than 0.2 dB in the passband. A common-mode rejection ratio (CMRR) of 53 dB in the passband is observed, thanks to a careful common-mode control strategy     

A high precision monolithic super-beta operational amplifier

A single-chip (67/spl times/90 mil) integrated-circuit operational amplifier using thin-film resistors and super-gain transistors has been designed to achieve dc follower accuracies of 0.001 percent with 100-k/spl Omega/ source resistance. The circuit achieves gains of 140 dB using thermally balanced layout designs for both input and output stages, nulled drifts of 0.3 /spl mu/V//spl deg/C, and offset currents well under 1 nA. All other dc specifications including power-supply variation error (PSRR), common-mode gain error (CMRR), etc., are in the 1-10 ppm error range; and a procedure is given by which long-term drifts of less than 10 /spl mu/V/month can be assured. AC performance is comparable to general-purpose integrated-circuit operational amplifiers, i.e., f/SUB t/=300 kHz and slew rate of 1.2 V//spl mu/s at gain of ten. The circuit is externally compensated for unity gain with a single 390-pF capacitor and is fully input and output protected.     

AN ANTI-ALIASING FILTER FOR ∑△ ADC

An anti-aliasing filter for ADCs using a combination of active RC and analog FIR filters is presented in this letter. The first order active RC filter is set at 100kHz to minimize the die size and variations of linear phase and gain in 0-4kHz passband. The 2-tap FIR filter provides more than -53dB attenuation at 2MHz 4kHz frequency range. The proposed filter achieved more than -76dB attenuation at sampling frequency with 0.01 phase linearity and 0.02dB gain variation within 0-4kHz bandwidth. The active die area of the fully differential filter is 0.17mm2 in 0.5um CMOS technology. The experimental and simulation results have been obtained and the feasibility of the proposed method is shown.     

A programmable gain/loss circuit

A general-purpose gain/loss circuit is described. Its function is controlled by an 8-b digital word. It provides up to 256 0.1-dB steps in gain or loss. The circuit has two modes of incremental gain/loss steps (two sets of gain/loss values for bits in the control word). A ninth bit selects between gain and loss. The IC has three digital interfaces: serial, parallel clocked input, and parallel fixed input. The chip is fabricated in a 3-/spl mu/m CMOS n-well process. It requires a /spl plusmn/5-V power supply, and for maximum gain of 25.5 dB, the 0.1-dB large-signal bandwidth is 260 kHz.     

A 2-V/sub pp/ 80-200-MHz fourth-order continuous-time linear phase filter with automatic frequency tuning

A CMOS 80-200-MHz fourth-order continuous-time 0.05/spl deg/ equiripple linear phase filter with an automatic frequency tuning system is presented. An operational transconductance amplifier based on transistors operating in triode region is used and a circuit that combines common-mode feedback, common-mode feedforward, and adaptive bias is introduced. The chip was fabricated in a 0.35-/spl mu/m process; filter experimental results have shown a total harmonic distortion less than -44 dB for a 2-V/sub pp/ differential input with a single 2.3-V power supply. The group delay ripple is less than 4% for frequencies up to 1.5 f/sub c/. The frequency tuning error is below 5%.     

A 200-Ms/s 10-mW switched-capacitor filter in 0.5-μm CMOStechnology

Wideband amplifiers with low but precisely known dc gain allow the achievement of accurate infinite impulse response switched-capacitor (SC) filters operating at very high sampling frequencies. The low and precise opamp gain value is taken into account while sizing the capacitors (precise opamp gain (FOG) approach), so that no idle phase is required for amplitude error compensation and double-sampling technique can be implemented. In a 0.5-μm standard CMOS technology with 3.3-V power supply, an opamp is designed which exhibits a settling time of about 3 ns (for 0.1% settling accuracy) in a closed-loop configuration with input, feedback, and load capacitors of 0.5 pF, white the slew rate is 1 V/ns. The open-loop dc gain of the amplifier is set to the value of 80 (38 dB) by a gain-control closed loop, which guarantees an accuracy of ±2%. The proposed solution is validated by experimental results from a 200-Ms/s SC filter. From a single 3.3-V supply the filter consumes 10 mW (excluding clock generation) and exhibits a -40 dB total harmonic distortion for a 2-V_pp signal amplitude at 4 MHz, achieving a 62-dB dynamic range     

AN ANTI-ALIASING FILTER FOR ∑△ ADC

An anti-aliasing filter for ∑△ ADCs using a combination of active RC and analog FIR filters is presented in this letter. The first order active RC filter is set at 100kHz to minimize the die size and variations of linear phase and gain in 0-4kHz passband. The 2-tap FIR filter provides more than -53dB attenuation at 2MHz ±4kHz frequency range. The proposed filter achieved more than -76dB attenuation at sampling frequency with ±0.01° phase linearity and ±0.02dB gain variation within 0-4kHz bandwidth. The active die area of the fully differential filter is 0.17mm2 in 0.5μm CMOS technology. The experimental and simulation results have been obtained and the feasibility of the proposed method is shown.