外来物导致的塑封器件金属化层损伤机理分析

对塑封器件进行破坏性物理分析(DPA),发现有样品芯片表面存在金属化层损伤。对损伤部位进行背散射电子成像和能谱分析,确定损伤部位存在钢颗粒。结合塑封封装工艺环节进一步分析损伤形貌,结果表明钢颗粒来源于塑封模具破损或老化,在环氧固化过程中产生的应力导致钢颗粒压碎金属化层。分析了具有这类缺陷的塑封器件在高可靠应用领域中的危害性。这类缺陷形成机理不常见,研究结论对改进塑封器件生产工艺具有参考价值。     

塑封碳化硅肖特基二极管粘片工艺

粘片工艺是塑封碳化硅肖特基二极管封装中的关键工艺,实现了芯片背面金属与引线框架的物理连接与电连接,对器件的参数以及可靠性影响较大。我们发现器件生产中或者器件可靠性的多种失效模式都产生于粘片工艺。我们通过对焊料成分、拍锡头结构,工艺参数的优化等,使器件的品质大大提升。     

TSOP封装脱模中硅片碎裂失效的有限元分析

针对TSOP封装在塑封工艺中脱模时可能发生的芯片碎裂,利用有限元法模拟封装脱模过程阐明了芯片碎裂失效的机制.研究表明,模具内表面有机物形成的局部沾污可能阻碍芯片的顺利脱模,导致硅片内产生较大的局部应力并碎裂失效.通过模拟在不同的沾污面积、形状和位置下的封装脱模,确认了最可能导致失效的条件.芯片碎裂失效可以通过使用高弹性模量的塑封料或减小硅片尺寸得以改善.     

LQFP和eLQFP热机械可靠性的有限元分析

封装形式的差异性对产品可靠性具有重要影响。基于有限元法,对比分析了薄型四方扁平封装(LQFP)和载体外露薄型四方扁平封装(eLQFP)在室温和回流焊温度下的翘曲、芯片和粘片胶的应力水平以及各材料界面应力分布。研究表明,LQFP的翘曲比eLQFP的大,但芯片和粘片胶上的最大应力无明显差别;eLQFP在塑封材料与芯片有源面界面的应力水平比LQFP的大;eLQFP在芯片与粘片胶界面、粘片胶与芯片载体界面的剪切应力比LQFP的大,但eLQFP在芯片与粘片胶界面、粘片胶与芯片载体界面的剥离应力比LQFP的小;eLQFP在塑封材料与芯片载体镀银区界面的应力水平高于LQFP的应力水平,由于塑封材料与镀银芯片载体的结合强度弱,eLQFP更易发生界面分层。     

基于三维多芯片柔性封装的热应力分析

利用ANSYS软件针对一种三维多芯片柔性封装结构进行建模,通过有限元2D模型模拟该封装结构在热循环温度-40~125℃条件下产生的热应力/应变情况,讨论了芯片厚度、基板厚度、微凸点高度及模塑封材料对热应力/应变的影响。结果表明,三维多芯片柔性封装体的等效热应力发生在微凸点与芯片的连接处,其数值随着芯片厚度的减薄呈递减趋势;基板厚度也对热应变有一定的影响;增加微凸点高度有利于减小等效热应力;通过比较塑封材料得知,采用热膨胀系数较大,且杨氏模量与温度的依赖关系较强的模塑封材料进行塑封会产生较大应变。     

PMCM器件的失效根因分析

从塑封多芯片组装(PMCM)器件的电性能测试数据出发,根据器件的环境试验过程和MCM的材料结构、芯片性能,得出了某PMCM器件的失效性质与塑封封装材料、工艺相关的结论;同时讨论了一些PMCM失效分析问题。     

芯片涂胶的塑封器件超声检测工艺研究

基于超声检测原理,提出一套针对芯片涂胶的塑封器件超声检测工艺,防止将涂覆胶误判为分层缺陷,并通过理论分析与试验结果进行检测工艺适用性的验证,为利用超声检测手段检测和评价芯片涂胶的塑封器件内部界面分层提供判定准则。     

粘片胶固化对塑封集成电路可靠性的影响

当具有诸如分层等可靠性缺陷的微电子器件焊接在线路板上,通过回流焊时会产生塑封体裂缝、塑封体鼓胀等重要缺陷。粘片胶未充分固化、水汽未完全排除、环境湿气较大易吸湿等原因导致水汽沿着塑封体与引线引脚向内部扩散。表现为各结合面的分层,粘片胶与芯片之间、塑封体与引线之间、塑封体与芯片之间,各种分层在快速加热产生的热应力下水汽快速膨胀,从而引起器件可靠性隐患。     

QFN封装分层失效与湿-热仿真分析

采用湿度敏感度评价试验及湿-热仿真方法,分析了温湿度对于QFN封装分层失效的影响.通过C-SAM和SEM等观察发现,QFN存在多种分层形式,分层大多发生在封装内部材料的界面上,包括封装塑封材料和芯片之间的界面、塑封材料和框架之间的界面等.此外,在封装断面研磨的SEM图像上发现芯片粘结剂内部有空洞出现.利用有限元数值模拟的方法,对QFN封装的内部湿气扩散、回流过程中的热应力分布等进行了模拟,分析QFN分层失效的形成原因.结果表明,由于塑封器件材料、芯片、框架间CTE失配,器件在高温状态湿气扩散形成高气压条件下易产生分层.最后提出了改善QFN分层失效的措施.     

薄型塑封芯片钝化层损伤的失效分析与改进

针对某薄型塑封产品试制中出现的开、短路问题,通过表面研磨、截面剖切、能谱分析等失效分析手段,确认了塑封料内无机填料颗粒损伤芯片钝化层的缺陷模式。从塑封材料的使用管控、塑封工艺参数改进及塑封料选型等角度对钝化层损伤问题进行了分析与验证。结果表明,合模压力的施加过程是影响芯片钝化层损伤的关键因素,采用215 k N的1段式合模压力设定可有效改善该缺陷,对薄型封装的塑封参数设定及材料选型提供了参考建议。     

TO系列塑料封装离层探讨

文章研究了TO系列塑料封装功率器件产品产生离层的原因。同时,研究了TO系列塑料封装功率器件产品在上芯、压焊、塑封工序中的原材料、塑封模具、工艺参数等对离层的影响,并通过SAT图片,对影响离层的因素进行了论证,提出了如何预防或减轻TO系列塑料封装产品离层的产生。实验结果表明:塑封工艺参数的合理选择、塑封模具结构的合理选用、塑封料优选对TO系列塑料封装离层有较好的改善作用,并且在塑封生产线上易于实现。文章在这些方面做了相关尝试,取得了较好的效果。     

塑料成型模具设计多媒体与动态演示系统的研制

在对塑料成型工艺、成型设备、成型所用模具的特点进行系统分析的基础上，研制开发了旨在对初入模具行业的技术人员以模具设计知识为指导的塑料成型模具设计多媒体与动态演示系统。该系统利用多媒体计算机的文本、图像、动画、视频和音频的综合处理能力和其交互式特点，借助VB、AUTOCAD、3DS MAX等高级软件，为塑料成型模具设计学习人员创造了一个图文并茂、生动逼真的学习环境。     

Study on the different procedures for debleeding of plastic dip

Inevitable wear on encapsulation molds and small variances in the leadframes cause a small amount of the molding compound or resin to leak out. The leakage results in either excess flash around the body of the plastic package or a thin transparent film on the leadframe and leads, which subsequently affect the solder-dipping that protects the leadframe from corrosion. Thus, effective debleeding procedure must be performed before the solder-dipping process. In this study, nine different flow procedures are designed. The results of the study show that the resin bleed can be more effectively removed by a debleeding procedure carried out immediately after molding rather than post-cure. The wet blasting process used for the debleeding purpose is also found not suitable as it causes side effects to the package surface and leadframe.     

Improving the deflection of wire bonds in stacked chip scale package (CSP)

The deformation of gold wire bonds during transfer molding of stacked chip scale package (CSP) can seriously cause wire crossover and shorting. The major challenges of the stacked CSP development are to reduce the wire sweep (deflection), and make the sufficient space clearance between the wires of first to second die. In this paper, M shape wire looping program is developed to increase the wire sweep resistance in the stacked CSP. Both linear elastic finite element analysis and experiments based on wire bonding and molding process evaluation are conducted. It is found that M shape looping program is much better than conventional normal wire shape in terms of wire sweep resistance after molding. X-ray and scanning electronic microscopy (SEM) can verify the improvement of wire deflection after chemical de-capsulation. It is believed that using M shape looping program can efficiently overcome the risk of wire shorting and improve the yield of wire bonds in high volume production of stacked CSP.     

Study on the fluid/structure interaction at different inlet pressures in molded packaging

This paper presents the computational study of fluid/structure interaction (FSI) analysis in the molding process using the Mesh-based parallel Code Coupling Interface (MpCCI) method with finite volume coding (FLUENT 6.3) and finite element coding (ABAQUS 6.9). The FSI analysis is implemented on the molded package during the encapsulation process with different inlet pressures. Real-time flow visualization, deformation and stress of the silicon die during the encapsulation process are presented in this paper. A fluctuation phenomenon of the silicon die is found in the encapsulation process when the inlet pressure increases. The maximum deformation during the process is determined at different locations on the silicon die, calculated during the final stage of the filling process. The deformation and stress of the die is exponentially increased with increasing inlet pressure. The maximum stress on the solder bump is concentrated near to the inlet gate. Thus, the present FSI analysis approach is expected to be a guideline or reference and provides better understanding of the encapsulation process for package design in the microelectronic industry.     

超薄圆片划片工艺探讨

集成电路小型化正在推动圆片向更薄的方向发展,超薄圆片的划片技术作为集成电路封装小型化的关键基础工艺技术,显得越来越重要,它直接影响产品质量和寿命。本文从超薄片划片时常见的崩裂问题出发,分析了崩裂原因,简单介绍了目前超薄圆片切割普遍采用的STEP切割工艺。另外,针对崩裂原因,还从组成划片刀的3个要素入手分析了减少崩裂的选刀方法。     

等离子增强化学气相沉积法低温生长SiO_x薄膜的针孔缺陷修复

针对等离子增强化学气相沉积(PECVD)方法低温(60℃)生长氧化硅(SiOx)薄膜中存在的针孔缺陷,在SiOx薄膜上采取原子层沉积(ALD)方法生长氧化铝(AlOy),利用ALD方法材料保形生长的特点,进行SiOx薄膜的针孔缺陷修复工艺技术研究。实验结果表明:在SiOx薄膜上利用ALD方法保形生长氧化铝,可以明显降低AlOy/SiOx复合薄膜的水汽渗透率,提高薄膜封装性能。通过实验数据分析认为:复合薄膜的水汽阻隔能力是由于ALD方法及PECVD方法两种薄膜生长方法的综合作用,这种综合作用很有可能来自PECVD方法薄膜中针孔缺陷的修复,而ALD方法正是完成修复过程的技术手段。另外,ALD方法的工艺参数与针孔缺陷的修复效果相关,ALD生长周期时间延长,有利于提高针孔缺陷的修复效果,从而降低了复合薄膜的水汽渗透率。     

Comparing the Impacts of the Capillary and the Molded Underfill Process on the Reliability of the Flip-Chip BGA

In the assembly process for the conventional capillary underfill (CUF) flip-chip ball grid array (FCBGA) packaging the underfill dispensing creates bottleneck. The material property of the underfill, the dispensing pattern and the curing profile all have a significant impact on the flip-chip packaging reliability. Due to the demand for high performance in the CPU, graphics and communication market, the large die size with more integrated functions using the low-K chip must meet the reliability criteria and the high thermal dissipation. In addition, the coplanarity of the flip-chip package has become a major challenge for large die packaging. This work investigates the impact of the CUF and the novel molded underfill (MUF) processes on solder bumps, low-K chip and solder ball stress, packaging coplanarity and reliability. Compared to the conventional CUF FCBGA, the proposed MUF FCBGA packaging provides superior solder bump protection, packaging coplanarity and reliability. This strong solder bump protection and high packaging reliability is due to the low coefficient of thermal expansion and high modulus of the molding compound. According to the simulation results, the maximum stress of the solder bumps, chip and packaging coplanarity of the MUF FCBGA shows a remarkable improvement over the CUF FCBGA, by 58.3%, 8.4%, and 41.8% (66 $mu {rm m}$), respectively. The results of the present study indicates that the MUF packaging is adequate for large die sizes and large packaging sizes, especially for the low-K chip and all kinds of solder bump compositions such as eutectic tin-lead, high lead, and lead free bumps.      

High reliability, high density, low cost packaging systems formatrix systems for matrix BGA and CSP by vacuum printing encapsulationsystems (VPES)

Ball grid array (BGA) and chip scale package (CSP) packaging markets are increasing. In general, transfer molding systems are used for these packaging processes. However, transfer molding systems are difficult to change the model for high expensive metal die. This paper describes a unique vacuum printing encapsulation system (VPES) we developed to solve such problems with lower cost than transfer molding. We used matrix type BGA and CSP for this test. Matrix type BGA and CSP make it easy to use printing technology for die-bonding, packaging, marking, and flux coating process. The total cost of this packaging is cheaper than the transfer molding process. We developed very low warpage and high reliability epoxy resin for matrix BGA and CSP. We succeeded in achieving high reliability and low cost packaging systems with this technology