MIPS64^TM架构为RMI公司XLP^TM处理器带来超高性能

MIPS科技公司宣布，其高性能MIPS64^TM架构已为RMI公司新款XLP^TM处理器采用。RMI公司推出的XLP处理器是一款以MIPS64^TM指令集为基础的多核处理器，拥有目前业界最高的每瓦性能。RMI是为通信和各种媒体应用提供高性能处理器的领导厂商，其XLP处理器采用MIPS64兼容超标量体系结构及具备无序（out—of-order）处理能力的多线程处理器内核。     

基于多核处理器的面向时延敏感服务的云基础架构

给出了一种采用MIPS指令集的64核处理器Tilepro64作为硬件平台,实现了可以达到亚毫秒级处理时延的云计算基础架构作为基带信号处理和关键应用的支撑平台,实现了在多核处理器上的运算并行优化、动态平衡负载、时延保证、服务注册机制的设计和实现。相对于x86通用处理器,该云计算平台功耗低、密度高、能效比高;相对于专用硬件,开发成本低、周期短。     

一种DSP和通用CPU一体化的处理器架构及其4核实现

提出了一种DSP和通用CPU一体化的处理器架构,并完成了一款基于该架构的同构4核处理器设计和流片验证.该处理器基于VLIW结构,支持自主定义的DSP指令系统,兼容现有通用的MIPS 4KC处理器指令集,支持最大8个指令通道的并行发射.处理器在不改变CPU的指令编码以及执行顺序的前提下,实现了芯片结构上的DSP和CPU执行处理的一体化,适合在统一的平台上同时完成宽带通信和多媒体的信号和协议处理的嵌入式应用开发.处理器内核通过自主定义的DSP指令字中前后并行标识位和一条专用的前导paralink指令实现了DSP与CPU指令的并行发射.在4核处理器的同构架构上,采用了全局读局部写的多核间片上数据存储策略,在控制硬件开销的基础上实现片上数据的共享.仿真和流片验证结果表明,所提出的DSP和CPU一体化处理器架构可行,在宽带通信和多媒体等嵌入式应用上具有优势.     

Cavium Networks公司推出新型OCTEON^TMⅡ处理器

MIPS科技公司（MIPS Technologies,Inc）宣布,Cavium Networks公司推出的新型OCTEON^TMⅡ因特网应用处理器（IAP）中采用了MIPS科技的高性能MIPS64 架构。OCTEONⅡ系列采用多达32个MIPS64内核．是Cavium基于MIPS64架构的可扩展多核OCTEON处理器成功产品线的最新产品,并创下了在一个芯片中采用MIPS64处理器内核数目的新纪录。     

高性能MIPS64架构推动Cavium Networks公司新型OCTEONⅡ处理器

MIPS科技公司宣布,Cevium Networks公司正式推出的新型OCTEONⅡ因特网应用处理器（IAP）中。采用了MIPS科技的高性能MIPS64架构。OCTEONⅡ系列采用多达32个MIPS64内核,是Cavium基于MIPS64架构的可扩展多核OCTEON处理器成功产品线的最新产品,并创下了在一个芯片中采用MIPS64处理器内核数目的新纪录。     

多核CPU系统结构分析与建模

多核已经成为通用处理器设计技术的最重要发展方向。由于多核芯片内具有多个处理蠡核，芯片的缓存结构、线程调度等与传统CPU有很大的区别，本文探讨了多核芯片的基本结构特征，并基于指令集级系统仿真工具Simics建立了多核CPU模拟环境用于进行分析。     

一种多核处理系统通信机制的仿真模型

设计了一种多核处理系统通信机制的仿真模型,采用面向对象的设计模式对多核处理系统的互联节点、处理单元进行抽象,可快速搭建多核处理系统的硬件架构,支持不同互联结构和数据传输方法的仿真验证.测试结果表明,提出的仿真模型可对多核处理器中互联节点的通信能力进行精确仿真,可满足设计人员对多核处理系统硬件体系架构的性能评估需求,大幅缩短设计时间。     

嵌入式系统

MIPS64架构为新型多核处理器带来强大功能 MIPS宣布．Cavium Networks最新推出的OCTEON ⅡCN68XX／67XX处理器系列采用了其MIPS64架构,集成了8至32个增强的MIPS64内核,在单个芯片中可提供高达48GHz的64位计算能力,可为大型企业、移动互联网基础设施、安全数据中心和云计算应用带来高性能和应用加速。     

嵌入式Flash CISC/DSP微处理器的研究与实现

本文研究一种新的既具有微控制器功能,又有增强DSP功能的高性能微处理器的实现架构.在统一的增强CISC指令集下,我们将基于哈佛和寄存器-寄存器结构的微处理器模块和单周期乘法/累加器、桶形移位寄存器、无开销循环及跳转硬件支持模块、硬件地址产生器等DSP功能模块以及嵌入式Flash Memory和指令队列缓冲器有机的集成起来,在统一架构下通过单核实现CISC/DSP微处理器,有效地提高了处理器的性能.该微处理器采用0.35μm CMOS工艺实现,芯片面积为25mm².在80M工作频率下,动态功耗为425mW,峰值数据处理能力可达80MIPS.该处理器核可满足片上系统(SOC)对高性能处理器的需求.     

高性能嵌入式计算几个关键问题及其研究进展

随着多核处理器芯片在嵌入式应用领域越来越受到关注,提高应用程序开发产能同时获得并行性能收益是多核大众化并行计算研究的核心目标。着重综述了嵌入式应用领域面临的三个关键问题。首先,对当前的高性能嵌入式计算与超级计算做了比较,并对嵌入式应用领域做了分类总结。其次,对当前的适用于嵌入式的片上多核处理器架构做了研究。最后,综述了多核并行编程的方式的研究现状,并总结了嵌入式多核并行未来的研究问题。     

多核处理器核间高速通讯架构的研究

多核处理器使得并行系统的结构日益复杂,已经成为处理器的主流,并发展成为各种通信与媒体应用的主流处理平台.通讯结构是多核系统中的核心技术之一,核间通信的效率是影响多核处理器性能的重要指标.目前有三种主要的通讯架构:总线系统结构、交叉开关网络和片上网络.总线结构设计相对方便、硬件消耗较少、成本较低,交叉开关是适用于构建大容...     

多核处理器功耗优化与评估技术发展综述

多核处理器已经成为当前处理器设计的主流,其并行处理能力显著提高了处理器的性能,同时,多核处理器本身的高度集成度也使其功耗显著上升,从而在一定程度上限制了多核处理器的发展。本文描述了低功耗设计的基本理论、常用的低功耗设计技术和多核处理器中的功耗评估技术,并分析和总结了低功耗多核处理器研究的最新进展,可为多核处理器的设计提供有益的参考。     

通用处理器多核流水线自适应同步方法

在通用处理器上进行信号处理是软件无线电发展的方向之一,现有的共享存储并行编程（OpenMP）和直接线程并行法难以对信号处理进行并行加速。针对串行算法的并行化问题,引入多核流水线方法,对传统串行方法和多核流水线的实时性进行了分析对比。针对多核流水线的同步问题,研究了一种分布式的自适应线程同步方法。结合信号处理实例,对串行方法和多核流水线的实时性进行测试,结果表明多核流水线的吞吐率是串行方法的2.1倍,处理能力大大提高。     

A Novel Reconfigurable Processor Using Dynamically Partitioned SIMD for Multimedia Applications

In this paper, we propose a novel reconfigurable processor using dynamically partitioned single‐instruction multiple‐data (DP‐SIMD) which is able to process multimedia data. The SIMD processor and parallel SIMD (P‐SIMD) processor, which is composed of a number of SIMD processors, are usually used these days. But these processors are inefficient because all processing units (PUs) should process the same operations all the time. Moreover, the PUs can process different operations only when every SIMD group operation is predefined. We propose a processor control method which can partition parallel processors into multiple SIMD‐based processors dynamically to enhance efficiency. For performance evaluation of the proposed method, we carried out the inverse transform, inverse quantization, and motion compensation operations of H.264 using processors based on SIMD, P‐SIMD, and DP‐SIMD. Experimental results show that the DP‐SIMD control method is more efficient than SIMD and P‐SIMD control methods by about 15% and 14%, respectively.     

一种异构多核处理器的并行流存储结构

 异构多核处理器可结合多种处理器体系结构的优势,既保留传统通用体系结构的灵活性,又拥有大量计算资源,可提供更高的峰值计算性能.YHFT64-3异构多核处理器中浮点处理部件18套,峰值计算能力强大,设计与之相匹配的存储系统是一项重大挑战.针对YHFT64-3处理器,本文提出了一种并行流层次存储结构,深入阐述了如何体现应用特点、支持并行数据流处理的存储系统的设计思想和方法,从多个层次实现对并行数据流的挖掘或捕获.测试结果表明,这种存储结构体现了应用特点,能够较好地发挥YHFT64-3处理器的性能,同频情况下(500MHz),YHFT64-3比YHFT64-2性能高2—3个数量级,与1.6GHz的Itanium2性能相当,但代价更低.     

Parallelization Strategies and Performance Analysis of Media Mining Applications on Multi-Core Processors

This paper studies how to parallelize the emerging media mining workloads on existing small-scale multi-core processors and future large-scale platforms. Media mining is an emerging technology to extract meaningful knowledge from large amounts of multimedia data, aiming at helping end users search, browse, and manage multimedia data. Many of the media mining applications are very complicated and require a huge amount of computing power. The advent of multi-core architectures provides the acceleration opportunity for media mining. However, to efficiently utilize the multi-core processors, we must effectively execute many threads at the same time. In this paper, we present how to explore the multi-core processors to speed up the computation-intensive media mining applications. We first parallelize two media mining applications by extracting the coarse-grained parallelism and evaluate their parallel speedups on a small-scale multi-core system. Our experiment shows that the coarse-grained parallelization achieves good scaling performance, but not perfect. When examining the memory requirements, we find that these coarse-grained parallelized workloads expose high memory demand. Their working set sizes increase almost linearly with the degree of parallelism, and the instantaneous memory bandwidth usage prevents them from perfect scalability on the 8-core machine. To avoid the memory bandwidth bottleneck, we turn to exploit the fine-grained parallelism and evaluate the parallel performance on the 8-core machine and a simulated 64-core processor. Experimental data show that the fine-grained parallelization demonstrates much lower memory requirements than the coarse-grained one, but exhibits significant read-write data sharing behavior. Therefore, the expensive inter-thread communication limits the parallel speedup on the 8-core machine, while excellent speedup is observed on the large-scale processor as fast core-to-core communication is provided via a shared cache. Our study suggests that (1) extracting the coarse-grained parallelism scales well on small-scale platforms, but poorly on large-scale system; (2) exploiting the fine-grained parallelism is suitable to realize the power of large-scale platforms; (3) future many-core chips can provide shared cache and sufficient on-chip interconnect bandwidth to enable efficient inter-core communication for applications with significant amounts of shared data. In short, this work demonstrates proper parallelization techniques are critical to the performance of multi-core processors. We also demonstrate that one of the important factors in parallelization is the performance analysis. The parallelization principles, practice, and performance analysis methodology presented in this paper are also useful for everyone to exploit the thread-level parallelism in their applications.

CEMulti-core Architecture for Optimization of Energy over Heterogeneous Environment with High Performance Smart Sensor Devices

Nowadays, it is unusual for an electronic system to be without sensors, thus sensing plays an important part in everyday life. To this, the field of image processing is an added advantage as it stores image data and makes it readily available for parallel processing. The wireless sensor nodes over heterogeneous networks exhibit radio communication always with highest energy consumption. Multicore processors are more suitable for real time applications compared to traditional modern microcontrollers of sensor nodes in terms of improvement in their energy consumption rate. To significantly reduce the energy consumption, the usage of off-the-shelf low power microcontroller with appropriate processing core has to be considered. The proposed CEMulti-core architecture incorporated with the MIPS single core processor and multicore processor is simulated and the experimental results are compared and analyzed for their speedup, clock cycles and the time required for execution. Thus enabling the sensor node over heterogeneous networks to process large sized images with increase in energy efficiency.     

基于多核MIPS64芯片的综合安全网关设计与实现

针对当前安全设备在面对日益复杂的多形态网络行为和攻击应用上存在的低效率和低功能,提出一种面向下一代网络的高性能、分层次、并行处理的多功能综合安全网关体系结构。该体系结构以多核MIPS64安全处理芯片为基本核心模块,采用X86作为资源调度管理,以MIPS64cavium芯片内嵌的针对TCP数据包深度检查和模式识别的硬件完成网络数据流的高速检测,以PCI express X16总线实现线速处理网络数据流量,以双通道DDR2和Ultra320SCSI完成海量数据流的内部处理和存储。实际测试表明新型安全网关具有极好的效果。     

多核DSP编程技术研究

数字信号处理器（DSP）是对数字信号进行高速实时处理的专用处理器。当前,基于单核结构的嵌入式处理器越来越不能满足日益增长的数据处理应用方面的要求,单纯的增加单个处理器的处理速度更会带来难以接受的能耗。多核嵌入式结构已成为解决这一问题的有效途径,也使整个系统只用DSP搭建成为可能,但同时也为如何开发充分利用多核结构的应用...