Analysis for the reliability of the intrinsic base ion implantation of a 3 Ghz IL bipolar process from the measure of integrated resistances: From the results, setting of rules for an expert system

To avoid a shift of the process parameters during various steps of wafer manufacturing, it is important to monitor them, daily and quicker as possible. At parametric facility, testing devices of the wafer are electrically characterized to make a critical checking of the process. For the case of a 3 GHz bipolar technology, we have defined rules for the monitoring of the dose and of the energy of a critical ion implantation and for the control of the thickness variation of a thin LOCOS. The analysis is based on the measurement of three types of integrated resistances. Also, to write and to validate the rules, we did a process analysis with a tool called Failure Modes and Effects Analysis (FMEA), which allowed us to predict the effects of these parameters on the electrical characteristics. Following this study, we realise a Design Of Experiment (DOE). From the results, and based on a simple process monitoring method, specific rules are written to be inserted in a technological expert system for the failure of the intrinsic base ion implantation during the fabrication process.     

An extraction method to determine interconnect parasitic parameters

Interconnect parasitic parameters in integrated circuits have significant impact on circuit speed. An accurate monitoring of these parameters can help to improve interconnect performance during process development, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are destructive (such as SEM measurement) or can determine only partial parasitic parameters (such as large capacitor measurement). In this paper, we present a new method for extracting interconnect parasitic parameters, which can simultaneously determine the interlayer and intralayer capacitances, line resistance, and effective line width. The method is based on two test patterns of the same structure with different dimensions. The structure consumes less wafer area than existing methods. The method shows good agreement with SEM measurement of dielectric thickness in both nonglobal planarized and chemical-mechanical polished processes, and gives accurate prediction of the process spread of a ring oscillator speed over a wafer     

Critical issues of wafer level chip scale package (WLCSP) withemphasis on cost analysis and solder joint reliability

Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the, important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layer on the solder joint reliability of WLCSP on printed circuit board (PCB) through the creep responses such as the deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped with pad-redistribution WLCSPs are considered in this study     

扇出型晶圆级封装中圆片翘曲研究

在扇出型晶圆级封装工艺中,由于芯片材料与塑封料之间的热膨胀系数差异,晶圆塑封过程中必然会形成一定的翘曲.如何准确预测晶圆的翘曲并对翘曲进行控制是扇出型晶圆级封装技术面临的挑战之一.在讨论圆片翘曲问题时引入双层圆形板弯曲理论与复合材料等效方法,提出一套扇出型晶圆级封装圆片翘曲理论模型,并通过有限元仿真与试验测试验证了该翘...     

Extraction of wafer-level defect density distributions to improveyield prediction

Defect density distributions play an important role in process control and yield prediction. To improve yield prediction we present a methodology to extract wafer-level defect density distributions better reflecting such chip-to-chip defect density variations that occur in reality. For that, imaginary wafermaps are generated for a variety of different chip areas to calculate a yield-to-area dependency. Based on these calculations a micro density distribution (MDD) will be determined for each wafer that reflects the degree of defect clustering. The single MDD's per wafer may be summarized to also provide a total defect density distribution per lot or any other sample size. Furthermore, the area needed for defect inspection may be reduced to just a fraction of each wafer which reduces time and costs of data collection and analysis     

Sea of Leads Compliant I/O Interconnect Process Integration for the Ultimate Enabling of Chips With Low-$hbox k$Interlayer Dielectrics

Sea of leads (SoL) process integration for the series of steps required to transform a fully intact die at the wafer level to a die that is assembled onto a board is described. The primary goal is to address the issues involved in reconciling the fabrication and assembly requirements of compliant leads, such as SoL, with those of standard semiconductor processes and chip assembly techniques. The effort is motivated in-part by the potential failure of the low-$hbox k$interlayer dielectric in microprocessors as a result of high mechanical stresses due to the coefficient of thermal expansion (CTE) mismatch between the chip and the board. SoL, and other compliant interconnections, mitigate this problem by mechanically decoupling the chip and the board. While compliant leads offer advantages over C4 technology, there is much to consider during the series of steps needed to transform the fully intact dice at the wafer level to dice that are assembled onto the board. The use of an encapsulation film over the leads during wafer sawing is shown to be necessary for slippery leads and other free-standing compliant leads. The use of a suitable flux when the leads are finished with a nickel–oxide nonwettable layer is essential for a successful wafer-level solder reflow. Successful die assembly using thermocompression bonding is demonstrated using two different SoL dice with correspondingly different substrates. The resistance of a chain of 30 cascaded leads is 2.7$Omega$.     

Critical Dimension Uniformity Via Real-Time Photoresist Thickness Control

In this paper, we present the experimental results on wafer-to-wafer and within-wafer critical dimension (CD) control. It is known that photoresist thickness affects CD. In this paper, we control photoresist thickness to control CD. As opposed to run-to-run control where information from the previous wafer or batch is used for control of the current wafer or batch, the approach here is real time and makes use of the current wafer information for control of the current wafer CD. The experiments demonstrate that such an approach can reduce CD nonuniformity wafer to wafer and within wafer.     

Modeling the effect of barrier thickness and low-k dielectric on circuit reliability using 3D model

The continuous scaling down of the device size and escalating circuit speed drives the requirement for EM-resistant Cu interconnect with diffusion barrier and the low-k dielectric. The study of barrier layer thickness and low-k dielectric effect in a complete 3D circuit is necessary as the actual physical implementation of an integrated circuit in a wafer is indeed 3D in nature. This paper investigates the effect of barrier layer thickness and low-k dielectric on the circuit reliability of a complete 3D circuit model. It was found that the maximum atomic flux divergence (AFD) value increases with decreasing barrier layer thickness, which implied a shorter EM lifetime with thinner barrier. Low-k dielectric will give a higher maximum AFD due to higher stress gradient, and thus a shorter EM lifetime.     

Statistical model for spatial correlation in thin film depositionand reactive growth

This paper presents a statistical method for the estimation of thickness variations present across a wafer lot in low pressure chemical vapor deposition (LPCVD) and reactively grown films. The method uses experimental thickness data to construct a unified Karhunen-Loeve expansion based model that captures both deterministic and random thickness variations. The model uses a set of quadratic interpolation functions fitted to mean spatial data to approximate the deterministic nonuniformity and a few normalized random variables to represent run-to-run fluctuations. This model therefore retains the spatial correlations present between different deposition and growth steps in a process necessary for the estimation of parametric yield and permits the calculation of distribution functions over different lot populations (wafer, die, point, etc.). Models for spatial correlations in LPCVD oxide, nitride, polycrystalline silicon, and thermal oxide growth were constructed from a data set of 35000 thickness measurements recorded from a total of 40, 25-wafer runs. In each case, the model gives good predictions (90-95% confidence) with just one or two random variables     

Pseudomorphic HEMT manufacturing technology for multifunctionalKa-band MMIC applications

We have demonstrated very good performance, high yield Ka-band multifunctional MMIC results using our recently developed 0.25-μm gate length pseudomorphic HEMT (PHEMT) manufacturing technology. Four types of MMIC transceiver components-low noise amplifiers, power amplifiers, mixers, and voltage controlled oscillators-were processed on the same PHEMT wafer, and all were fabricated using a common gate recess process. High performance and high producibility for all four MMIC components was achieved through the optimization of the device epitaxial structure, a process with wide margins for critical process steps and circuit designs that allow for anticipated process variations, resulting in significant performance margins. We obtained excellent results for the Ka-band power amplifier: greater than 26 dBm output power at center frequency with 4.0% standard deviation over the 3-in. wafer, 2-GHz bandwidth, greater than 20 pet-cent power-added efficiency, over 8 dB associated gain, and over 10 dB linear gain. The best performance for the Ka-band LNA was over 17 dB gain and 3.5 dB noise figure at Ka-band. In this paper, we report our device, process, and circuit approach to achieve the state-of-the-art performance and producibility of our MMIC chips     

Wafer-Level Integration Technique of Surface Mount Devices on a Si-Wafer With Vibration Energy and Gravity Force

This paper reports about a novel wafer-level integration technique of discrete surface mount devices (SMDs). It enables wafer-level mounting of plural kinds of SMDs on a silicon (Si)-wafer using vibration and gravity force. Deep holes with 400-m depth are formed on the surface of a Si-wafer by deep reactive ion etching process after general integrated circuit process for positioning of SMDs. A non-conductive adhesive (CYTOP) are coated on the deep holes and it is used to fix the aligned SMDs. SMDs are distributed on a Si-wafer mounted on vibration generator, and then a vibration is applied. The SMDs migrate due to the reduced friction between the wafer surface, and they drop into the holes on the silicon wafer. The size of the holes has an appropriate clearance to the size of SMD. In order to align two or more kinds of SMDs, sizes of the deep holes on a Si-wafer are adjusted to the size of each SMD. SMDs with the largest size are dropped into the holes first, and then the secondary large SMDs are dropped into the holes with the corresponding size. SMDs are finally connected electrically by wire bonding at the final step. In the experiment, two different sizes of SMD were successfully mounted into all the holes on a Si-wafer automatically. This technology will be a wafer-level process technology which is very promising to integrate two or more kinds of discrete elements.     

超薄型圆片级芯片尺寸封装技术

ShellCase公司的圆片级封装技术工艺,采用商用半导体圆片加工设备,把芯片进行封装并包封到分离的腔体中后仍为圆片形式。圆片级芯片尺寸封装(WL-CSP)工艺是在固态芯片尺寸玻璃外壳中装入芯片。玻璃包封防止了硅片的外露,并确保了良好的机械性能及环境保护功能。凸点下面专用的聚合物顺从层提供了板级可靠性。把凸点置于单个接触焊盘上,并进行回流焊,圆片分离形成封装器件成品。WL-CSP封装完全符合JEDEC和SMT标准。这样的芯片规模封装(CSP),其测量厚度为300μm-700μm,这是各种尺寸敏感型电子产品使用的关键因素。     

Ultrathin wafer level chip size package

The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant polymer layer under the bumps provides on board reliability. Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices. This WLCSP fully complies with Joint Electron Device Engineering Council (JEDEC) and surface mount technology (SMT) standards. Such chip scale packages (CSP's) measure 300-700 μm in thickness, a crucial factor for use in various size sensitive electronic products     

Design optimization of one-turn helix: a novel compliant off-chip interconnect

As the rapid advances in integrated circuit (IC) design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great potential for next-generation packaging. One-turn helix (OTH) interconnect, a compliant chip-to-next level substrate or off-chip interconnect, is proposed in this work, and this interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The interconnect has high mechanical compliance in the three orthogonal directions, and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of the helix interconnect is similar to the standard IC fabrication, and the wafer-level packaging makes it cost effective. In this paper, we report the fabrication of an area array of helix interconnects on a silicon wafer. Also, we have studied the effect of interconnect geometry parameters on its mechanical compliance and electrical parasitics. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH interconnect. An optimization technique using response surface methodology has been applied to select the optimal structure parameters. The optimal compliant OTH interconnect will have a total standoff height of about 100 /spl mu/m, a radius of about 35 /spl mu/m and a cross section area of about 430 /spl mu/m/sup 2/.     

Analysis and decomposition of spatial variation in integratedcircuit processes and devices

Variation is a key concern in semiconductor manufacturing and is manifest in several forms. Spatial variation across each wafer results from equipment or process limitations, and variation within each die may be exacerbated further by complex pattern dependencies. Spatial variation information is important not only for process optimization and control, but also for design of circuits that are robust to such variation. Systematic and random components of the variation must be identified, and models relating the spatial variation to specific process and pattern causes are needed. In this work, extraction and modeling methods are described for wafer-level, die-level, and wafer-die interaction contributions to spatial variation. Wafer-level estimation methods include filtering, spline, and regression based approaches. Die-level (or intra-die) variation can be extracted using spatial Fourier transform methods; important issues include spectral interpolation and sampling requirements. Finally, the interaction between wafer- and die-level effects is important to fully capture and separate systematic versus random variation; spline- and frequency-based methods are proposed for this modeling. Together, these provide an effective collection of methods to identify and model spatial variation for future use in process control to reduce systematic variation, and in process/device design to produce more robust circuits     

Rapid characterization and modeling of pattern-dependent variationin chemical-mechanical polishing

Pattern-dependent effects are a key concern in chemical-mechanical polishing (CMP) processes. In oxide CMP, variation in the interlevel dielectric (ILD) thickness across each die and across the wafer can impact circuit performance and reduce yield. In this work, we present new test mask designs and associated measurement and analysis methods to efficiently characterize and model polishing behavior as a function of layout pattern factors-specifically area, pattern density, pitch, and perimeter/area effects. An important goal of this approach is rapid learning which requires rapid data collection. While the masks are applicable to a variety of CMP applications including back-end, shallow-trench, or damascene processes, in this study we focus on a typical interconnect oxide planarization process, and compare the pattern-dependent variation models for two different polishing pads. For the process and pads considered, we find that pattern density is a strongly dominant factor, while structure area, pitch, and perimeter/area (aspect ratio) play only a minor role     

Wafer-level hermetic MEMS packaging by anodic bonding and its reliability issues

This paper reviews wafer-level hermetic packaging technology using anodic bonding from several reliability points of view. First, reliability risk factors of high temperature, high voltage and electrochemical O₂ generation during anodic bonding are discussed. Next, electrical interconnections through a hermetic package, i.e. electrical feedthrough, is discussed. The reliability of both hermetic sealing and electrical feedthrough must be simultaneously satisfied. In the last part of this paper, a new wafer-level MEMS packaging material, anodically-bondable low temperature cofired ceramic (LTCC) wafer, is introduced, and its reliability data on hermetic sealing, electrical interconnection and flip-chip mounting on a printed circuit board (PCB) are described.     

Statistically based parametric yield prediction for integratedcircuits

This paper presents a novel procedure for predicting integrated circuit parametric performance and yield when provided with sample transistor test results and a circuit schematic. Two enhancements to the existing Monte Carlo simulation procedures are described: (1) a multivariate nested model is used to reproduce random process-induced device-variations, rather than the multivariate multinormal model typically used, and (2) the stochastic Monte Carlo method for mapping process variability into a performance distribution is replaced with a deterministic mapping technique. The use of multivariate nested distributions allows estimation not only of correlation between various model parameters, but also allows each of those variations to be apportioned among the various stages of the process (i.e., wafer to wafer, lot to lot, etc.). This allows matched devices to be more accurately simulated, without having to develop customized models for each configuration of matching, and provides focus for process improvement efforts into those areas with the maximum potential reward. The use of deterministic mapping provides simulation results which are repeatable and do not rely on chance to insure that the process parameter space has been evenly explored. A software package which implements the entire procedure has been written in C++     

Effects of pattern characteristics on copper CMP

Copper chemical mechanical polishing(CMP)is influenced by geometric characteristics such as line width and pattern density,as well as by the more obvious parameters such as slurry chemistry,pad type,polishing pressure and rotational speed.Variadons in the copper thickness across each die and across the wafer Can impact the circuit performance and reduce the yield.In this paper,we propose a modeling method to simulate the polishing behavior as a function of layout pattern factors.Under the same process conditions,the pattern density,the line width and the line spacing have a strong influence on copper dishing,dielectric erosion and topography.The test results showed:the wider the copper line or the spacing,the higher the copper dishing;the higher the density,the higher the dielectric erosion;the dishing and erosion increase slowly as a function of increasing density and go into saturation when the density is more than 0.7.     

Photolithography Control in Wafer Fabrication Based on Process Capability Indices With Multiple Characteristics

Photolithography, typically taking about one- third of the total wafer manufacturing costs, is one of the most complex operations and is the most critical process in semiconductor manufacturing. Three most important parameters that determine the final performance of devices are critical dimension (CD), alignment accuracy and photoresist (PR) thickness. Process yield, a common criterion used in the manufacturing industry for measuring process performance, can be applied to examine the photolithography process. In this paper, we solve the photolithography production control problem based on the yield index $S_{PK}$. The critical values required for the hypothesis testing, using the standard simulation technique, for various commonly used performance requirements, are obtained. Extensive simulation results are provided and analyzed. The investigation is useful to the practitioners for making reliable decisions in either testing process performance or examining quality of an engineering lot in photolithography.