Calculations of cutoff frequency, breakdown voltage, and capacitance for diffused junctions in thin epitaxial silicon layers

Recent developments in high-quality silicon varactors for low-noise parametric amplifiers and high-efficiency harmonic generators necessitate the use of epitaxial silicon layers that are thinner than 10 microns, with resistivity less than 1 Ω-cm. This paper extends Breitschwerdt's recent calculations [1] to such thin epitaxial layers, and also includes the calculation of series resistance and capacitance per unit area in a range useful for microwave diode design. A planar geometry for the junction has been assumed. The impurity distribution of the in-diffusion from the surface and the out-diffusion from the substrate are assumed to be complementary error functions. Depletion layer characteristics of the p-n junction-- including junction depth, impurity gradient at the junction, depletion layer width, capacitance per unit area, and avalanche breakdown voltage--are predicted for various epitaxial layer resistivities. The capacitance per unit area at breakdown is also presented in graphical form. Series resistance has been obtained by numerical integration of various impurity distributions. Zero-bias cutoff frequency for various layer thicknesses is presented graphically as a function of junction depth and breakdown voltage. The calculations predict that there are optimum diffusion conditions for maximum cutoff frequency and for maximum breakdown voltage with a given epitaxial layer thickness. They indicate that the optimum zero-bias cutoff frequency is nearly inversely proportional to the thickness of the epitaxial layer. For instance, the maximum cutoff frequency of a junction in a 2-µ layer can exceed 600 GHz compared with 300 GHz in a 4-µ layer, and 140 GHz in an 8-µ layer. Calculated and experimentally determined characteristics show reasonably good agreement.     

Space-charge layer width in diffused junctions

This paper outlines a calculation of space-charge layer width in a planar junction made by diffusing an n or p impurity (assumed to follow a Gaussian or a complementary error function distribution) into a uniformly doped crystal of opposite conductivity type. The collector junction of most drift transistors conforms closely to this model. An exponential approximation to the impurity distribution permits curves to be drawn of the space-charge layer penetration in each direction from the junction as a function of applied reverse voltage, and of the electric field distribution. The quantities involved are normalized in terms of the initial doping level N1, the impurity diffusion lengthL = 2 sqrt{Dt}, and the junction depth xj. The curves should be useful in calculating depletion-layer capacitance, transistor punch-through voltage and junction breakdown voltage.     

Voltages and electric fields of diffused semiconductor junctions

Equations are developed and graphs are presented, showing a functional relationship between electric field and space-charge widening and also between reverse bias voltage and space-charge widening, for diffused diodes. Planar geometry, with the diffusion made from a constant surface concentration (C0) into material of constant impurity density, is assumed. The voltage vs space-charge width relation is presented graphically for the case of silicon. Graphs for other materials are not included, since they would differ from the silicon graphs only by a constant in the voltage axis. These graphs illustrate that for small reverse voltages the junction may be considered as being essentially linear, while for large reverse voltages it may be considered as an abrupt junction. A graph is provided which may be used to gain a qualitative indication of the electric field distribution within the space-charge region. This graph also gives an indication of the transition of junction behavior from nearly linear to nearly abrupt as the reverse voltage is increased.     

An analytical method for two-dimensional field distribution of aMOS structure with a finite field plate

An analytical method is presented for two-dimensional field distribution of a MOS structure with a field plate, which allows explicit equations for field components in terms of oxide thickness, depletion width, and field plate length. Useful design curves of breakdown voltage versus substrate impurity concentration with oxide thickness and plate length as parameters are provided     

A mathematical study of space-charge layer capacitance for an abrupt p-n semiconductor junction

Simple approximation equations are presented for the space-charge layer capacitance of an abrupt p-n semiconductor junction. By direct comparison with exact capacitance calculations, this approximation method is shown to yield a maximum error of about 3.5% throughout a wide range of impurity atom density and reverse biasing voltage. In addition, calculations are presented to show the magnitude of error associated with several approximation equations presently available in the technical literature.     

Space-charge layer capacitance and offset voltage of an exponential-constant p-n junction

It is important to study an exponential-constant p-n junction because it gives a realistic approximation for many diffused p-n junction profiles. To calculate the space-charge layer capacitance for this junction we use an abrupt space-charge edge approximation with a correction which includes the effect of the mobile carriers at the edges of the space-charge region. In this approach the offset voltage v_off is used in place of the built-in potential as obtained from the depletion approximation. An analytical model for the space-charge region capacitance for an exponential-constant junction is developed. This model holds well for zero bias, for small forward voltages, and for reverse voltages. It shows good agreement when compared with the Chawla-Gummel model. It is simple and gives a direct relationship between the depletion capacitance and the applied voltage.     

单场限环结构的表面电场分布及环间距的优化

基于横向扩散与纵向扩散构成的冶金结边界为椭圆形这一特点,讨论单场限环结构表面电场强度的分布,给出表面电场强度、主结及环结分担电压的解析表达式。在纵向结深和掺杂浓度一定的条件下,根据临界电场击穿理论,讨论环间距的优化设计方法。单场限环结构主结环结间表面电场强度的绝对值曲线近似呈抛物线,最大电场位于主结处。随着环间距的增大,最大电场变大;随着横向扩散深度的增大,最大电场变小。环右侧最大电场也出现在结处,随着环间距和横向扩散深度的增加,最大电场均减小。在场限环结构中,当主结和环结在表面处的最大电场强度均等于临界电场强度时,击穿电压达到最大值,此时所对应的环间距为最佳环间距。     

Breakdown voltage of cylindrical Gaussian P-N junctions

Avalanche breakdown voltage data are presented for silicon planar p-n junctions in a form appropriate for use in the design or evaluation of impurity diffusion processes of the predeposit/drive-in type. Breakdown voltage is computed for a junction with an assumed Gaussian impurity density distribution and plane-cylindrical geometry, and is related to the amount of predeposited impurity, junction depth and background impurity density of the processed slice. Comparison is made between such data for Gaussian junctions and corresponding data for a one-sided step junction.

Data are also presented for specific examples of fabrication processes, showing the influence of changing the parameters that control the predeposit and drive-in cycles; designing the process and evaluation of the resulting device structures are discussed in the context of breakdown voltage. Experimental results obtained for fabricated device samples show good agreement with the breakdown voltage predicted theoretically in terms of the Gaussian model.     

EEPROM工艺中场开启电压的特殊要求与对策

ＥＥＰＲＯＭ要求场开启电压≥２０Ｖ，Ｐ－Ｎ结击穿电压也要求≥２０Ｖ，前者需提高场区杂质浓度，而后者则需要降低场杂质浓度，通过工艺模拟和实验找到了一种化解这个矛盾的对策，首先根据Ｐ－Ｎ结击穿电压的要求确定场区杂质浓度，继而大幅度调节场氧厚度，从而使二者都能满足要求。     

A review of HVI technology

The reduction of breakdown voltage (BV) influenced by high voltage interconnection (HVI) is a key problem in power integrated circuit, which essentially is that the modulation of electric field distribution at the device surface caused by HVI. In this paper, we review the developments of the methods to shield HVI including thick insulating film technology, field reduction layer technology, field plate technology and self-shielding technology. The four kinds of HVI technologies prevent BV degradation from the introduced adverse charge induced by interconnections in different ways. Thick insulting film technology increases the distance between the HVI and surface of silicon. Field reduction layer technology uses additional doping layers with optimized impurity concentration to enhance the depletion of the drift region under HVI. Field plate technology shields the influence of HVI with various field plate structures. Self-shielding technology makes HVI avoid crossing over high voltage junction terminal (HVJT), thus no additional shielding structure is needed. The divided reduced surface field (RESURF) technology solves the leakage current in the self-shielding structure.     

漂移区纵向线性掺杂的SOI高压器件研究

随着SOI层厚度的变化,当SOI层的厚度为2μm时,SOI LDMOS器件具有一个最佳的击穿电压.如果漂移区纵向的杂质浓度为线性分布,那么它的纵向电场就会为一个常数,击穿电压会达到最大值,而这种杂质浓度线性分布的漂移区可以通过热扩散得到.采用这种方法制得的SOI LDMOS的纵向击穿电压提高了43%,导通电阻降低了24%,这是因为它的表面浓度更高.     

Simulation of near-surface proton-stimulated diffusion of boron in silicon

A quantitative model for near-surface redistribution of doping impurity in silicon in the course of proton-stimulated diffusion is developed for the first time. According to the model, the near-surface peak of the impurity concentration is caused by migration of neutral impurity—self-interstitial pairs to the surface with subsequent decomposition of these pairs and accumulation of the impurity at the silicon surface within a thin layer (referred to as δ-doped layer). The depletion and enhancement regions that are found deeper than the near-surface concentration peak are caused by expulsion of ionized impurity by an electric field from the near-surface region of the field penetration. The field appears due to the charge formed in the natural-oxide film at the silicon surface as a result of irradiation with protons. The diffusion-kinetic equations for the impurity, self-interstitials, vacancies, and impurity—self-interstitial pairs were solved numerically simultaneously with the Poisson equation. It is shown that the results of calculations are in quantitative agreement with experimental data on the proton-stimulated diffusion of boron impurity in the near-surface region of silicon.     

C—V法测量pn结杂质浓度分布的基本原理及应用

全面地介绍了pn结C-V测量法的基本原理、测试设备及条件。利用pn结反向偏压时的电容特性推导了有效杂质浓度随深度分布的计算公式及突变结和线性缓变结的1/(C2)-V和1/(C3)-V关系图。应用该原理计算、分析了IN5401整流二极管pn结的特性及杂质浓度的纵向分布。     

非对称线性缓变结击穿电压的解析计算

通过有效掺杂浓度梯度的定义和耗尽近似求解 ,得到非对称线性缓变结击穿电压的简洁表达式。借助计算的有效掺杂浓度梯度和双边对称线性结击穿电压公式 ,可以方便地计算出非对称线性结的击穿电压。     

Analytical solutions for avalanche-breakdown voltages of single-diffused gaussian junctions

Closed-form solutions of the potential difference between the 2 edges of the depletion layer of a single diffused Gaussian p-n junction are obtained by integrating Poisson's equation and equating the magnitudes of the positive and negative charges in the depletion layer. By using the closed form solution of the static Poisson's equation and Fulop's average ionization coefficient, the ionization integral in the depletion layer is computed, which yields the correct values of avalanche breakdown voltage, depletion layer thickness at breakdown, and the peak electric field as a function of junction depth. Newton's method is used for rapid convergence. A flowchart to perform the calculations with a programmable hand-held calculator, such as the TI-59, is shown.     

Avalanche breakdown characteristics of a diffused P-N junction

A one-dimensional analysis is presented on the avalanche breakdown characteristics of a diffused p-n junction diode. By numerically integrating the carrier ionization rate in a junction space-charge layer, avalanche breakdown voltage is calculated for diffused diodes of silicon and germanium; this voltage is graphically illustrated throughout a range of parameters applicable to most practical situations. In addition, for calculating the maximum cutoff frequency of varactor diodes, junction capacity is similarly illustrated assuming the device is biased to avalanche breakdown. From these illustrations, and from an accompanying nomograph which relates the physical constants of a junction to its impurity atom gradient, the above parameters can be readily established without additional calculations. Further, examples are also presented to demonstrate the reduction of breakdown voltage resulting from a rapid increase of conductivity within the space-charge layer of a diffused p-n junction; this situation approximates many epitaxial and double diffused structures.     

On the validity of the gradual channel approximation for junction field effect transistors with drift velocity saturation

The errors are analyzed which result from the gradual channel approximation for junction field effect transistors with drift velocity saturation of carriers. Near the drain the neglect of the second derivative of potential with respect to position coordinate along the channel in Poisson's equation for the depletion layer is found to be more stringent than that of the field component normal to the channel boundary. The resulting errors are presented as a function of a dimensionless parameter which is proportional to mobility and pinch-off voltage and inversely proportional to channel length and saturation drift velocity. A modified channel boundary is constructed at which the boundary condition is exactly satisfied.     

Equivalent doping profile transformation: a semi-empirical,analytical method for predicting breakdown characteristics of anapproximate single-diffused parallel-plane junction

In this paper, a semi-empirical analytical method called the equivalent doping profile transformation method (EDPTM) has been proposed for the first time to predict the breakdown characteristics of an approximate single-diffused parallel-plane pn-junction that has a doping profile of the combination of a diffused side linear gradient constant and a constant substrate doping concentration, which considers the influence of the diffusion gradient level on the space charge region of the substrate side. Through the equivalent doping profile transformation, this approximate pn-junction turns into a double-sided asymmetric linear-graded junction (Jin et al., 1999). As a result, the breakdown voltage, critical peak electrical field, and the maximum depletion layer width can be carefully evaluated at different doping substrate concentration and gradient constant combinations. Compared with previous approximations such as abrupt and classical symmetrical linear-graded junctions, this method can give exact breakdown characteristics of a single-diffused pn-junction. The results are in excellent agreement with the numerical analysis, which proves the validity of this new method     

A simple method for determining the impurity distribution near a p-n junction

It is well known that the form of the dependence upon bias voltage of the incremental space-charge layer capacitance of an asymmetrically-dopedp-njunction depends (in a rather complicated way) upon the concentration profile of the impurity charge on the high-resistivity side. It is shown in this paper that this impurity profile is related, in a very simple way, to the dependence of the incremental space-charge layer elastance upon the total depletion charge in either half of the dipole layer. The incremental-elastance vs. charge relationship has been employed in a simple pulsed-charge automatic measurement system which yields the impurity profile directly, as the slope of anx-yrecording. The system has advantages for rapid evaluation of impurity distributions in the base regions of transistors. These same advantages apply for the high-resistivity sides of asymmetrically doped diodes, under circumstances in which the quick automatic plotting feature is needed, very high accuracy is not required, and the reverse saturation current of the junction is small.