AES/Rijndael算法协处理器设计与实现

AES／Rijndael算法是高性能的加密算法，具有极佳的抗攻击性能。文章提出了AES／Rijndael算法协处理器的半定制ASIC硬件实现方案，设计兼顾了处理速度与硬件资源耗费。其较高的加密强度，对于保护关键信息的安全具有很强的实用价值。方案在Cyclone系列FPGA芯片上实现，占用逻辑单元1400余个，综合仿真和实测的结果验证了本设计的正确性。     

AES算法的密码分析与快速实现

高级加密标准(AES)确定分组密码Rijndael为其算法,取代厂泛使用了20多年的数据加密标准(DES),该算法将在各行业各部门获得广泛的应用.文章以DES为参照对象,阐述了Rijndael算法的设计特色,介绍了AES在密码分析方面国内外已有的一些理论分析成果,描述了AES算法采用软件和硬件的快速实现方案.     

AES密码算法的FPGA优化设计

主要介绍基于FPGA的AES算法优化设计.从AES加密算-法的介绍、Rijndael算法的描述、AES密码算法的优化设计、AES密码算法的FPGA实现、PC机与FPGA的通信设计等方面论述实现硬件加密的方法,手段、可行性和优越性;实现了基于FPGA技术的Rijndacl算法,并给出了相应的各种仿真波形和结果.     

AES算法的高速实现

文章简要介绍了新的高级加密标准AES算法(Rijndael)的加密解密流程，分析了该算法自身的特点。解开了算法内部的轮循环，代之以流水线的方式实现。而且还分析了每次轮操作的内部过程，对轮操作内部的执行进行合并和简化，从而高速实现了AES算法的加密和解密。     

Rijndael算法的Java实现

本文介绍了高级加密标准(Advanced Encryption Standard,AES)Rijndael算法的 设计原则、步骤描述和特点,分析了该算法的基本操作,给出了Rijndael算法的Java实现。     

基于网络安全的数据加密技术的研究

数据加密技术是实现网络安全的重要技术之一。本文讨论了目前主要的一些数据加密算法：DES，IDEA，RSA算法及高级加密标准(AES)的Rijndael算法。介绍加密算法在网络中的有关应用及数据加密技术的发展状况。     

AES加密算法的原理与设计实现

2001年11月，NIST确定新的加密算法Rijndael为高级加密标准（AES），以取代安全性已经不能满足需要的的原数据加密标准（DES）。AES属于对称分组密码，可用128、192、256位密钥对128位的分组明文明文行加解密。本文在分析其算法结构和性能特点的基础上，作出了具体的设计实现。     

基于S盒优化的轻量级加密算法设计

分组密码一直是解决信息系统安全问题的常用加密方法。分组密码的典型代表数据加密标准DES（Data Encryption Standard）被广泛应用于软件加密和硬件加密,其中所体现的设计思想和设计原则依然值得研究和借鉴。S盒作为DES算法的一个关键环节,它的设计好坏直接影响DES的加密性能。通过对分组密码安全性设计的分析,立足于DES算法框架,提出了一种轻量级安全加密算法LEA（Light weight Encryption Algorithm）,通过增加位选逻辑陷阱来对S盒中的元素进行选取和重新优化设计,最后从S盒统计特性角度对其安全性进行分析。该算法能有效解决低成本系统的安全问题。     

DES算法的S盒的设计优化

DES(数据加密标准)算法被广泛应用于软件加密和硬件加密。S盒是DES算法中的一个关键环节,它的设计好坏直接影响DES的加密性能。VHDL(甚高速集成电路硬件描述语言)是借助EDA(电子设计自动化)工具进行硬件设计的基本描述语言。文中结合VHDL的特点,对使用VHDL设计S盒进行了一些分析,综合速度、资源利用率等提出了最优方案。     

按AES加密数据的新方法

为了在数据加密工程中推进一步推广AES标准,提高用AES标准加密数据的效率、安全性和灵活性,节省数据加密的软硬件资源,本论文用逻辑代数、二进制数、模2四则运算知识和GF域的四则运算知识对按照AES的数据加密算法Rijndael的具体实现进行了深入仔细地分析研究,提出了实现Rijndael的新方法和新技术,并对相关技术用通俗明确的语句进行了说明。本论文提出的数据加密的实现方法可以应用到实际工程中,具有节省数据加密器的软硬件资源的特点。     

Rijndael FPGA Implementations Utilising Look-Up Tables

This paper presents single-chip FPGA Rijndael algorithm implementations of the Advanced Encryption Standard (AES) algorithm, Rijndael. In particular, the designs utilise look-up tables to implement the entire Rijndael Round function. A comparison is provided between these designs and similar existing implementations. Hardware implementations of encryption algorithms prove much faster than equivalent software implementations and since there is a need to perform encryption on data in real time, speed is very important. In particular, Field Programmable Gate Arrays (FPGAs) are well suited to encryption implementations due to their flexibility and an architecture, which can be exploited to accommodate typical encryption transformations. In this paper, a Look-Up Table (LUT) methodology is introduced where complex and slow operations are replaced by simple LUTs. A LUT-based fully pipelined Rijndael implementation is described which has a pre-placement performance of 12 Gbits/sec, which is a factor 1.2 times faster than an alternative design in which look-up tables are utilised to implement only one of the Round function transformations, and 6 times faster than other previous single-chip implementations. Iterative Rijndael implementations based on the Look-Up-Table design approach are also discussed and prove faster than typical iterative implementations.     

基于FPGA的双通道旋转变压器测角系统

提出了一种基于FPGA的双通道旋转变压器测角电路设计方案,通过FPGA来控制AD2S82A、AD2S80A的解码和同步问题。同时用FPGA对转换后数据进行误差补偿和组合,以及二进制角度值的转换,提高了整个系统的集成度和可靠度。整个电路在Altium Designer 9.0设计环境下设计实现。采用Altera公司的EP2C35F484C6型FPGA芯片进行FPGA部分的仿真,实验和仿真的结果很好地实现了该方案的设计功能,并满足高精度、高速度转换的设计要求。     

FPGA Implementation(s) of a Scalable Encryption Algorithm

SEA is a scalable encryption algorithm targeted for small embedded applications. It was initially designed for software implementations in controllers, smart cards, or processors. In this letter, we investigate its performances in field-programmable gate array (FPGA) devices. For this purpose, a loop architecture of the block cipher is presented. Beyond its low cost performances, a significant advantage of the proposed architecture is its full flexibility for any parameter of the scalable encryption algorithm, taking advantage of generic VHDL coding. The letter also carefully describes the implementation details allowing us to keep small area requirements. Finally, a comparative performance discussion of SEA with the advanced encryption standard Rijndael and (a cipher purposed for efficient FPGA implementations) is proposed. It illustrates the interest of platform/context-oriented block cipher design and, as far as SEA is concerned, its low area requirements and reasonable efficiency.     

FPGA与S7-200的串行通信设计

FPGA在高速采集系统中的应用十分广泛,S7-200在工程应用中也十分普遍,将两者充分结合各取所长,可在高性能仪器仪表和电子产品中得到广泛应用。然而要实现两者的综合应用,就必须解决两者的通信问题,该文在Quartus II开发环境下采用Verilog语言和在STEP 7开发环境下采用梯形图编辑器实现了FPGA和S7-200之间的串口通信功能,其中FPGA通信部分采用了模块化的思想,S7-200使用了自由口通讯。经过仿真、下载调试,验证了设计方案的可行性及有效性,该设计具有较强的通用性和实际应用价值。     

描述Rijndael的一个新的方程组

由于Rijndael的S盒的代数表达式是逆函数合成GF(28)上一个q-多项式,该文合理假设S盒的变量并通过讨论各变量之间的关系,把Rijndael用GF(28)上一个多变量二次方程组来表示,使得Rijndael的密钥恢复等同于求解这个方程组.该方程组较Murphy-Robshaw方程组更简单,用XSL技术求解复杂度更低。     

Property of finite fields and its cryptography application

A new property of finite fields is discovered, that the co-ordinates of the finite field element are expressed by algebraic polynomials with the element itself as the variable. The new property is used to determine the algebraic expression of the Rijndael S box. Furthermore, it is shown why the expression of the Rijndael S box appears so simple.     

FPGA Implementation(s) of a Scalable Encryption Algorithm

SEA is a scalable encryption algorithm targeted for small embedded applications. It was initially designed for software implementations in controllers, smart cards, or processors. In this letter, we investigate its performances in recent field-programmable gate array (FPGA) devices. For this purpose, a loop architecture of the block cipher is presented. Beyond its low cost performances, a significant advantage of the proposed architecture is its full flexibility for any parameter of the scalable encryption algorithm, taking advantage of generic VHDL coding. The letter also carefully describes the implementation details allowing us to keep small area requirements. Finally, a comparative performance discussion of SEA with the Advanced Encryption Standard Rijndael and ${tt ICEBERG}$ (a cipher purposed for efficient FPGA implementations) is proposed. It illustrates the interest of platform/context-oriented block cipher design and, as far as SEA is concerned, its low area requirements and reasonable efficiency.      

AES算法的一种高效FPGA实现方法

在简要介绍AES算法(Rijndael)加密解密流程的基础上,结合该算法特点,采用复合域方法优化了S-Box的实现,并简化了MixColumns和InvMixColumns的结构,最后采用6级流水线在FPGA上加以高速高效实现.     

密钥控制的多S盒Rijndael算法

根据AESS盒的设计思想构造出了一批密码性能良好的S盒,并从方差的角度对它们的雪崩概率进行了分析。在此基础上,对Rijndael算法中的字节代换步骤SubBytes进行改进,从而提出了一种基于密钥控制的多S盒的Rijndael算法。实验结果表明,改进后的算法对差分攻击的抵抗能力有所提高,雪崩效应更趋合理。