Electrically reprogrammable nonvolatile semiconductor memory

Electrically reprogrammable nonvolatile memories using avalanche injection of electrons and holes into a floating gate are described. The fabrication data and the results of measurement on fabricated devices are shown. Analyses of the operation of the memory cell are done using conventional MOS transistors. The injection of current into silicon dioxide, its ratio to avalanche current, the WRITE speed, the basic data for analog memory, and the drift of the characteristics are measured and discussed.     

MAS-ROM-electrically reprogrammable ROM with decoder

The electrical characteristics of an MAS-ROM with on-the-chip X-Y matrix decoding and its reliabilities are evaluated. The MOS-ROM makes use of the so-called charge-storage phenomena in the gate insulator film and provides an electrical reprogrammable and nonvolatile integrated-circuit memory device in which one memory cell is composed only of an N-channel enhancement-type MAS transistor. The threshold voltage of the transistor is selectively increased by electron injection from the channel and decreased by the application of high negative voltage to the gate. The reliability test shows that the long-term decay has a logarithmic dependence on time with a slope of 0.7 V per decade of storage time under a gate voltage of +10 V at 150/spl deg/C.     

Well-driven floating gate transistors

A new layout structure for floating gate MOS devices on top of an isolating n-well is proposed. The well provides the floating device with noise isolation from the substrate and can also be used as an additional input for threshold voltage control or signal modulation     

Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell

The stacked-gate injection MOS transistor (SIMOS) uses a control gate stacked on the floating gate for selection of the cell during reading, programming, and erasure. Programming is achieved by the injection of hot electrons from the channel into the floating gate, resulting in a large upward shift in threshold voltage. In both states, operation is in the enhancement mode. Electrical erasure can be performed by injection of hot holes from an avalanche breakdown at the source-substrate junction and by Fowler-Nordheim electron injection from the floating gate to the source. Because the floating gate can be charged positively during the erasure, part of the channel is not covered by the floating gate, and in this way the enhancement mode of the SIMOS transistor after erasure is guaranteed. In a matrix array, the memory cell consists of the SIMOS transistor only. Decoders, read amplifiers, etc., can be integrated on the same substrate. Erasure can be performed as a block, or word-by-word. Different disturb effects on memory cells during programming and erasure are discussed. The cell area of the SIMOS memory is 850 µm². The photograph of a fully decoded 8192-bit SIMOS memory chip is presented.     

Substrate response of a floating gate n-channel MOS memory cell subject to a positive linear ramp voltage

A computer simulated substrate response of an n-channel MOS floating gate transistor to a positive linear ramping gate voltage was investigated. Device parameters, such as the channel length, effective electron mobility, substrate doping level and the gate voltage ramping rate were changed to see their effects on the substrate response. The substrate response was monitored by using the response of the surface potential at the mid-channel point. In the one-dimensional analysis it was found that the surface potential at the mid-channel point increased initially and dropped quickly after passing through its peak value and then decreased slowly. The mid-channel surface potential reached a higher peak value if the device had (1) a longer channel length, (2) a lower effective electron mobility, (3) a higher gate voltage ramping rate, or (4) a lower substrate doping level. Solutions show that the conditions for the mid-channel point to reach its peak surface potential faster are: (a) a shorter channel length, (b) a higher effective electron mobility, (c) a higher gate voltage ramping rate, and (d) a lower substrate doping level.     

High voltage floating gate array transistors

A new high voltage field-effect transistor is described. It features an array of uncontacted gate elements between the main gate and the drain which float so as to inhibit avalanche breakdown. Good agreement is obtained between model predictions and the performance of experimental devices fabricated in Si-TaSi/sub 2/ semiconductor-metal eutectic material. Transistors are demonstrated which hold off up to 1000 V, compared with the avalanche breakdown potential of 300 V or less expected for conventional devices made with similarly doped silicon.<>     

Low-voltage p-channel, n-channel and ambipolar organic thin-film transistors based on an ultrathin inorganic/polymer hybrid gate dielectric layer

A key issue in research into organic thin-film transistors (OTFTs) is low-voltage operation. In this study, we fabricated low-voltage operating (below 3V) p-channel, n-channel and ambipolar OTFTs based on pentacene or/and C₆₀ as the active layers, respectively, with an ultrathin AlO_X/poly(methyl methacrylate co glycidyl methacrylate) (P(MMA–GMA)) hybrid layer as the gate dielectric. Benefited from the enhanced crystallinity of C₆₀ layer and greatly reduced density of electron trapping states at the interface of channel/dielectric due to the insertion of ultrathin pentacene layer between C₆₀ and P(MMA–GMA), high electron mobility can be achieved in present pentacene/C₆₀ heterostructure based ambipolar OTFTs. The effect of the thickness of pentacene layer and the deposition sequence of pentacene and C₆₀ on the device performance of OTFTs was studied. The highest electron mobility of 3.50 cm²/V s and hole mobility of 0.25 cm²/V s were achieved in the ambipolar OTFT with a pentacene (3.0 nm)/C₆₀ (30 nm) heterostructure.     

Adaptive log domain filters for system identification using floating gate transistors

We describe an adaptive log domain filter with integrated learning rules for model reference estimation. The system is a first-order low pass filter implemented using multiple input floating gate transistors operating in subthreshold to realize on-line learning of gain and cut-off frequency. We use adaptive dynamical system theory to derive robust control laws for gain and cut-off frequency adaptation in a system identification task. Simulation results show that convergence is slower using simplified control laws but still occurs within milliseconds. Experimental results confirm that the estimated gain and cut-off frequency track the parameters of the reference filter. The adaptive log domain filter has measured power consumption of 33 μW. During operation, deterministic errors are introduced by mismatch within the analog circuit implementation. An analysis is presented which attributes the errors to current mirror mismatch.     

A p-channel MESFET on silicon using an erbium gate

A p-channel MESFET (metal semiconductor field-effect transistor) has been fabricated using erbium as gate material and iridium as source and drain contacts. The results show that it is possible to achieve p-type devices with characteristics comparable to n-type devices. As substrate silicon on sapphire (SOS) was used since it gives a well-defined channel thickness. The thickness of the silicon was 0.6 μm; after processing this was reduced to about 0.5 μm, which was, thus, the ultimate channel thickness.     

Electrically erasable f.a.m.o.s. memory structure using avalanche injection from floating gate

A new principle is proposed for an electrically erasable f.a.m.o.s. device using a simple m.o.s. technology with double polysilicon layers in which the lower (electrically floating) polysilicon gate is left undoped. Writing is accomplished by avalanche injection of electrons from a p-n junction in the substrate as in the original f.a.m.o.s. structure. Erasing proceeds by avalanche injection of electrons from the floating gate induced by voltage pulses applied to the heavily doped upper (control) gate.     

An 8192-bit electrically alterable ROM employing a one-transistor cell with floating gate

Describes a fully decoded, TTL compatible, electrically alterable, 8-kbit MOS ROM using a two-level n-channel polysilicon gate process. The memory cell consists of a single transistor with stacked gate structure where the floating gate covers only one part of the channel and is extended to an erase overlap of the source diffusion region off the channel. Programming in typically 100 ms/word is achieved by injection of hot electrons from the short channel (3.5 /spl mu/m) into the floating gate. Electrical block erasure is performed by Fowler-Nordheim emission of electrons from the floating gate. To avoid excessive avalanche breakdown currents during erasure 40 nm-50 nm oxides at the erase overlap and a voltage ramp are used. The memory operates with standard voltages (/spl plusmn/5 V, +12 V), during read, program and erase operation, a single pulsed high voltage (+26 V) for programming, and an erase voltage ramp of +35 V maximum. Typical access time is 250 ns.     

Downscaling of n-channel organic field-effect transistors with inkjet-printed electrodes

In this contribution we demonstrate for the first time a downscaled n-channel organic field-effect transistors based on N,N′-dialkylsubstituted-(1,7&1,6)-dicyanoperylene-3,4:9,10-bis(dicarboximide) with inkjet printed electrodes. First we demonstrate that the use of a high boiling point solvent is critical to achieve extended crystalline domains in spin-coated thin films and thus high electron mobility >0.1 cm² V⁻¹ s⁻¹ in top-gate devices. Then inkjet-printing is employed to realize sub-micrometer scale channels by dewetting of silver nanoparticles off a first patterned gold contact. By employing a 50 nm crosslinked fluoropolymer gate dielectric, ∼200 nm long channel transistors can achieve good current saturation when operated <5 V with good bias stress stability.     

Operation and characterization of N-channel EPROM cells

This paper describes the operation and characterization of N-Channel, double-polysilicon gate MOS structures that may be used in an Erasable, Programmable, Read-Only Memory (EPROM). The trade-offs for various structures with regard to writing ability, reading ability, fabrication complexity and ease of erasure are discussed. Measurements of the device are compared to the associated theory, and the sensitivity of the structure to various device parameters is also described.     

Electrical characteristics of boron-implanted n-channel MOS transistors

Back-gate-bias V_BG dependence of threshold voltage V_T and gate-bias V_G dependence of “gain” term β (and effective mobility μ_eff) of 50-keV-boron-implanted n-channel MOS transistors are described as functions of implant dose. In low field region, e.g. forward-biased V_BG, the slopes of √[?(φ_sub + V_BG)] vs V_T characteristics depend on the implant dose, while under high reverse bias, the slopes are constant and determined by the unimplanted substrate impurity concentration. Corresponding to this, the V_G vs β(μ_eff) characteristics indicate strong dose dependence and reduction of β(μ_eff) in low field, while in high field the reduction of β(μ_eff) is observed but not so significant. The effect is clear in the case of a deeply implanted layer or in case of a large ratio of effective channel length to width, as predicted by transistor equations.     

Flexible and transparent nanocrystal floating gate memory devices using silk protein

The charge storage behavior of a floating gate memory device using carbon nanotube-CdS nanostructures embedded in Bombyx mori silk protein matrix has been demonstrated. The capacitance – voltage characteristics in ITO/CNT–CdS-silk composite/Al device exhibits a clockwise hysteresis behavior due to the injection and storage of holes in the quantized valence band energy levels of CdS nanocrystals. The enhanced charge injection resulting in increase in memory window is observed at higher sweeping voltages. Nearly frequency independent hysteresis width over a wide range of 100 kHz–2.0 MHz, indicates its origin due to the charge storage in nanocrystals. The memory behavior of carbon nanotube–CdS nanostructures/silk nanocomposite devices has also been demonstrated on polyethylene terephthalate substrates, which may provide the way for flexible, transparent and printable electronic devices.     

Short channel erase in n-channel Si-gate MNOS EEPROM transistors

A unipolar method of erasing MNOS EEPROM transistors with short channel lengths by reverse-biasing of source and drain with gate and substrate grounded is described for n-channel Si-gate transistors. With pulse conditions kept constant, the threshold voltage shift caused by short channel erase (SCE) depends strongly on channel length and nitride thickness of the transistors. At effective channel lengths < 0.4 μm, SCE voltages V_SCE < 20 V are sufficient to cause a shift in the threshold voltage comparable to the value obtained with 25 V pulses using the conventional erase method and both voltage polarities.SCE voltage measurements at varied temperatures show that the results are in agreement with the model conception of the avalanche punch-through erase (APTE) mode. The retention data have been found regardless of the SCE treatment. Endurance has been investigated by multiple cycling of MNOS transistors using up to 10⁷ pulses of 25 V, 100 μs. The effective window width did not change, but the transconductance was found to decrease slightly with cycle number.     

Organic field-effect transistors and memory elements using deoxyribonucleic acid (DNA) gate dielectric

Deoxyribonucleic acid (DNA) bio-polymers derived from fish waste products are employed as gate dielectric in n-type methanofullerene as well as p-type pentacene based organic field-effect transistors working at low voltage levels and low gate leakage currents. Based on the large hysteresis in the transfer characteristics, operation of the transistor as a non-volatile memory element is shown. Practically hysteresis free operation of DNA based transistors is obtained at low voltage levels by adding an additional aluminium oxide blocking layer between the organic semiconductor and the DNA gate dielectric.     

Highly linear transconductance topology using floating transistors

A new technique for realising highly linear transconductances is presented. The technique is based on using floating transistors in the input stage of the transconductor, which act as source-followers along with a degeneration resistor. An example realisation of the technique is given together with circuit-level simulations     

Simple source/drain contact structure for solution-processed n-channel fullerene thin-film transistors

This paper describes a simple approach for reducing the contact resistances at the source/drain (S/D) contacts in solution-processed n-channel organic thin-film transistors (OTFTs). Blending poly(ethylene glycol) (PEG) into the fullerene semiconducting layer significantly improved the device performance. The PEG molecules in the blends underwent chemical reactions with the Al atoms of the electrodes, thereby forming a better organic-metal interface. Further, the rougher surface obtained after the addition of PEG could also increase the effective contact area, thereby reducing the resistance. As a result, the electrical properties of the devices were significantly improved. Unlike conventional bilayer structures, this approach allows the ready preparation of OTFTs with a low electron injection barrier at the S/D contacts.