Towards frozen organic PN junctions at room temperature using high-Tg polymeric electrolytes

Light-emitting electrochemical cells (LECs) based on a semiconducting polymer blended with lithium salt and novel polyelectrolytes have been studied. Random copolymers of poly(ethylene glycol) methyl ether methacrylate have been developed in order to increase their glass transition temperature (T_g) above room temperature. Devices have been optimized and successfully turned on upon heating. Cooling devices under applied voltage bias down to room temperature leads to frozen PN junctions. The relaxation of these junctions over voltage-free storage is studied. The higher the T_g, the longer the shelf-life of the junctions. This research opens the route to room temperature stable organic PN junctions for use in organic electronic devices such as light-emitting diodes, photovoltaic solar cells and other organic electronic devices.     

High efficiency n-CdS/p-InP solar cells prepared by the close-spaced technique

Heterojunction solar cells have been made by epitaxial growth of CdS on p-type InP using the close-spaced technique. Good rectification and photovoltaic properties have been observed in the cells grown on the (110) face of InP. The characteristics of the most efficient cell are V_oc = 807 mV, the fill factor = 0.74 and the power conversion efficiency = 14.4% under the solar input of 77 mW/cm². The photovoltaic properties of the cells obtained in this experiment are better than those reported elsewhere, and this is attributed to the superiority of the growth system to those of others in points that the junction is formed at relatively high temperature in a short time.     

Changes of electrical properties by Al content of AlxGa1−xAs in pHEMT structures as observed using HRXRD

Characterizations on the pseudomorphic High Electron Mobility Transistor structure under High-Resolution X-ray Diffraction (HRXRD) have been carried out at room temperature. Variation of Al contents in Al_xGa_1−xAs alloys has been found to show a shift of diffraction peaks. This variation is also found to show the change of lattice constant of crystal and also sheet carrier concentration as obtained from a Hall effect measurement. The latter phenomenon is considerably interesting to study in the early stage of the electrical properties of device based on the crystal structure.     

Thin film polycrystalline Si p-n junction solar cells with preferential doping

A model has been introduced for a polycrystalline thin film silicon p-n junction solar cell with preferential doping along the grain boundaries. Detailed numerical calculations have been done for the effect of doping depths along the grain boundaries, for different grain sizes, on the performance of the cell under AM1 conditions. The results indicate that preferential doping of grain boundaries leads to significant improvement of the cell performance.     

The C-V-f and G/ω-V-f characteristics of Al/SiO2/p-Si (MIS) structures

The frequency dependence of capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of the Al/SiO₂/p-Si metal-insulator-semiconductor (MIS) structures has been investigated taking into account the effect of the series resistance (R_s) and interface states (N_ss) at room temperature. The C-V and G/ω-V measurements have been carried out in the frequency range of 1 kHz to 1 MHz. The frequency dispersion in capacitance and conductance can be interpreted only in terms of interface states and series resistance. The N_ss can follow the ac signal and yield an excess capacitance especially at low frequencies. In low frequencies, the values of measured C and G/ω decrease in depletion and accumulation regions with increasing frequencies due to a continuous density distribution of interface states. The C-V plots exhibit anomalous peaks due to the N_ss and R_s effect. It has been experimentally determined that the peak positions in the C-V plot shift towards lower voltages and the peak value of the capacitance decreases with increasing frequency. The effect of series resistance on the capacitance is found appreciable at higher frequencies due to the interface state capacitance decreasing with increasing frequency. In addition, the high-frequency capacitance (C_m) and conductance (G_m/ω) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance. Experimental results show that the locations of N_ss and R_s have a significant effect on electrical characteristics of MIS structures.     

Laterally inhomogeneous barrier analysis of identically prepared Cd/CdS/n-Si/Au-Sb structures by SILAR method

In this study, CdS thin films have been deposited on n-Si substrate using a successive ionic layer adsorption and reaction (SILAR) method at room temperature. Structural properties have been investigated by means of X-ray diffraction (XRD) and scanning electron microscopy (SEM) measurements. The XRD and SEM investigations show that films are covered well, polycrystalline structure and good crystallinity levels. The Cd/CdS/n-Si/Au-Sb structures (28 dots) have been identically prepared by the SILAR method. The effective barrier heights and ideality factors of these structures have been obtained from forward bias current-voltage (I-V) and reverse bias capacitance voltage (C-V) characteristics. The barrier height (BH) for the Cd/CdS/n-Si/Au-Sb structure calculated from the I-V characteristics have ranged from 0.664 eV to 0.710 eV, and the ideality factor from 1.190 to 1.400. Lateral homogeneous barrier height has been determined approximately 0.719 eV from the experimental linear relationship between BHs and ideality factors. The experimental BH and ideality factor distributions obtained from the I-V characteristics have been fitted by a Gaussian function, and their means of values have been found to be (0.683 ± 0.01) eV and (1.287 ± 0.05), respectively. The barrier height values obtained from the reverse bias C⁻²-V characteristics have ranged from 0.720 eV to 0.865 eV and statistical analysis yields the mean (0.759 ± 0.02) eV. Additionally, a doping concentration obtained from C⁻²-V characteristics has been calculated (8.55 ± 1.62) × 10¹⁴ cm⁻³.     

ZnxCd1−xS/Cu2S heterojunction solar cells—I: Fabrication and performance

Alloy films of Zn_xCd_1?xS have been prepared by both vacuum evaporation and spray pyrolysis. Junctions of these films with Cu₂S have been formed by the solid state reaction for the evaporated alloy films and by the conventional chemiplating technique for the spray deposited alloy films. The current-voltage characteristics, diffusion length of minority carriers and spectral response of the cells have been determined. Highest conversion efficiency for the evaporated cells is 6.5% corresponding to x = 0 and for the sprayed cells is 5.6% corresponding to x = 0.1. The cell performance has been analysed and further scope of improvement indicated.     

ZnxCd1−xS/Cu2S heterojunction solar cells—II: Junction analysis

Cu₂S/Zn_xCd_1?xS heterojunction solar cells have been fabricated by two processes namely, spray pyrolysis and evaporation. The cells have been characterised in terms of the temperature dependence of the current-voltage and capacitance-voltage characteristics. Based on the analysis of the data, an energy band model has been proposed to explain the photovoltaic performance of the heterojunction. The dominant transport mechanism in both cases has been found to be interface recombination. The observed increase in open circuit voltage on increasing ZnS concentration has been understood on the basis of a reduction in the reverse saturation current caused primarily by an increase in the barrier height at the interface. The density of interface states is not observed to be significantly affected by the lattice parameter mismatch between Cu₂S and Zn_xCd_1?xS.     

The stability of electrical characteristics of Ti/n-Si/Ag,Ti/n-Si/Cu and Ti/n-Si/AgCu diodes prepared under the same conditions with respect to increasing aging time

The purpose of this study is to fabricate Ti/n-Si/Ag, Ti/n-Si/Cu and Ti/n-Si/AgCu Schottky type diodes and to investigate the effects of aging time on the diode parameters such as ideality factor, barrier height, series resistance, interface state density and rectification ratio. High purity titanium (Ti) metal was deposited on the back side of the n-Si semiconductor and then the Ti/n-Si junction was annealed at 420 °C in nitrogen atmosphere. This junction showed ohmic behavior. To fabricate rectifier contacts, Ag, Cu metals and AgCu alloy have been evaporated on the other polished surface of n-Si with Ti ohmic contact. Ag and Cu ratios in the AgCu alloy which are used in the process of preparing the Schottky contact were taken in equal weights. Thus, Ti/n-Si/Ag, Ti/n-Si/Cu and Ti/n-Si/AgCu Schottky type diodes were prepared under the same conditions. The current-voltage (I-V) characterization of Ti/n-Si/Ag, Ti/n-Si/Cu and Ti/n-Si/AgCu diodes were immediately made at room temperature in dark conditions. To investigate the effect of aging time, the I-V measurements of the diodes have been repeated after 1, 7, 15, 30 and 90 days. Characteristic parameters of the diode were calculated from the I-V measurements which are taken with respect to aging time. The results were compared. From these results, it can clearly be seen that the electrical characteristics of diode which is made from AgCu alloy are more stable than other two diodes.     

High performance TaYOx-based MIM capacitors

TaYO_x-based metal-insulator-metal (MIM) capacitors with excellent electrical properties have been fabricated. Ultra-thin TaYO_x films in the thickness range of 15-30 nm (EOT ∼ 2.4-4.7 nm) were deposited on Au/SiO₂ (100 nm)/Si (100) structures by rf-magnetron co-sputtering of Ta₂O₅ and Y₂O₃ targets. TaYO_x layers were characterized by X-ray photoelectron spectroscopy (XPS), energy dispersive X-ray (EDX) and X-ray diffraction (XRD) to examine the composition and crystallinity. An atomic percentage of Ta:Y = 58.32:41.67 was confirmed from the EDX analysis while XRD revealed an amorphous phase (up to 500 °C) during rapid thermal annealing. Besides, a high capacitance density of ∼3.7-5.4 fF/μm² at 10 kHz (ε_r ∼ 21), a low value of VCC (voltage coefficients of capacitance, α and β) have been achieved. Also, a highly stable temperature coefficient of capacitance, TCC has been obtained. Capacitance degradation phenomena in TaYO_x-based MIM capacitors under constant current stressing (CCS at 20 nA) have been studied. It is observed that degradation depends strongly on the dielectric thickness and a dielectric breakdown voltage of 3-5 MV/cm was found for TaYO_x films. The maximum energy storage density was estimated to be ∼5.69 J/cm³. Post deposition annealing (PDA) in O₂ ambient at 400 °C has been performed and further improvement in device reliability and electrical performances has been achieved.     

Analysis of electrical characteristics of Au/SiO2/n-Si (MOS) capacitors using the high-low frequency capacitance and conductance methods

The purpose of this paper is to analyze electrical characteristics in Au/SiO₂/n-Si (MOS) capacitors by using the high-low frequency (C_HF-C_LF) capacitance and conductance methods. The capacitance-voltage (C-V) and conductance-voltage (G/ω-V) measurements have been carried out in the frequency range of 1 kHz-10 MHz and bias voltage range of (−12 V) to (12 V) at room temperature. It was found that both C and G/ω of the MOS capacitor were quite sensitive to frequency at relatively low frequencies, and decrease with increasing frequency. The increase in capacitance especially at low frequencies is resulting from the presence of interface states at Si/SiO₂ interface. Therefore, the interfacial states can more easily follow an ac signal at low frequencies, consequently, which contributes to the improvement of electrical properties of MOS capacitor. The interface states density (N_ss) have been determined by taking into account the surface potential as a function of applied bias. The energy density distribution profile of N_ss was obtained from C_HF-C_LF capacitance method and gives a peak at about the mid-gap of Si. In addition, the high frequency (1 MHz) capacitance and conductance values measured under both reverse and forward bias have been corrected for the effect of series resistance (R_s) to obtain the real capacitance of MOS capacitors. The frequency dependent C-V and G/ω-V characteristics confirm that the N_ss and R_s of the MOS capacitors are important parameters that strongly influence the electrical properties of MOS capacitors.     

Morphological and electrical characterization of SixCryCzBv thin films

Si_xCr_yC_zB_v thin films with several compositions have been studied for integration of high precision resistors in 0.8 μm BICMOS technology. These resistors, integrated in the back-end of line, have the advantage to provide high level of integration and attractive electrical behavior in temperature, for analog devices. The film morphology and the structure have been investigated through transmission electron microscopy analysis and have been then related to the electrical properties on the base of the percolation theory. According to this theory, and in agreement with experimental results, negative thermal coefficient of resistance (TCR) has been obtained for samples with low Cr content, corresponding to a crystalline volume fraction below the percolation threshold.Samples with higher Cr content exhibit, instead, a variation of the TCR as a function of film thickness: negative TCR values are obtained for thickness lower than 5 nm, corresponding to a crystalline volume fraction below the percolation threshold; positive TCR are obtained for larger thickness, indicating the establishment of a continuous conductive path between the Cr rich grains. This property seems to be determinant in order to assure the possibility to obtain thin film resistors almost independent on the temperature.     

A study of the conduction properties of a rectifying nGaAs-n(Ga,Al)As heterojunction

The I–V characteristics of a rectifying nGaAs-nAl_xGa_1-xAs heterojunction (x ≈ 0.28) have been measured over a temperature range of 145–300°K and compared with theory. The non-saturating behavior of the reverse current can be explained by using the graded gap model for the heterojunction. The conduction band-edge step at the interface, determined from these measurements, is 280 meV, in good agreement with existing evidence. This model however fails to account for the forward current, which exhibits an anamolous “pseudo-saturation” behavior. The forward characteristics are qualitatively explained by including in the model deep-level states near the interface, which become negatively charged under forward bias.     

Temperature-dependent current-voltage characteristics of Cr/n-GaAs Schottky diodes

The Cr/n-GaAs/In Schottky contacts have been formed using dc magnetron sputtering. The current-voltage (I-V) characteristics of the device have been measured by steps of 20 K in the temperature range of 60-320 K. The ideality factor n of the device has remained about unchanged between 1.04 and 1.10 and Schottky barrier height around 0.58-0.60 eV from 320 K down to 160 K. It can be said that the experimental I-V data are almost independent of temperature above 160 K. After 160 K, the n value increased with a decrease in temperature and become 1.99 at 60 K. The I-V characteristics at high temperatures have been exactly explained by the standard TE model. The nature and origin of abnormal behaviors at low temperatures have been successfully explained by the current flow through the low SBH circular patches suggested by Tung and used by some studies in literature. It has been seen that the straight line of the nT vs. T plot with a T₀ value of 14 K was parallel to that of the ideal Schottky contact. Again, a lateral homogeneous BH value of 0.62 eV was calculated from the linear relationship between the ideality factor and barrier height values. It has been seen that he ?(T = 0) and BH temperature coefficient α values obtained from the flat band BH and the Norde’s model plots are in close agreement with each other.     

Characterization of p-CdTe/n-CdS hetero-junctions

Nano-crystalline CdTe/CdS thin film hetero-junctions have been grown on glass substrate by thermal evaporation technique. The growth conditions to get stoichiometric compound films have been optimized. The grown hetero-junctions have been characterized for their I–V characteristics. Analysis of I–V characteristics has been made to investigate the current conduction mechanism in p-CdTe/n-CdS hetero-junction. The band gap energy of cadmium telluride and cadmium sulfide films have been computed from the study of variation of resistance with temperature. Based on the study, band diagram for p-CdTe/n-CdS hetero-junction has been proposed.     

A computer-aided simulation model for the I–V characteristic of M-n-p silicon Schottky-barrier diodes produced by use of low-energy arsenic-ion implantation

Current-transport properties of Al-n-p silicon Schottky-barrier diodes have been studied both experimentally and theoretically. An analytical model for the I-V characteristic of a metal-n-p Schottky barrier diode has been developed by using an interfacial layer-thermionic-diffusion model. Assuming a Gaussian distribution for the implanted profile, the barrier-height enhancement and ideality factor have been derived analytically. Using low energy (25 KeV) arsenic implantation with the dose ranged form 8 × 10¹⁰/cm² to 10¹²/cm², Al-n-p silicon Schottky barrier diodes have been fabricated and characterized. Comparisons between the experimental measurements and the results of computer simulations have been performed and satisfactory agreements between these comparisons have been obtained. The reverse I–V characteristics of the fabricated Al-n-p silicon Schottky barrier diodes can also be well simulated by the developed model.     

Some electrical properties of polyaniline/p-Si/Al structure at 300 K and 77 K temperatures

The electrical characterization of the PANI/p-Si/Al structure has been investigated by using current-voltage (I-V), capacitance-voltage (C-V) and capacitance-frequency (C-f) characteristics. Especially, some characteristics have been compared with the 300 K temperature characteristics at liquid nitrogen temperature. The characteristic parameters of the structure such as barrier height, ideality factor and series resistance have been determined from the current-voltage measurements. According to the C-V characteristics, the higher values of capacitance at low frequencies and high temperature have been attributed to the excess capacitance resulting from the interface states in equilibrium with the p-Si, which can follow the a.c. signal.     

Electrical properties of manganese doped Ga1−xInxAs grown by liquid phase epitaxy

Mn-doped Ga_1?xIn_xAs crystals (0 < x < 0.25) have been grown by the LPE technique, and the doping characteristics and electrical properties of the layers have been studied by Hall measurement. The distribution coefficient of Mn has been found to depend on the substrate orientation. The acceptor enerby level is about 77 meV and is comparable to that of Mn-doped GaAs. p-n junction diodes with high InAs compositions, grown using the step grading technique, showed a diode factor of 2. Electron diffusion lengths greater than 3μm have been measured in these Mn doped layers.     

Measurement of space charge generation-recombination current in Hg1−xCdxTe photodiodes by deep level transient spectroscopy

Deep Level Transient Spectroscopy (DLTS) measurements have been used to characterize n⁺ ? pHg_1?xCd_xTe junction photodiode performance. Deep level results obtained on a x = 0.320 liquid phase epitaxial grown photodiode and a x = 0.219 bulk quench anneal-grown photodiode have identified deep Shockley-Read recombination centers. Detailed characterization of trap energy, trap density, and capture cross sections for these traps located within the diode depletion region have been used to predict a space charge generation-recombination current and dynamic resistance-area product at zero bias voltage. This paper presents for the first time a direct correlation of DLTS parameters with photodiode device performance.     

Electrical properties of MOS diodes In/TiO2/p-CdTe

In/TiO₂/p-CdTe MOS diodes, which have a rectification coefficient of K = 6 × 10³ at an external bias of 2 V, are fabricated for the first time by means of the inexpensive spray-pyrolysis method. It is established that tunnel-recombination processes in the MOS structures under investigation for forward and reverse voltages with the participation of levels at an energy depth of 0.25 eV are the dominant current-flow mechanism. The features of the voltage-capacitance characteristics of In/TiO₂/p-CdTe MOS diodes testify to a sharp decrease in the resistance of the TiO₂ high-resistance layer at forward bias, which is caused by the relation between the energy parameters of components of the MOS structure under investigation.