Polycrystalline silicon resistors for integrated circuits

The suitability of thin films of doped polycrystalline silicon on SiO₂ substrates for the production of high value resistors for monolithic integrated circuits is considered. Resistors fabricated from this material posses the advantages of high sheet resistivity and dielectric isolation while still preserving an all silicon technology compatible with conventional production techniques.Relevant structural and electrical properties of doped polycrystalline films produced by both vacuum evaporation onto hot substrates with gas-doping and by diffusion-annealing of amorphous films have been investigated. Sheet resistivities and TCR values measured on 2500 Å polycrystalline films have proved superior to those encountered with conventional diffused resistors. Typically films with sheet resistivities of 1 kΩ/□ had TCR's of ?1000 ppm/°C while conventional diffused resistors are generally made from material of 200 Ω/□ and +2000 ppm/°C TCR. Etched resistor line widths of 0·25 mil. have been obtained in the polycrystalline material employing conventional photolithographic techniques. The temperature stability and linearity of doped polycrystalline resistors have been investigated.     

Gigaohm-range polycrystalline silicon resistors for microelectronic applications

The objective of this work was to investigate the conduction properties of very high resistance devices formed from undoped chemical-vapor-deposited polycrystalline silicon. Test structures having resistances as high as 600 GΩ at 5 V were fabricated, of a size suitable for microelectronic device applications. Detailed measurements of current-voltage characteristics in the dark and with photoexcitation, the effect of resistor length, and the temperature dependence of resistance, were made. The data is interpreted in terms of a model based on avalanche breakdown of the reverse-biased n⁺-i junction, with the current limited by the remaining quasi-neutral i-region. Theoretical current-voltage curves and the dependence of effective resistance on device length are calculated with the model, showing all the qualitative aspects of the data. Incorporation of gigaohm-range load resistors into a 16K CMOS static RAM cell is described. The work shows the dominant effects of grain boundaries in controlling current transport in undoped polysilicon, providing high-diffusivity paths for impurity diffusion, and apparently determining the reverse breakdown behavior of the junctions present.     

Excess noise measurements in ion-implanted silicon resistors

The low-frequency noise spectra of partially annealed boron-implanted silicon resistors with various geometries are measured. The implantation energies are 50, 80 and 110 keV and the doses are 2·5 × 10¹² cm^?2, 1·0 × 10¹³ cm^?2 and 1·0 × 10¹⁴ cm^?2. The spectra exhibit thermal noise and $\text{?}{}^{\mathrm{?n}}$ (excess) noise exclusively. Investigations indicate that the contracts from the implanted layer to the electrode generally contribute small amounts to the total excess noise observed. The excess noise exhibits a strong dependence on the sheet resistance of the layers, while the dependence on substrate bias, implantation energy, and on temperature is relatively weak. A discussion of the results is given in terms of a volume effect. Noise measurements on implanted layers, produced under carefully controlled conditions, show promise as a tool to investigate excess noise.     

Modeling and optimization of monolithic polycrystalline silicon resistors

The processing parameters of monolithic polycrystalline silicon resistors are examined, and the effect of grain size on the sensitivity of polysilicon resistivity versus doping concentration is studied theoretically and experimentally. Because existing models for polysilicon do not accurately predict resistivity dependence on doping concentration as grain size increases above 600 Å, a modified trapping model for polysilicon with different grain sizes and under various applied biases is introduced. Good agreement between theory and experiments demonstrates that an increase in grain size from 230 to 1220 Å drastically reduces the sensitivity of polysilicon resistivity to doping levels by two orders of magnitude. Such an increase is achieved by modifications of the integrated-circuit processes. Design criteria for the optimization of monolithic polysilicon resistors have also been established based on resistivity control, thermal properties, and device geometry.     

Electrical trimming of heavily doped polycrystalline silicon resistors

The newly discovered phenomenon of resistance decrease in heavily doped polycrystalline silicon resistors by conduction of high current densiy has been investigated experimentally. Threshold values exist for the impurity concentration and for the applied current density for the occurrence of this phenomenon. Decreased resistance is stable as far as current higher than the threshold value is not applied thereafter. Applications to D/A converters and operational amplifiers are described. Electrical trimming of resistors in the circuits with accuracy of ±0.01 percent is easily attained.     

Some annealing properties of low-energy-antimony—implanted silicon resistors

Shallow-implanted antimony in silicon can be used in fabricating n-type silicon resistors with very low temperature coefficient of resistance (TCR), controllably and reproducibly. This paper reports a study of the sheet resistance of silicon resistors implanted with ¹²¹Sb at 10 keV, for various doses and annealing conditions. The methods used in fabricating samples and taking measurements were described in an earlier paper[1]. For high doses, ～ 10¹⁵ Sb/cm², we found that two-stage annealing[2]—preannealing at 550°C followed by annealing at 1000°C—improves the electrical conductivity. For low doses, ～10¹² Sb/cm², the final annealing determines the conductivity. For medium doses, ～10¹³–10¹⁴ Sb/cm², the interplay of damage-annealing and activation of Sb in Si introduces complications, giving a crossover of shet resistance vs implant dose for various annealing temperatures. For doses around 3 × 10¹³ cm^?2, the resistances are very insensitive to the details of annealing sequence and temperature; also the TCR is very low, about 50 ppm/°C. The effect of annealing conditions for various doses, resistivities and TCR values are discussed.     

Popcorn noise and generation-recombination noise observed in ion-implanted silicon resistors

Experimental results show that, for low currents, the generation-recombination noise component increases with current, and, at higher currents, it decreases inversely with current. For currents greater than a certain value, a generation-recombination noise component is scarcely observed.     

A new computer-aided simulation model for polycrystalline silicon film resistors

A general transport theory for the I–V characteristics of a polycrystalline film resistor has been derived by including the effects of carrier degeneracy, majority-carrier thermionic-diffusion across the space charge regions produced by carrier trapping in the grain boundaries, and quantum mechanical tunneling through the grain boundaries. Based on the derived transport theory, a new conduction model for the electrical resistivity of polycrystalline film resitors has been developed by incorporating the effects of carrier trapping and dopant segregation in the grain boundaries. Moreover, an empirical formula for the coefficient of the dopant-segregation effects has been proposed, which enables us to predict the dependence of the electrical resistivity of phosphorus-and arsenic-doped polycrystalline silicon films on thermal annealing temperature.Phosphorus-doped polycrystalline silicon resistors have been fabricated by using ion-implantation with doses ranged from 1.6 × 10¹¹ to 5 × 10¹⁵/cm². The dependence of the electrical resistivity on doping concentration and temperature have been measured and shown to be in good agreement with the results of computer simulations. In addition, computer simulations for boron-and arsenic-doped polycrystalline silicon resistors have also been performed and shown to be consistent with the experimental results published by previous authors.     

The stability of polycrystalline silicon thin film resistors measured using excess noise

The resistance of thin films of polycrystalline silicon prepared by chemical vapour deposition is found to vary with time and with cycling the temperature or strain. These variations of resistance are compared with the magnitude and variations of the excess, , noise which is known to be an equilibrium resistance fluctuation. The noise is found to be sensitive to the detailed state of the specimen.     

硅基高精度镍铬薄膜电阻的制备和性能表征

集成无源元件（IPD）技术可以将分立的无源元件集成在衬底内部,提高系统的集成度。为了获得高精度的薄膜电阻,采用多层薄膜电路工艺在硅晶圆上制备了不同线宽的镍铬薄膜电阻,利用显微镜和半导体参数测试仪对薄膜电阻的图形线宽及电学特性进行了表征及测试。结果表明,制备出的镍铬薄膜电阻线宽精度在±5%以内,电阻精度在±0.5%以内,具有稳定的电学特性。基于镍铬的高精度硅基无源集成电阻器在系统集成中有广泛的应用价值。     

A compatible technique for the formation of thin tantalum film resistors on silicon integrated circuits

A problem in the production of silicon integrated circuits has been yield limitation and applicability restriction due to the large variation and temperature sensitivity of diffused silicon resistors. Use of a thin-film resistive complement on silicon integrated circuits improves performance of many microcircuits heretofore made by the silicon planar process alone. The technique for thin-film on silicon integrated circuits is based on a two-metal resistor-conductor system: tantalum and aluminum. Tantalum was selected as the resistive material because it can be cathodically sputtered with ease, and a wide range of specific resistivity is available as a result of the controlled energy sputtering technique. The process involves production of the active element part of the circuit with standard silicon integrated circuit planar techniques, including contacting the cuts with deposited aluminum. The only deviation from the standard process lies in leaving some unetched SiO2surface area for resistor deposition. Tantalum is cathodically sputtered over the wafer, and delineated by standard photolithographic techniques to form resistor, conductor, and pad areas. A second layer of aluminum is then vacuum deposited over the wafer, and this is delineated to cover the pad and conductor areas of the tantalum with a high conductivity overlay. The exposed tantalum is then thermally stabilized and the final sheet resistivity adjusted by the resulting controlled sheet resistivity increase. The resulting circuits contain stable resistors with tolerance distributions of ±5 percent to ±10 percent, and TCR of -200 to -300 PPM/°C. The silicon active elements in the circuits do not degrade as a result of the thin-film resistor formation.     

Determination of self-heating and thermal resistance in polycrystalline and bulk silicon resistors by DC measurements

Self-heating of silicon resistors (fabricated in polycrystalline and bulk silicon) which are used as passive devices in analog circuits and as ESD-Protection elements is characterised in this work by purely DC measurements. A methodology using the device simultaneously as heater and temperature sensor is presented. Extraction of thermal resistance is derived and discussed. Different types of resistors including a wide range of different geometries are characterised, the geometry dependence of the thermal resistance is determined for different resistor types. Theoretical models describing geometry dependence for thermal resistance are in very good agreement with the presented results.     

noise measurements in ion-implanted silicon resistors as a function of the substrate reverse bias voltage

The 1/ƒ noise of ion-implanted resistors has been measured as a function of a reverse bias voltage. Using a substrate bias, the sheet-resistance was changed. It has been empirically found that the relative 1/ƒ noise is proportional to the square of the resistance.     

A quantitative model of the effect of grain size on the resistivity of polycrystalline silicon resistors

The effect of grain size on the resistivity of polycrystalline silicon films has been investigated theoretically and experimentally. It is shown that existing models do not accurately predict the resistivity dependence on doping concentration as grain size increases. A new modified trapping theory demonstrates from a good agreement with experimental results that a significant increase in grain size drastically reduces the sensitivity of polysilicon resistivity to doping concentration.     

Nonlinear metal resistors

Rectifying I/V characteristics were observed for a thin-metal-film structure made of gold, aluminium and silver vacuum-deposited layers. Also discontinuities were found in the slope resistance of these films. The structure of the devices is described, and typical I/V and slope-resistance characteristics are presented.     

Implanted high value resistors

High value resistors are desirable in integrated circuits and they can be made by ion implantation. The linearity of conventional boron implanted resistors is not, however, always satisfactory.

Methods for improving the voltage linearity of ion-implanted, integrated circuit resistors are described in this paper. In particular the use of a damaging implant was investigated in detail. Hall effect measurements as a function of temperature have shown that a deep acceptor was produced by the damage. The improved linearity observed in such layers was mainly due to the presence of this deep level, rather than to reduction of mobility. A simple theory was developed that reproduced resistor behaviour satisfactorily.

It was confirmed that the use of a known deep acceptor, such as indium, also led to improved linearity.     

Buried-guarded layer ion-implanted resistors

Megohm silicon monolithic resistors have been fabricated with sheet resistances up to 120 kΩ/□ using an implanted p-layer resistor which is buried under an implanted n-guard layer. The n-guard layer protects against slice-to-slice variations of the fixed surface charge, and was made using phosphorus doses and energy of 1.5-5 × 10¹²/cm²and 30 keV. Resistors have been fabricated up to 20 MΩ; sheet resistances were in the range of 7-120 kΩ/□ using boron doses and energies of 1-3 × 10^:12/cm²and 30-300 keV. The sheet resistance, voltage dependence of resistance, temperature coefficients, junction leakage, and parasitic capacitance have been measured for different implantation parameters. This process has been used to fabricate two matched 8-MΩ resistors for use in a high input impedance differential preamplifier integrated circuit. A match of 2 percent and a magnitude tolerance of ±10 percent has been achieved. The temperature coefficient of resistance (TCR) is about 4000 ppm/°C and tracks within 400 ppm/ °C. These resistors are linear up to ∼1 V, about 50 times higher bias voltage than required in the application. The structure and fabrication are compatible with present monolithic silicon integrated circuit processing.     

电阻涂料的施工应用技术

电阻涂料的施工应用技术是电阻器生产厂家经常遇到的问题。介绍电阻涂料的涂装工艺、涂装环境、质量检查、涂膜弊病的防止、涂料组分对施工性的影响和防火安全技术 ,为国产电阻器涂料的应用提供方便。