An investigation of steady-state velocity overshoot in silicon

Electron dynamics in silicon is investigated by means of improved momentum- and energy-balance equations including particle diffusion and heat flux. The resulting system of partial differential equations is numerically solved in a variety of field configurations including strong discontinuities, in order to enhance velocity overshoot effects. It is found that diffusion, usually neglected in previous studies, plays a major role, and considerably modifies the features of the velocity vs distance curve, leading to an increase of the carrier drift velocity in the low-field region, i.e. before experiencing the effect of the strong field. In addition, it is found that, in order to take full advantage of velocity overshoot effects in MOSFET's, a structure must be designed having the strongest possible field at the source-end of the channel, where carrier density is controlled by the gate.     

Effect of velocity/field characteristics on the operation of avalanche-diode oscillators

The velocity/field characteristics of the carriers traversing the drift region in an avalanche diode can have profound effects on the operational parameters of the device. The letter describes these effects in terms of a theory that imposes the velocity/field characteristic on the simple Read-diode model. The effect of the velocity/field dependence is to alter the external induced current waveshape at large signal levels. For carriers with characteristics similar to electrons in GaAs, the modification is in the form of a spike in a class-C configuration. In silicon, the spike is negative and lossy. The analysis demonstrates one of the basic advantages of GaAs as a material for avalanche-diode fabrication and also predicts a power-saturation effect in silicon Read diodes at efficiencies in the 20 to 25% region.     

The influence of boundary conditions and the bias on amplification from negative differential mobility elements

We demonstrate from a study of the small signal impedance properties of supercritical negative differential mobility (NDM) element that the various modes of device amplification are determined primarily by cathode conditions and the bias. These conclusions are drawn from 1) a detailed analytical investigation where cathode conditions are represented by prespecified values of electric field, and 2) by synthesizing previously published studies. Briefly, it is shown that multiple (bias induced stable-unstable-stable) amplifying states will arise from NDM elements with cathode fields Ecwithin the NDM region. (Here, the different states occur when the device dc current density is, respectively, less than, approximately equal to, or greater than a critical value of current Jc. Jcis determined by Ec.) Single amplifying states will arise from elements with values of Ecthat are either less than the NDM threshold field value, or within the saturated drift velocity region. (In the latter case, time-dependent values for Ecare required.) The study proposes that general features of the space-charge profiles and the cathode conditions may be ascertained from measurements of 1) the small signal device impedance as a function of bias level, and 2) the dc current versus voltage relation.     

An engineering model for short-channel MOS devices

An engineering model for short-channel MOS devices which includes the effect of carrier drift velocity saturation is described. Based on a piecewise carrier drift velocity model, simplified expressions for the DC drain current I_D, the small signal transconductance g_m and the output conductance g _ds in the saturation region are derived. For a given gate voltage, the expressions depend only on the threshold voltage V _T and the dimensions of the device, whose desired values are normally known     

An analytical model for the low- emitter-impurity-concentration transistor

The epitaxial transistor model developed by Grung and Warner is adapted for predicting the characteristics of the low-emitter-impurity-concentration (LEC) transistor. The model predicts the following results for the low region (the lightly-doped emitter region): through a given cross section, the minority-carrier drift current is typically larger than the minority-carrier diffusion current. In other words, the model predicts that the conventional low-level minority-carrier diffusion equation is invalid for the low region, especially for typical bias levels. As a result, the effect of the electric field on minority carriers cannot be neglected in the low region of the LEC transistor and (by extension) in the corresponding low regions of such devices as the epitaxial diode and the integrated-injection-logic transistor.     

Theory and small signal analysis for a new bipolar injectiontransit time device (BIPOLITT)

We have proposed and analyzed a new millimeter and submillimeter wave transit time device, the bipolar injection and transit time diode (BIPOLITT). The theory and small signal analysis for a two-terminal type rf operation is presented here. The device structure is similar to a heterojunction bipolar transistor (HBT) with an rf floating base. The relatively longer base is utilized to achieve an injection-phase delay close to 180°. The collector depletion region is used as drift region. As an example, a BIPOLITT diode for 300-400 GHz operation is designed, and its small signal specific negative resistance is calculated to be about -3×10^-7 Ω·cm²      

有机电致发光器件发光层中电场与载流子浓度分布的数值研究

以陷阱电荷限制传导理论为基础 ,用数值方法研究了单层有机电致发光器件发光层中电势、电场和载流子密度的空间分布 .分析结果表明 ,电场强度在靠近两边电极的地方上升很快 ,而在中间区域几乎是线性地缓慢增大 .大部分载流子分布在靠近两个电极的地方 ,只有少量分布在中间区域 .在靠近注入电极的地方扩散电流大于漂移电流 ,而在其它区域漂移电流大于扩散电流.     

Experimental and Computed Four Scattering and Four Noise Parameters of GaAs FET's Up to 4 GHz (Short Papers)

The four scattering parameters, operating in the pinch-off mode, of a Schottky-barrier-gate FET (MESFET) are investigated with the aid of an appropriate equivalent circuit. The dependence of the electron drift velocity on the electric field of the channel has been simplified to be piecewise linear by Turner and Wilson. Hot electron effects have therefore been neglected. The four noise parameters of the device have also been computed using the noise sources of van der Ziel. All computed parameters are compared with their measured values in the frequency region 0.5-4 GHz. Investigated GaAs FET's are commercial units.     

Optimization of high voltage LDMOSFETs with complex multiple-resistivity drift region and field plate

An improved high voltage LDMOSFET with multiple-resistivity drift region is proposed. Using the 2-D process simulator TSUPREM4 and device simulator MEDICI, we design a conventional LDMOSFET optimized for breakdown voltage. Then multiple-resistivity drift region is incorporated, with optimized thickness and doping concentration to reduce specific on-resistance while the breakdown voltage is not degraded. To further improve the device performance, we apply a field plate above the drift region to attract more electrons. Carrier concentration in the channel is increased, so drain current level is improved. The simulation result shows that the optimized complex structure, containing both multiple-resistivity drift region and a field plate, exhibits a 34.2% reduction in specific on-resistance with a mere 2.5% degradation of breakdown voltage compared to the standard LDMOSFET.     

长波长InGaAs扩散结PIN光电二极管正面入光结构的理论分析

本文指出,对扩散pn结的正面入光结构,突变结理论有一定局限性。由于p~+区内杂质浓度的分布,在扩散区中存在十分强的自建漂移场,因而光生载流子将在自建场的作用下漂移进pn结内。由于载流子的漂移速度V_d远大于扩散速度V_f,因此可制得性能优异的PIN光电二极管,制作工艺比背面入光结构简单。已制得光电响应时间低达80ps的正面入光PIN二极管。     

Importance of low-field drift velocity characteristics for HEMT modeling

The drift velocity versus field relationship, which is precisely calculated by taking into account electronic states and dominant two-dimensional scatterings, is introduced in numerical modeling of high electron mobility transistors (HEMT's). In comparison with conventionally used analytical drift velocity expressions such as two-piece linear model and silicon-like simple model, cutoff frequency characteristics can be explained without using excessively large saturation velocity values lacking in physical meaning. The calculated electric field near the source under the gate is a few kilovolts per centimeter. It is concluded that low-field drift velocity characteristics are very important in estimating the device performance, and must be based upon accurate physics.     

Power limitations in BARITT devices

The results of a large-signal numerical simulation of the BARITT device using a single-carrier model are given to illustrate the basic transport mechanisms involved in the device. The results of existing first-order small- and large-signal analyses are compared with those computed numerically. Space-charge-limited thermionic injection, spatial velocity modulation, carrier diffusion, premature carrier collection, large-signal electric field depression and the low-field drift region are found to account for the large reduction of power and efficiency of the BARITT device. The maximum power and efficiency of Si uniformly doped and Read structures are found to be approximately 300 W/cm² and 3%, respectively. The effects of doping profile and material parameters are found to involve a trade off of large-signal handling capability and frequency of operation on one hand vs the negative conductance and thus the Q factor of BARITT devices on the other hand. The excessively high electron mobility in GaAs is found to be detrimental to device operation.     

一种SOI nLDMOS的开态特性设计

介绍了一种用于高压电平位移电路的SOInLDMOS器件结构,对其漂移区、sink区、bufferN场板等结构参数进行器件工艺联合仿真,并分析相关结构参数对开态特性的影响,用于指导高压MOS器件尤其是基于SOI的横向MOS器件的开态特性设计。采用优化的参数,器件关态击穿电压为296V,开态击穿电压为265V,比导通电阻为60．9mΩ·cm^2。     

阶梯浅沟槽隔离结构LDMOS耐压机理的研究

提出了一种具有阶梯浅沟槽隔离结构的LDMOS.阶梯浅沟槽结构增加了漂移区的有效长度,改善了表面电场及电流的分布,从而提高了器件的击穿电压.借助器件模拟软件Silvaco对沟槽深度、栅长及掺杂浓度等工艺参数进行了优化设计.结果表明,在保证器件面积不变的条件下,新结构较单层浅沟槽隔离结构LDMOS击穿电压提升36%以上,而导通电阻降低14%.     

SJ/RESURF LDMOST

A monolithic lateral double diffused MOSFET (LDMOST) based on the super junction (SJ) concept is proposed to significantly improve the device's on-state and off-state characteristics. The device structure features a split drift region made of two parts: 1) an SJ structure that extends over most of the drift region and 2) a terminating reduced surface field (RESURF) region occupying a portion of the drift region adjacent to the n/sup +/ drain. This structure suppresses substrate-assisted depletion effects and ensures complete depletion and near uniform electric field distribution over the entire drift region. In the on-state, the high conductivity of the SJ drift region results in a significant improvement in the specific on-resistance for a given breakdown voltage (BV) and, hence, a reduction in the on-state, switching, and gate-drive losses. In the off-state, the RESURF region, located near the n/sup +/ drain, effectively neutralizes the substrate-assisted depletion effects and results in high BV.     

光生伏打效应与光折变光栅的建立

带输运模型是目前被广泛接受的光折变理论.该模型以扩散机制为主.在某些情况下加上两个修正,即有外场时的漂移机制和光生伏打效应.其中光生伏打效应被考虑为等效于外加电场.而且常常被忽略了.作者认为光生伏打效应应当总被看作与扩散相并列的光折变机制,而且在铁电晶体.如LiNbO_3.中.光生伏打效应常常超过扩散而成为光折变过程的主要机制.文中将已有的光生伏打效应的唯像理论加以扩展,对产生光折变光栅的过程给出了较全面的分析.     

埋层低掺杂漏SOI高压器件的击穿电压

提出一种具有埋层低掺杂漏(BLD)SOI高压器件新结构。其机理是埋层附加电场调制耐压层电场,使漂移区电荷共享效应增强,降低沟道边缘电场,在漂移区中部产生新的电场峰。埋层电中性作用增加漂移区优化掺杂浓度,导通电阻降低;低掺杂漏区在漏极附近形成缓冲层,改善漏极击穿特性。借助二维半导体仿真器MEDICI,研究漂移区浓度和厚度对击穿电压的影响,获得改善击穿电压和导通电阻折中关系的途径。在器件参数优化理论的指导下,成功研制了700V的SOI高压器件。结果表明:BLD SOI结构击穿电压由均匀漂移区器件的204V提高到275V,比导通电阻下降25%。     

RESURF LDMOSFET with a trench for SOI power integrated circuits

A new structure of RESURF LDMOSFET is proposed, based on silicon-on-insulator, to improve the characteristics of the breakdown voltage and the specific on-resistance, where a trench is applied under the gate in the drift region. A trench is used to reduce the electric field under the gate when the concentration of the drift region is high, thereby increasing the breakdown voltage and reducing the specific on-resistance. Detailed numerical simulations demonstrate the characteristics of this device and indicate an enhancement on the performance of the breakdown voltage and the specific on-resistance in comparison with an optimal conventional device with LOCOS under the gate.     

A two-dimensional analysis of indium phosphide junction field effect transistors with long and short channels

A two-dimensional analysis of indium phosphide junction field effect transistors with long and short gates is presented. The two devices are shown to have properties similar to those of gallium arsenide JFETs. The short gate device has a negative resistance region at low drain voltages which is absent in the long gate device. The negative resistance region is determined by the distribution of the drift velocity along the conducting channel, and the resulting distribution of the electron charge. A field dependent mobility is used, and its effect on current saturation is discussed. The electrostatic charge distribution and electric field distribution are calculated for both devices, and are shown in graphic form.     

Carrier recombination influence on the SOIMOSFET floating bodyeffect

The carrier recombination influence on the floating body effect for fully depleted n-channel SOIMOSFET was analyzed by device simulation. It was found that the hole diffusion to the source electrode is negligibly small and that the surface recombination for the generated hole dominates the hole extinction, at the subthreshold region. Based on the simulated result, an analytical model on the hole concentration is proposed, in which the recombination velocity is explicitly included. The model explains the hole concentration behavior that is responsible for the floating body effect for the fully depleted SOIMOSFET