Thin-film silicon-on-sapphire deep depletion MOS transistors

This paper describes thin-film MOS transistors in which the entire silicon film forms the conducting channel, not just the surface inversion layer. Single crystal silicon which is epitaxially deposited on sapphire to a thickness of 0.5 to 2.0 microns forms the channel of the field-effect transistor. The oxidations for the channel oxide were done in both steam and dry oxygen ambients resulting in very little oxide charge (0-2 × 10¹¹cm^-2) on both [111] and [100] silicon orientations. No orientation dependence was observed. The absence of an active substrate leads to device characteristics that are significantly different from MOS transistors made on thick silicon. Analysis of the output characteristics and the C-V curve of these devices enables one to study the characteristics of the silicon film and its two surfaces. It is shown that the silicon-sapphire interface region has similar characteristics to the silicon-silicon dioxide interface region in its tendency to support donor sites after heating in hydrogen. To facilitate analysis of the C-V curve, two interesting relations are derived: specifically, the slope of the curve is related to the doping density of the silicon, and the 0.95 level on the normalized curve is shown to be offset approximately one volt from flat-band potential regardless of oxide thickness or doping density, provided these parameters set the normalized flat-band capacitance significantly below 0.95. The use of thin high resistivity p-type films allows one to fabricate p-type enhancement transistors which exhibit a low threshold voltage due to the fact that the silicon surface does not have to be inverted before the channel conducts. Finally, partial-gate deep depletion transistors are examined and it is shown that a substantial increase in drain breakdown voltage may be obtained with thiss geometry.     

On the origin of leakage currents in silicon-on-sapphire MOS transistors

n-channel n-p-n metal-oxide-semiconductor transistors (MOST's), fabricated in thin films of silicon-on-sapphire, exhibit values of source-to-drain leakage currents (IL)which vary from wafer to wafer, typicaily from 10^-11to 10^-7A/mil of channel width. Conversely, p-channel (p-n-p) devices exhibit low leakage current values in the range of 10^-11∼ 10^-10A/mil of channel width, consistent from wafer to Wafer. A model of a high concentration of donorlike states in the silicon in the vicinity of the Al2O3-Si interface creating a back-surface Conductive channel is proposed to account for both the inconsistently high n-channel and consistently low p-channel leakage current values. Experimental measurements of IL, which support the general conclusions of the model, are presented. ILis shown to be a strong function of a) the annealing temperature of the sapphire substrate prior to film growth, b) the silicon-film growth rate, c) the impurity concentration profile in the channel region, and d) the device geometry. These measurements show that the dominant factor controlling the overall magnitude of ILis the state of the Al2O3-Si interface immediately prior to silicon-film growth. A set of silicon-film growth conditions and device processing steps is outlined which achieve consistent n- and p-channel leakage current values of less than 10^-9A/mil of gate width.     

Low frequency noise in junction field effect transistors

Low frequency noise in four-terminal JFETs has been measured as a function of substrate (second gate) bias with temperature and drain current as additional variables. Sharp peaks of noise have been observed at some values of gate bias. The mechanism of low frequency noise caused by Schockley-Read-Hall (SRH) centres and the significance of charge capture processes in and near the channel are discussed. The experimental results show that most of the excess low frequency noise is caused by SRH centres situated in the transition region between the channel and the fully depleted region of the gate-channel junctions. In JFETs with gate-widths of 1000 μm or less the noise caused by unit electronic charge fluctuations at invidual SRH centres can be readily observed.     

Low frequency noise spectroscopy in MOS and Bipolar devices

We present the basic principles and the state of the art of the noise modeling and characterization for MOS and Bipolar devices. We give examples of usual applications of noise spectroscopy for these devices: determination of noise mechanisms, interface states density measurements, individual traps characterization in MOSFETs, localization of noise sources and series resistances extraction in BJT's.     

Accurate noise measurements on transistors

This paper is concerned with a method of noise measurement which permits improved accuracy by circumventing some of the problems of the usual comparison techniques. Results are presented of measurements of Ieqand Rnshowing good agreement between theory and experiment. It is suggested that noise measurements may be a very satisfactory method of determining the effective base resistance for inhomogeneous structures. The theoretical representation of the noise sources, including the effect of generation-recombination in the emitter-base region, is summarized in the appendix.     

Improved analysis of low frequency noise in dynamic threshold MOS/SOI transistors

In this paper, low-frequency noise (LFN) in N- and P-channel dynamic-threshold (DT) MOSFETs on Unibond substrate (SOI) is thoroughly investigated and, especially, an improved formulation of classical McWhorter’s noise model is proposed. In order to confirm our approach, an experimental comparison between body tied and DTMOS on SOI substrate has been achieved in terms of LFN behaviour. Furthermore, two different types of DTMOS transistors have been used: with and without current limiter. The LFN in DTMOS is analysed in ohmic and saturation regimes and the impact of the use of a current limiter (clamping transistor) is thoroughly analysed. An explanation based on floating body effect inducing excess noise is also proposed.     

Low-frequency noise in depletion-mode SIMOX MOS transistors

Low-frequency noise measurements in depletion-mode SIMOX MOSFETs are reported. A simple model provides a reliable interpretation of the low-frequency noise in multi-interface depletion-mode transistors. An experimental procedure to separate noise contributions of front and back interfaces from noise due to bulk carrier fluctuations is described. The noises generated in the thin Si film and at the two Si-SiO₂ interfaces can be identified and characterized independently in terms of bulk properties and interface trap densities. Single-level traps at the back interface and defects in the volume are detected in high-temperature annealed materials     

White noise in MOS transistors and resistors

The theoretical and experimental results for white noise in the low-power subthreshold region of operation of an MOS transistor are discussed. It is shown that the measurements are consistent with the theoretical predictions. Measurements of noise in photoreceptors-circuits containing a photodiode and an MOS transistor-that are consistent with theory are reported. The photoreceptor noise measurements illustrate the intimate connection of the equipartition theorem of statistical mechanics with noise calculations     

Low frequency conductance and capacitance measurements on MOS capacitors in weak inversion

The analysis of capacitance and conductance measurements as a function of frequency on MOS capacitors biased in depletion is well understood. However, little information is available on such measurements for capacitors biased in weak inversion. In this work it is shown that approximations to the theory of surface state response lead to a very simple technique for obtaining the density of fast surface states as a function of energy in the weak inversion region. Low frequency conductance and capacitance measurements have been made on a number of MOS samples and analysis of the data yields N_ss as a function of energy in excellent agreement with results obtained by other techniques. As expected, experimental results show that N_ss in weak inversion depends strongly on the annealing treatment given the MOS samples. However, annealing is found to have a much greater effect in reducing N_ss in weak inversion than at midgap. It is also shown that the depletion layer generation current in the majority of samples measured is due to surface state generation rather than bulk generation.     

Scanning electron microscope measurements on short channel MOS transistors

Several methods are discussed for measurement of PN junction shapes and channel field conditions in short (≈1 μm gate lengths) MOS transistors. A special test structure for short channel MOS transistor measurements with a scanning electron microscope (SEM) is presented. Secondary electron measurements on lased scribed and angle lapped and stained PN junctions are discussed. Methods for sectional imaging of electrically active, cleaved transistors using electron-beam-induced current (EBIC) are presented. An approximate quantitative model of the EBIC imaging process is presented which allows the calculation of current in a MOS transistor. Using this model the current is shown to be dominated by electric field effects in the depletion region of the transistor.     

Direct capacitance measurements of small geometry MOS transistors

Methods for measuring the intrinsic capacitances of small geometry MOS transistors are described. The influence of short- and narrow-channel effects on the capacitance characteristics of MOS transistors is evaluated. The results are compared with long-channel devices. It is shown that the presented capacitance methods can be used to study the physics of short-channel transistors.     

1/f noise in n-channel silicon-gate MOS transistors

It is found that equivalent gate noise power for l/f noise in n-channel silicon-gate MOS transistors at near zero drain voltage at room temperature is empirically described by two noise terms, which vary asK_{1}(q/C_{ox}) (V_{G} -V_{T})/f and K_{2}(q/C_{ox})^{2}/f, where V_{G}is gate voltage, VTis threshold Voltage, and Coxis gate-oxide capacitance per unit area. Unification of carrier-density fluctuation (McWhorter's model)and mobility fluctuation (Hooge's model) can account for the experimental data. The comparison between the theory and experiment shows that the carrier fluctuation term K2is proportional to oxide-trap density at Fermi-level. The mobility fluctuation term K1is correlated to K2, being proportional toradic K_{2}. The origin of this correlation is yet to be clarified.     

Hole-induced 1/f noise increase in MOS transistors

This paper presents experimental evidence for hole-generated 1/f noise traps in gate oxides near the MOS interface. To clarify the microscopic nature of noise traps, 1/f noise is measured in Si MOS transistors in which carriers are intentionally injected into the gate oxides. It was found that 1/f noise increases more rapidly after drain avalanche hot-carrier injection than after channel hot-electron injection. A rapid noise increase is also observed after X-ray irradiation. These results show that the increase in 1/f noise is closely related to holes. We propose a model in which the reaction between holes and oxygen vacancies near the interface creates noise traps, i.e., E' centers and fixed positive charges     

White noise of MOS transistors operating in weak inversion

A theory is given for the thermal noise of MOS transistors in the weak inversion regime. For MOS transistors with low surface-state density, the relation for the thermal noise in saturation is shown to be the same as a shot noise relation. The theory is compared with measurements and the origin of the white noise in MOST's operating in weak inversion is discussed.     

Low frequency noise in SiGe-base heterojunction bipolar transistors and SiGe-channel metal oxide semiconductor field effect transistors

We show that low frequency noise (LFN) in SiGe-base heterojunction bipolar transistors and SiGe-channel pMOSFETs may be made significantly lower than that in their all-Si counterparts and indicate how this can be done. Optimization of LFN in SiGe channel pMOSFETs follows from a calculation involving a novel analytical model, which accounts for both static and LFN characteristics of SiGe-channel devices.     

Depletion V-groove MOS (VMOS) power transistors

A new depletion MOS transistor is proposed. The structure uses anisotropic etching to define the channel in an n/p epitaxial silicon slice. A simple planar model is developed to explain the characteristics of the devices and is verified by measurements on experimental structures.Power devices are fabricated to illustrate the power capability of the structure. Parameters measured for this structure include: junction temperature, d.c. power dissipation, distortion, ac output power, efficiency. The devices were found to be capable of delivering up to 12W with a cutoff frequency of 80 MHz.     

A reliable approach to charge-pumping measurements in MOS transistors

A new and accurate approach to charge-pumping measurements for the determination of the Si-SiO2interface state density directly on MOS transistors is presented. By a careful analysis of the different processes of emission of electrons towards the conduction band and of holes towards the valence band, depending on the charge state of the interface, all the previously ill-understood phenomena can be explained and the deviations from the simple charge-pumping theory can be accounted for. The presence of a geometric component in some transistor configurations is illustrated and the influence of trapping time constants is discussed. Furthermore, based on this insight, a new technique is developed for the determination of the energy distribution of interface states in small-area transistors, without requiring the knowledge of the surface potential dependence on gate voltage.     

Surface states and 1/f noise in MOS transistors

Surface-state density in n-channel MOS transistors operating in the inversion mode has been determined from the channel conductance and related to 1/fnoise in these devices. It has been found that the noise is proportional to the surface-state density at the Fermi level. The surface orientation and temperature affect the noise output only indirectly, through their influence on the surface-state density and the position of the Fermi level at the surface.     

Subthreshold 1/f noise measurements in MOS transistors aimed at optimizing focal plane array signal processing

In focal plane signal processing applications it is imperative to minimize noise in the associated input circuit. The latter usually consists of MOS transistor preamplifiers and multiplexers. This paper concentrates on the 1/f noise generation in NMOS input signal processing circuits. A 1/f noise model for the subthreshold region is derived and correlated with 1/f noise measurements of NMOS transistors. This model is unique in that slow and fast surface states can be modeled separately. Typical values for slow and fast surface state densities from measured data and model correlation were found to be N _{ss s}=1×10¹¹ cm^-2 eV^-1 and N _{ss f}=3×10¹⁰ cm^-2 eV^-1, respectively. The order of magnitude of these results correlate well with published data [1–3]. The importance of these results is that process changes to minimize the 1/f noise can be monitored and the required minimization of 1/f noise for focal plane signal processing circuits can be achieved.