埋沟CCD器件电荷处理容量的二维数值模拟

借助于二维器件模拟软件PISCES-IIB,通过在某相CCD电极下的耗尽区注入数量可控的电子电荷,对埋沟CCD器件电荷容量进行了定量分析。采用此方法对一种沟道宽度为7μm的CCD信道电荷容量进行了瞬态模拟,对不同结深、不同沟道掺杂浓度对CCD电荷容量的影响进行了讨论。得到了此结构工艺参数的初步优化结果,即CCD沟道表面掺杂浓度为结深为1 μm时,埋沟CCD的电荷容量可达文章提出的方法适用于其他CCD单元结构电荷容量的模拟。     

Proton-bombardment isolated GaAlAs/GaAs charge-coupled devices

Proton bombardment is used for the first time as a channel isolation technique to fabricate buried channel homojunction charge-coupled devices (c.c.d.s) of n-GaAs channel on GaAs substrate and heterojunction c.c.d.s of n-Ga1?xAlxAs on GaAs. The c.c.d. structure is a Schottky-barrier gate buried channel 3-phase device with 30 transfer gates. The channel-stop bombardment was carried out at room temperature with an energy of 200 keV and a total dose of 1015/cm2. The c.c.d.s were tested with electrical charge injection and direct readout. The charge transfer efficiency was found to be greater than 0.999 per transfer for both GaAs and GaAlAs. The proton-bombardment isolated devices were compared with similar devices using mesa isolation and were found to perform similarly.     

New dynamic RAM Cell for VLSI memories

A novel high-alpha-particle-immunity and high-density dynamic RAM cell with readout signal gain is proposed. The cell is composed of a MOSFET for charge transfer, a MOS capacitor for charge storage and a junction FET (JFET) with buried channel under the MOS capacitor. The buried channel is dynamically switched according to whether there is charge-storage or not. The cell has extremely small collection efficiency for charges generated by alpha-particles, and allows a large amount of leakage charges due to its peculiar structure. Thus, it can achieve high packing density.     

Super junction LDMOS with enhanced dielectric layer electric field for high breakdown voltage

The lateral super junction(SJ) power devices suffer the substrate-assisted depletion(SAD) effect,which breaks the charge balance of SJ resulting in the low breakdown voltage(BV).A solution based on enhancing the electric field of the dielectric buried layer is investigated for improving the BV of super junction LDMOSFET (SJ-LDMOS).High density interface charges enhance the electric field in the buried oxide(BOX) layer to increase the block voltage of BOX,which suppresses the SAD effect to achieve the charge balance of SJ.In order to obtain the linear enhancement of electric field,SOI SJ-LDMOS with trenched BOX is presented.Because the trenched BOX self-adaptively collects holes according to the variable electric field strength,the approximate linear charge distribution is formed on the surface of the BOX to enhance the electric field according to the need.As a result,the charge balance between N and P pillars of SJ is achieved,which improves the BV of SJ-LDMOS to close that of the idea SJ structure.     

Optimum scaling of buried-channel CCD's

The maximum charge packet size in a two-phase charge-coupled device (CCD) is limited by many constraints relating to the transfer efficiency requirement and control circuit limitations. The constraints are quantified and an optimization routine is developed for designing CCD's with maximum charge capacity per unit area under these constraints. The optimum charge capacity for scaled down CCD's is calculated and it is shown that the normal buried channel cannot be designed to have adequate charge capacity at small geometries. A novel low-voltage buried-channel structure is introduced which uses a shallow p-type surface implant to minimize surface trapping and increases the charge capacity per unit area 2.4× compared to the normal buried channel. The optimum charge packet size at ∼1-µm geometry for these CCD structures, based on these calculations, is shown to be inadequate for VLSI dynamic memory applications.     

A theoretical and experimental analysis of the buried-source VMOS dynamic RAM cell

The buried-source dynamic RAM cell combines a VMOS transistor (VMOST) and a buried junction capacitor to make a one-transistor cell (1TC) providing large storage capacitance, long charge retention, and high density. The threshold voltage, breakdown voltage, and weak inversion current for the forward and reverse modes of operation of the VMOST and the junction capacitance are experimentally related to the nonuniform doping profile of the channel. Equations are developed for the VMOST short-channel threshold voltage and storage capacity of the cell. The charge capacity (per unit of cell area) of the buried-source cell is calculated to be 2.5 times that of the conventional 1TC cell. The cell charge retention time was measured at more than 1 s at 100°C, proving operation of the device as a dynamic memory element. The technology is capable of producing an 80-µm²cell using 4-µm minimum features, no cell contacts, and a single level of interconnect.     

Bulk charge effects in VLSI MOSFET's

An analysis of the relative magnitudes of the bulk charge for three MOSFET structures suitable for VLSI devices, such as NMOS (normal), VMOS (V slot) and UMOS (U slot), is carried out. It is shown that even for the same channel design (i.e. channel length, doping, source/drain junction depth, and oxide thickness), the amount of bulk charge and hence the threshold voltage can be significantly different for the three structures. This effect becomes more important with decreasing channel length, and increasing source to substrate bias. Further, for a given channel length, the bulk charge and hence the threshold voltage of an NMOS decreases with increasing source/drain junction depth. However, for the VMOS and UMOS structures, the bulk charge as well as the threshold voltage do not depend on the junction depth of the source/drain diffusion. An expression is also derived for the bulk charge of UMOS transistors valid for both short and long channels.     

Relationship between short channel behavior and long term stability of n-channel enhancement and depletion MOSFETs

Enhancement and depletion mode n-channel MOSFETs are investigated with respect to short channel effects and hot carrier related instabilities. It is found that subthreshold characteristics of normally off type devices are improved by additional deep channel implants. However, long term stability of enhancement mode devices decreases with the deep channel implant dose. A similar behavior is observed for depletion mode devices. Significant improvement in device stability can be realized using buried channel conduction. However, short channel effects attain untolerable magnitudes in devices with deep buried channels. It is concluded in this paper, that the conventional approaches used for optimization of long term stability and d.c. characteristics of small size MOSFETs are technologically incompatible. In the outlook, device design requirements are discussed to circumvent these problems.     

Analysis of enhanced hot-carrier effects in scaled flash memorydevices

In this paper, we analyze the impact of both junction scaling and channel length scaling on hot-carrier reliability of Flash memory devices with the help of a newly developed charge pumping technique. Lateral profiles of dopant concentration and erase-induced damage near both graded and abrupt junctions were obtained from charge pumping measurements. We found that more erase-induced damage is spread into the channel if the junction Is more abrupt. Further current-voltage (I-V) measurements and write/erase cycling experiments demonstrate that the effect of erase-induced damage on V_t becomes more severe when channel length is scaled down. To scale down Flash memory devices without sacrificing reliability, we suggest to either keep the source junction sufficiently graded or reduce the erase source bias     

The ultimate limits of CCD performance imposed by hot electron effects

It is shown that the ultimate speed of charge transfer in silicon charge coupled devices is limited by impact ionization in the silicon and the saturation of the drift velocity. The charge transfer speed of buried channel devices (BCCDs) decreases linearly with the separation, L, between centers of neighboring gates for L ≤ 10 μM. The decrease of the transfer speed of surface channel devices (SCCDs) is linear only for L ≤ 2 μm but is much faster for L > 2 μm. For L ≤ 2 μm, the ultimate charge transfer times of both SCCDs and BCCDs are about the same, corresponding to clock frequencies in the GHz range. Charge coupled devices made in small-energy gap compound semiconductors are also discussed. In spite of the higher carrier mobility, devices in these materials can not be operated at clock frequency above the KHz-MHz range due to interband impact generation of electron-hole pairs in the high electric field.     

具有增强介质层电场的SJ-LDMOS

横向超结功率器件遭受衬底辅助耗尽效应,这破坏了超结的电荷平衡,降低了器件的耐压。本文研究了一种基于增强介质层电场的解决方法,以提高横向超结器件（SJ-LDMOS）的耐压。通过高密度的界面电荷增强埋氧层（BOX）的电场从而提高埋氧层的耐压,这可以削弱纵向电场对超结的影响,消除衬底辅助耗尽效应,促进超结电荷平衡。为了获得理想的线性电场增强效果,一种具有槽形埋氧层的超结器件（TBOX SJ-LDMOS）被提出。槽形埋氧层能根据纵向电场的大小自适应地收集空穴,在埋氧层表面形成近似线性的电荷分布,这促进了超结的电荷平衡,提高了SJ-LDMOS器件的耐压,并使其接近理想超结的耐压值。     

Threshold voltage reduction model for buried channel PMOSFETs using quasi-2-D Poisson equation

A quasi-two-dimensional (2-D) threshold voltage reduction model for buried channel pMOSFETs is derived. In order to account for the coexistence of isoand anisotype junctions in a buried channel structure, we have incorporated charge sharing effect in the quasi-2-D Poisson model. The proposed model correctly predicts the effects of drain bias (V/sub DS/), counter doping layer thickness (x/sub CD/), counter doping concentration (N/sub CD/), substrate doping concentration (N/sub sub/) and source/drain junction depth (x/sub j/), and the new model performs satisfactorily in the sub-0.1 /spl mu/m regime. By using the proposed model on the threshold voltage reduction and subthreshold swing, we have obtained the process windows of the counter doping thickness and the substrate concentration. These process windows are very useful for predicting the scaling limit of the buried channel pMOSFET with known process conditions or systematic design of the buried channel pMOSFET.     

Determination of buried channel parameters from IV and CV measurements

A simple, direct method is described for the extraction of the minimum carrier potential vs charge packet size in a buried channel CCD. Also obtainable from this technique is a direct measurement of the location of the top of the charge packet with respect to the silicon surface. Close correlation is found between the results obtained from this technique and the predictions of the step junction depletion layer approximation.     

Reduction of fixed loss in buried-channel CCD's operating at 77 K

The authors describe studies on charge transfer loss in buried-channel charge-coupled devices (BCCD's) at 77 K. Experiments suggest that the fixed loss occurs mostly during the last transfer from phase clock to output diffusion. It is shown that this loss can be reduced by reducing the doping concentration in the buried channel and introducing a potential step in the middle of the storage well along the charge-flow direction. Transfer inefficiencies as low as 8.6×10 ^-5 without fat zero at 3-MHz clock rate are observed at 77 K     

电荷耦合器件辐射效应理论分析与模拟试验方法研究

分析了CCD电离效应和位移损伤机理,建立了一种国产埋沟CCD器件物理模型,实现了CCD信号电荷动态转移过程的数值模拟,计算了1MeV、14MeV中子引起的CCD电荷转移效率的变化规律.建立了线阵CCD辐照效应离线测量系统,实现了CCD辐射敏感参数测试.利用Co-60γ源和反应堆脉冲中子,开展了商用器件总剂量和中子位移损伤效应模拟试验,在不同辐照条件下,给出了暗电流信号、饱和电压信号、电荷转移效率以及像元不均匀性的变化情况.     

C-V and C-t analysis of buried oxide layers formed by high-dose oxygen implantation

For silicon-on-insulator devices with very thin active layers, the quality of the buried oxide layer and its interface with the top silicon layer can significantly affect device performance. This study focuses on the characterization of buried oxide layers formed by high-dose oxygen implantation into Si wafers. Capacitance-voltage (C-V) and capac-itance-time (C-t) measurements were performed on the epilayer/buried oxide/substrate capacitors. From high frequency C-V measurements, data on fixed oxide charge, inter-face traps, and donor densities were obtained for both buried oxide interfaces, as well as the thickness of the buried oxide layer. From C-t measurements, minority carrier generation lifetimes were calculated for thin depletion regions on both sides of the buried oxide. The data is correlated to changes in implanted dose, anneal temperature, and anneal time.     

Maximum free charge in two-phase surface charge-coupled devices

The maximum charge that can be stored and transferred efficiently in a surface CCD is significantly larger than in the buried channel device. However, whereas in the three-phase surface CCD the maximum charge depends primarily on clock voltage differences, in the two-phase device it depends on parameters which are fixed during fabrication. It is important therefore in the design of two-phase structures, to have a detailed understanding of how this charge depends on device parameters. The implanted barrier (IB) and stepped oxide (SO) structures are analysed by comparing the surface potentials obtained from one-dimensional models of the appropriate regions and a number of contrasting dependences found between the two types of CCD. A further limit to the maximum free charge for both devices is set when the field at the oxide-semi-conductor interface (and normal to it) approaches the breakdown field for Silicon. The presence of the implanted region in the IB. CCD gives rise to a radically different field limitation for the structure.     

Numerical analysis of silicon-on-lnsulator short channel effects in a radiation environment

Radiation-induced charge build-up in the buried oxide (BOX) of SOI MOSFETs affects device performance through threshold voltage shifts of the back channel. This charge build-up is related to the electric field in the BOX during irradiation. In this paper, we report on the application of a numerical model for the potential distribution in a semiconductor device to the task of determining the electric field in the BOX. This electric field distribution is then combined with a model for charge accumulation as a function of electric field during irradiation to predict the threshold voltage shifts in the back channel of SOI MOSFET devices as a function of channel length. For the device design analyzed here, this model agrees with available experimental data and predicts an increase in back channel threshold shift as the channel length enters the sub-micron regime.     

Shallow buried channel gated BJT on TFSOI substrate

The gated BJT structure is inherently suitable for SOI BiCMOS technology. However, being a surface channel device, it suffers higher noise and degraded carrier transport. In this study, a novel shallow buried channel design on TFSOI is proposed. Devices with various geometries have been fabricated with a simple CMOS-compatible process. These devices have low turn-on voltage, ideal BJT I-V characteristics with current gain higher than 1000, and a maximum transconductance of 290 mS/mm for a 0.5 μm channel length and 15 nm gate oxide. Careful measurements show that an order of magnitude improvement in noise performance can be expected from the buried channel operation. These devices are suitable for various BiCMOS applications     

Degradation induced by TID radiation and hot-carrier stress in 130-nm short channel PDSOI NMOSFETs

Hot-carrier reliability for devices operating in radiation environment must be considered. In this paper, we investigate how total ionizing dose impacts the hot-carrier reliability of partially-depleted SOI I/O NMOSFETs, highlighting the effect of buried oxide. Firstly, radiation-induced damage on short channel SOI devices with 100 nm thick Si film was investigated. After low total dose irradiation, incomplete fully-depleted state has been formed due to the non-uniformly distributed positive charges in the buried oxide. Furthermore, as the dominated factor of hot-carrier injection, the body current reduces after irradiation. Subsequently, the irradiated SOI devices were subjected to hot-carrier stress for 9000-s long time. Compared with unirradiated devices, the irradiated samples display enhanced hot-carrier degradation. We attribute this phenomenon to that radiation lowers the barrier for hot-carrier injection. Therefore, in order to ensure the reliability of SOI devices operating in harsh radiation environments, SOI devices with higher quality or corresponding hardness design should be taken.