1V高线性度2.4GHz CMOS低噪声放大器

讨论了低噪声放大器(LNA)在低电压、低功耗条件下的噪声优化及线性度提高技术.使用Chartered 0.25μm RF CMOS 工艺设计一个低电压折叠式共源共栅LNA.后仿真结果表明在1V电源下,2.36GHz处的噪声系数NF仅有1.32dB,正向增益S21为14.27dB,反射参数S11、S12、S22分别为 -20.65dB、-30.27dB、-24dB,1dB压缩点为-13.0dBm,三阶交调点IIP3为-0.06dBm,消耗的电流为8.19mA.     

3.1～10.6 GHz CMOS超宽带低噪声放大器设计

本文给出了一个低电压、低功耗增益连续可调CMOS超宽带低噪声放大器(Ultra-wideband Low Noise Amplifier,UWB LNA)设计。在0.85V工作电压下放大器的直流功耗约为10mW。在3.1～10.6GHz的超宽带频段内,增益S21为14±0.4dB,且随控制电压VC连续可调。输入、输出阻抗匹配S11、S22均低于-10dB,噪声系数(NF)最小值为3.3dB。设计采用TSMC 0.18μm RF CMOS工艺完成。     

低压中和化CMOS差分低噪声放大器设计

以设计低电压LNA电路为目的,提出了一种采用关态MOSFET中和共源放大器输入级栅漏寄生电容Cgd的CMOS差分低噪声放大器结构.基于该技术,采用0.35μmCMOS工艺设计了一种工作在5.8GHz的低噪声放大器.结果表明,在考虑了各种寄生效应的情况下,该低噪声放大器可以在0.75V的电源电压下工作,其功耗仅为2.45mW.在5.8GHz工作频率下:该放大器的噪声系数为2.9dB,正向增益S21为5.8dB,反向隔离度S12为-30dB,S11为-13.5dB.     

基于CMOS工艺的一种低功耗高增益低噪声放大器

采用0．18μm CMOS工艺,两级共源结构实现了低功耗高增益的低噪声放大器（LNA）设计。共源结构的级联采用电流共享技术,从而达到低功耗的目的。电路的输入端采用源极电感负反馈实现50欧姆阻抗匹配。同时两级共源电路之间通过串联谐振相级联。该LNA工作在5．2GHz,1.8V电源电压,能提供20dB的增益（S21为20dB）,而噪声系数为1．9dB,输入匹配较好,S11为-32dB。     

L波段0.9 mW CMOS LNA的分析与设计

给出了一种采用Γ型输入匹配网络的源简并共源低噪声放大器电路结构,分析了在低功耗情况下,高频寄生效应对低噪声放大器(LNA)输入阻抗及噪声特性的影响,并采用此结构设计了一款工作于L渡段的低功耗低噪声放大器.采用CMOS 0.18μm工艺,设计了完整的ESD保护电路,并进行了QFN封装.测试结果表明.在1.57 GHz工作频率下,该低噪声放大器的输入回波损耗小于-30 dB,输出回波损耗小于-14 dB,增益为15.5 dB,噪声系数(NF)为2.4 dB,输入三阶交调点(IIP3)约为-8 dBm.当工作电压为1.5 V时,功耗仅为0.9 mW.     

一种应用于无线通信的低电压低功耗Σ-D调制器的设计

文章首先分析了低电压对于低功耗CMOSΣ-"调制器设计提出的挑战,使用了自顶向下的设计策略,利用Hspice和Simulink对开关电容放大器和开关电路非理想特性建模,通过Matlab优化低功耗结构的运算放大器电路参数,最后给出了系统仿真结果。仿真结果显示,使用0.18#m2p6mCMOS工艺设计的Σ-"调制器在1.5V低电源电压条件下,信号带宽为200KHz,峰值信噪比达到93.5dB,动态范围为96.3dB,满足了GSM/PCS1800/DCS1900等无线应用的要求。     

用于物联网双频段低功耗CMOS低噪声放大器设计

设计一种用于物联网双频段的低功耗CMOS低噪声放大器(LNA).为了满足双频段和高增益,设计使用共源共栅(Cascode)结构并利用TSMC 0.18um工艺库进行仿真分析.仿真结果表明,在780MHz和433MHz中心频率下,电路的S11均小于-20dB和S21均大于20dB,并且具有好的稳定性.     

低功耗单端输入差分输出低噪声放大器

该文设计了应用于无线局域网2.4GHz低噪声放大器(LNA),采用了SMIC0.18μm CMOS工艺技术和单端输入差分输出的电路结构.电路同时采用了双支路的电流复用技术,实现了低功耗、低噪声和高增益的性能;通过在输出级增加一级共栅级放大电路,有效地增加了电路的对称性;共源支路串联电感,解决了差分信号相位偏差问题.仿真结果表明,设计的LNA的噪声系数为1.76dB,增益为20.9dB,在1.8V电源电压下,功耗为8.5mW.     

用于无线传感网络低功耗亚阈值CMOS低噪声放大器设计

设计一种工作在亚阈值区的低功耗CMOS低噪声放大器(LNA),用于无线传感网络.为了满足低功耗和高增益,设计使用共源共栅(cascode)结构并利用UMC 65nm工艺库进行仿真分析.仿真结果表明,在780MHz中心频率下,电路的增益大约34 dB,功耗仅为55μW,电源电压为1.2V.     

低电压低功耗带通Sigma Delta调制器的设计

本文设计了一种符合双标准接收机要求的一位四阶带通调制器.为了实现低电压低功耗设计的要求,改进了调制器结构,并进行了从系统到电路模块的优化.采用0.35μm CMOS工艺,Hspice和Matlab联合模拟表明:在2V电源电压下,调制器在GSM和WCDMA系统中的DR分别为86dB和36dB,而功耗仅为10.5mW和12mW.     

Low-power W-band CPWG InAs/AlSb HEMT low-noise amplifier

We present the development of a low-power W-band low-noise amplifier (LNA) designed in a 200-nm InAs/AlSb high electron mobility transistor (HEMT) technology fabricated on a 50-/spl mu/m GaAs substrate. A single-stage coplanar waveguide with ground (CPWG) LNA is described. The LNA exhibits a noise figure of 2.5 dB and an associated gain of 5.6 dB at 90 GHz while consuming 2.0 mW of total dc power. This is, to the best of our knowledge, the lowest reported noise figure for an InAs/AlSb HEMT LNA at 90 GHz. Biased for maximum gain, the single-stage amplifier presents 6.7-dB gain and an output 1-dB gain compression point (P1dB) of -6.7dBm at 90 GHz. The amplifier provides broad-band gain, greater than 5dB over the entire W-band.     

A 5-GHz CMOS wireless LAN receiver front end

This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-μm CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm     

A 0.6-V Low Power UWB CMOS LNA

This paper presents the design of a low-power ultra-wideband low noise amplifier in 0.18-mum CMOS technology. The inductive degeneration is applied to the conventional distributed amplifier design to reduce the broadband noise figure under low power operation condition. A common-source amplifier is cascaded to the distributed amplifier to improve the gain at high frequency and extend the bandwidth. Operated at 0.6V, the integrated UWB CMOS LNA consumes 7mW. The measured gain of the LNA is 10dB with the bandwidth from 2.7 to 9.1GHz. The input and output return loss is more than 10dB. The noise figure of the LNA varies from 3.8 to 6.9dB, with the average noise figure of 4.65dB. The low power consumption of this work leads to the excellent figure of gain-bandwidth product (GBP) per milliwatt     

A low supply voltage SiGe LNA for ultra-wideband frontends

A low-power low-noise amplifier (LNA) for ultra-wideband (UWB) radio systems is presented. The microwave monolithic integrated circuit (MMIC) has been fabricated using a commercial 0.25-/spl mu/m silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier uses peaking and feedback techniques to optimize its gain, bandwidth and impedance matching. It operates from 3.4 to 6.9GHz, which corresponds with the low end of the available UWB radio spectrum. The LNA has a peak gain of 10dB and a noise figure less than 5dB over the entire bandwidth. The circuit consumes only 3.5mW using a 1-V supply voltage. A figure of merit (FoM) for LNAs considering bandwidth, gain, noise, power consumption, and technology is proposed. The realized LNA circuit is compared with other recently published low-power LNA designs and shows the highest reported FoM.     

110-120-GHz monolithic low-noise amplifiers

The authors discuss the development of 110-120-GHz monolithic low-noise amplifiers (LNAs) using 0.1-mm pseudomorphic AlGaAs/InGaAs/GaAs low-noise HEMT technology. Two 2-stage LNAs have been designed, fabricated, and tested. The first amplifier demonstrates a gain of 12 dB at 112 to 115 GHz with a noise figure of 6.3 dB when biased for high gain, and a noise figure of 5.5 dB is achieved with an associated gain of 10 dB at 113 GHz when biased for low-noise figure. The other amplifier has a measured small-signal gain of 19.6 dB at 110 GHz with a noise figure of 3.9 dB. A noise figure of 3.4 dB with 15.6-dB associated gain was obtained at 113 GHz. The authors state that the small-signal gain and noise figure performance for the second LNA are the best results ever achieved for a two-stage HEMT amplifier at this frequency band     

A Low-Power,$X$-Band SiGe HBT Low-Noise Amplifier for Near-Space Radar Applications

A low-power,$X$-band low-noise amplifier (LNA) is presented. Implemented with 180 GHz silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs), the circuit occupies 780$times hbox660 muhboxm^2$. The LNA exhibits a gain of 11.0 dB at 9.5 GHz, a mean noise figure of 2.78 dB across$X$-band, and an input third-order intercept point of$-$9.1 dBm near 9.5 GHz, while dissipating only 2.5 mW. The low-power performance of this LNA, together with its natural total-dose radiation immunity, demonstrates the potential of SiGe HBT technology for near-space radar applications.     

5.7 GHz low-power variable-gain LNA in 0.18 /spl mu/m CMOS

A variable-gain low-noise amplifier (LNA) suitable for low-voltage and low-power operation is designed and implemented in a standard 0.18 /spl mu/m CMOS technology. With a current-reused topology, the common-source gain stages are stacked for minimum power dissipation while achieving high small-signal gain. The fully integrated 5.7 GHz LNA exhibits 16.4 dB gain, 3.5 dB noise figure and 8 dB gain tuning range with good input and output return losses. The LNA consumes 3.2 mW DC power from a supply voltage of 1 V. A gain/power quotient of 5.12 dB/mW is achieved in this work.     

Low-power single-to-differential LNA at S-band based on optimised transformer topology and integrated ESD

A single-ended to differential low-power low-noise amplifier (LNA) designed and implemented in 0.18 mum CMOS technology is presented. The device takes advantage of a current reuse strategy by stacking two common-source differential transistor pair stages for minimum current dissipation, together with the design of optimised high Q differential transformers and inductors in order to minimise the impact of parasitics. The fully integrated, including ESD protection diodes, 2.1 GHz LNA consumes 1.1 mW at 1.2 V supply voltage and presents 29.8 dB gain, 4.5 dB noise figure, -21.1 dBm 1 dB compression point, -11.6 dBm input third-order intercept point and -12.3 dB input return loss performance.     

CMOS low-noise amplifier design optimization techniques

This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques. Based on the noise parameter equations, this paper provides clear understanding of the design principles, fundamental limitations, and advantages of the four reported LNA design techniques so that the designers can get the overall LNA design perspective. As a demonstration for the proposed design principle of the PCSNIM technique, a very low-power folded-cascode LNA is implemented based on 0.25-/spl mu/m CMOS technology for 900-MHz Zigbee applications. Measurement results show the noise figure of 1.35 dB, power gain of 12 dB, and input third-order intermodulation product of -4dBm while dissipating 1.6 mA from a 1.25-V supply (0.7 mA for the input NMOS transistor only). The overall behavior of the implemented LNA shows good agreement with theoretical predictions.     

一种接收前端三级低噪声放大器的设计

针对单片雷达接收机中对低噪声放大器（LNA）的要求,采用CMOS0．18,um工艺设计了一个三级级联的镜像抑制低噪声放大器。通过在低噪声放大器中接入限波滤波器,实现对镜像信号的衰减,从而减小了后端混频器电路的设计难度。在ADS中对设计的放大器仿真,其结果为：最大供电电压为5V情况下,信号频段为3．0～3．2GHz,中频输出为225MHz,功率增益≥31dB,噪声系数（FN）≤O．5dB,1dB点的输入／输出功率分别为-19．5dBm和11．5dBm,对镜像信号的抑制度达22dB。