基于InP-DHBT的20 GHz的超高速比较器

采用截止频率fT为170 GHz的InP-DHBT工艺,我们设计并制作了一个超高速主从电压比较器。整个芯片的面积（包括焊盘）是0.75?1.04 mm2,在-4V的单电源电压下消耗的功耗是440mW（不包括时钟产生部分）。整个芯片包含了77个InP DHBTs。比较器的尼奎斯特测试到了20GHz,输入灵敏度在10 GHz采样率的时候是6mV,在20 GHz的时候是16 mV。据我们所知,这在国内还是第一次在单片上集成超过70个InP DHBTs的电路,也是目前国内具有最高采样率的比较器。     

Graded base type-II InP/GaAsSb DHBT with f/sub T/=475 GHz

The first demonstration of a type-II InP/GaAsSb double heterojunction bipolar transistor (DHBT) with a compositionally graded InGaAsSb to GaAsSb base layer is presented. A device with a 0.4/spl times/6 /spl mu/m/sup 2/ emitter dimensions achieves peak f/sub T/ of 475 GHz (f/sub MAX/=265 GHz) with current density at peak f/sub T/ exceeding 12 mA//spl mu/m/sup 2/. The structure consists of a 25-nm InGaAsSb/GaAsSb graded base layer and 65-nm InP collector grown by MBE with breakdown voltage /spl sim/4 V which demonstrates the vertical scaling versus breakdown advantage over type-I DHBTs.     

Low-power InP/GaAsSb/InP DHBT cascode transimpedance amplifier with GBP/P/sub dc/ of 7.2 GHz/mW

A low-power high gain-bandwidth monolithic cascode transimpedance amplifier using novel InP/GaAsSb/InP DHBT technology was investigated. The amplifier exhibited state-of-the-art performance of 17.3 dB gain, 12 GHz bandwidth, 55 dB/spl Omega/ transimpedance, and a corresponding gain-bandwidth of 6.7 THz/spl Omega/ while consuming only 12.2 mW DC power. It also achieved good gain-bandwidth-product per DC power figure-of-merit (GBP/P/sub dc/) of 7.2 GHz/mW     

基于InP衬底的GaAsSb/InP异质结晶体管

采用金属有机化学气相沉积生长了InP/GaAs0.5Sb0.5/InP 双异质结晶体三极管(DHBT)材料,研究了材料质量对器件性能的影响.制备的器件不但具有非常好的直流特性,而且还表现出良好的微波特性,其结果与能带理论的预言一致,DHBT集电结和发射结的电流理想因子分别为1.00和1.06,击穿电压高达15V,电流放大增益截止频率超过100GHz.     

基于InP衬底的GaAsSb/InP异质结晶体管

采用金属有机化学气相沉积生长了InP/GaAs0.5Sb0.5/InP 双异质结晶体三极管(DHBT)材料,研究了材料质量对器件性能的影响.制备的器件不但具有非常好的直流特性,而且还表现出良好的微波特性,其结果与能带理论的预言一致,DHBT集电结和发射结的电流理想因子分别为1.00和1.06,击穿电压高达15V,电流放大增益截止频率超过100GHz.     

A 160-GHz f/sub T/ and 140-GHz f/sub MAX/ submicrometer InP DHBT in MBE regrown-emitter technology

We report a 0.7/spl times/8 /spl mu/m/sup 2/ InAlAs-InGaAs-InP double heterojunction bipolar transistor, fabricated in a molecular-beam epitaxy (MBE) regrown-emitter technology, exhibiting 160 GHz f/sub T/ and 140 GHz f/sub MAX/. These initial results are the first known RF results for a nonselective regrown-emitter heterojunction bipolar transistor, and the fastest ever reported using a regrown base-emitter heterojunction. The maximum current density is J/sub E/=8/spl times/10/sup 5/ A/cm/sup 2/ and the collector breakdown voltage V/sub CEO/ is 6 V for a 1500-/spl Aring/ collector. In this technology, the dimension of base-emitter junction has been scaled to an area as low as 0.3/spl times/4 /spl mu/m/sup 2/ while a larger-area extrinsic emitter maintains lower emitter access resistance. Furthermore, the application of a refractory metal (Ti-W) base contact beneath the extrinsic emitter regrowth achieves a fully self-aligned device topology.     

InP/GaAsSb type-II DHBTs with GaAsSb/lnGaAs superlattice-base and GaAsSb bulk-base structures

High-performance InP/GaAsSb double heteroj unction bipolar transistor (DHBT) employing GaAsSb/lnGaAs superlattice-base structure is demonstrated and compared with GaAsSb bulk-base structure by two-dimensional simulation analysis. The proposed device exhibits a higher current gain of 257 than the conventional InP/GaAsSb type-II DHBT with a lower current gain of 180, attributed to the tynneling behavior of minority carriers in the GaAsSb/lnGaAs superlattice-base region under large forward base—emitter bias. In addition, a larger unity gain cutoff frequency of 19.1 GHz is botained for the superlattice-base device than that of 17.2 GHz for the bulk-base device.     

4-bit adder-accumulator at 41-GHz clock frequency in InP DHBT technology

A 41-GHz 4-b adder-accumulator test circuit implemented in InP double heterojunction bipolar transistor (DHBT) technology using 624 transistors is reported. High clock rates are obtained by combining the logic functions into pipelined latches. The adder-accumulator contains a single-level parallel-gated carry circuit that is used as a step toward reduced power consumption. The carry circuit has a maximum clock frequency of 55 GHz. The accumulator architecture employs modular, pipelined 2-b adders and is cascadable to 2 N-bits. The test circuit includes a 4-b digital to analog converter (DAC) that facilitates demonstration of high-speed operation.     

A compact 43-GHz monolithic differential VCO in 0.5-/spl mu/m InP DHBT technology

A compact monolithic integrated differential voltage controlled oscillator (VCO) using 0.5-/spl mu/m emitter width InP/InGaAs double-heterostructure bipolar transistors with a total chip size of 0.42 mm /spl times/ 0.46 mm is realized by using cross-coupled configuration for extremely high frequency satellite communications system applications. The device performance of F/sub max/ greater than 320 GHz at a current density of 5 mA//spl mu/m/sup 2/ and 5-V BVceo allows us to achieve a low phase noise 42.5-GHz fundamental VCO with -0.67-dBm output power. The VCO exhibits the phase noise of -106.8 dBc/Hz at 1-MHz offset and -122.3 dBc/Hz at 10-MHz offset from the carrier frequency.     

InP/GaAsSb/InP双异质结双极晶体管技术发展现状(Ⅰ)

InP/GaAsSb/InP双异质结双极晶体管(DHBT)以其独特的交错Ⅱ型能带结构,在频率特性、击穿特性和热特性等方面较传统的InP/InGaAsSHBT与InP/InGaAs/InPDHBT等显示出极大的优越性。对InP/GaAsSb/InPⅡ型DHBT技术的提出、外延层结构设计与生长、器件结构设计、器件制造工艺与优化以及国内外发展情况研究水平、发展趋势和商业化情况进行了系统的回顾和展望。指出结合垂直方向材料结构优化缩小器件尺寸和采用微空气桥隔离基极电极结构是InP/GaAsSb/InPDHBT向THz截止频率发展的最重要的技术路线。     

InP/GaAsSb/InP双异质结双极晶体管技术发展现状(Ⅱ)

5 制作工艺和优化 Ⅱ型InP DHBT的工艺流程与传统Ⅰ型InP HBT和DHBT工艺基本相同,一般沿用传统的三台面工艺,所不同之处主要是基区材料不同而导致湿法腐蚀和工艺细节变化,此外,由于Ⅱ型DHBT集电区全部采用InP材料,从而减小了由于四元缓变层带来的形成集电区台面时的工艺难度.     

InP/GaAsSb/InP double HBTs: a new alternative for InP-based DHBTs

We report on the physical operation and performance of MOCVD-grown abrupt heterojunction InP/GaAs_0.51Sb_0.49/InP double heterojunction bipolar transistors (DHBTs). In particular, the effect of the InP collector thickness on the breakdown voltage and on the current gain cutoff frequency is assessed and a f_T of 106 GHz is reported for a DHBT with a 400 Å base and a 2000 Å InP collector with a BV_CEO of 8 V. We show that InP/GaAsSb/InP DHBTs are characterized by a weak variation of f_T as a function of temperature. Finally, we also demonstrate that high maximum oscillation frequencies f_MAX>f_T can be achieved in scaled high-speed InP/GaAsSb/InP DHBTs, and provide estimates of the maximum cutoff frequencies achievable for this emergent but promising material system. Recent results on improved structures validate our performance predictions with cutoff frequencies well beyond 200 GHz     

带有复合掺杂层集电区的InP/InGaAs/InP DHBT直流特性分析

设计了一种新结构InP/InGaAs/InP双异质结双极晶体管(DHBT),在集电区与基区之间插入n -InP层,以降低集电结的导带势垒尖峰,克服电流阻挡效应.采用基于热场发射和连续性方程的发射透射模型,计算了n -InP插入层掺杂浓度和厚度对InP/InGaAs/InP DHBT集电结导带有效势垒高度和I-V特性的影响.结果表明,当n -InP插入层掺杂浓度为3×1019cm-3、厚度为3nm时,可以获得较好的器件特性.采用气态源分子束外延(GSMBE)技术成功地生长出InP/InGaAs/InP DHBT结构材料.器件研制结果表明,所设计的DHBT材料结构能有效降低集电结的导带势垒尖峰,显著改善器件的输出特性.     

带有复合掺杂层集电区的InP/InGaAs/InP DHBT直流特性分析

设计了一种新结构InP/InGaAs/InP双异质结双极晶体管(DHBT),在集电区与基区之间插入n+-InP层,以降低集电结的导带势垒尖峰,克服电流阻挡效应.采用基于热场发射和连续性方程的发射透射模型,计算了n+-InP插入层掺杂浓度和厚度对InP/InGaAs/InP DHBT集电结导带有效势垒高度和I-V特性的影响.结果表明,当n+-InP插入层掺杂浓度为3×1019cm-3、厚度为3nm时,可以获得较好的器件特性.采用气态源分子束外延(GSMBE)技术成功地生长出InP/InGaAs/InP DHBT结构材料.器件研制结果表明,所设计的DHBT材料结构能有效降低集电结的导带势垒尖峰,显著改善器件的输出特性.     

10-GHz and 20-GHz Channel Spacing High-Resolution AWGs on InP

This letter reports on 10-GHz and 20-GHz channel-spacing arrayed waveguide gratings (AWGs) based on InP technology. The dimensions of the AWGs are 6.8$,times,$8.2 mm$^{2}$ and 5.0$,times,$6.0 mm$^{2}$, respectively, and the devices show crosstalk levels of $-$12 dB for the 10-GHz and $-$17 dB for the 20-GHz AWG without any compensation for the phase errors in the arrayed waveguides. The root-mean-square phase errors for the center arrayed waveguides were characterized by using an optical vector network analyzer, and are 18 $^{circ}$ for the 10-GHz AWG and 28$^{circ}$ for the 10-GHz AWG.      

发射区底切对倒置结构InP/GaAsSb/InP DHBT性能的影响

基于考虑载流子弹道输运等非局域传输瞬态效应的流体动力学模型,数值模拟计算了集电区在上面发射区在下面的倒置InP/GaAsSb/InP双异质结双极晶体管(DHBT)器件的直流输出特性和高频性能.计算结果表明:由于集电区台面面积小,集电区在上的倒置InP/GaAsSb/InP双异质结双极晶体管有较高的高频性能;对于发射区在下面与基区接触面积大导致较多的基区载流子复合而使器件的增益偏低问题,可以考虑掩埋侧边腐蚀工艺底切发射区的技术来减少发射区和基区的接触面积,从而减少复合改善器件的增益特性.     

Direct Digital Synthesizer With Sine-Weighted DAC at 32-GHz Clock Frequency in InP DHBT Technology

A direct digital synthesizer (DDS) implemented in InP double heterojunction bipolar transistor (DHBT) technology is reported. This DDS uses a sine-weighted digital to analog converter (DAC) architecture that eliminates the need for a ROM. This enables operation at high frequencies with lower power consumption compared to traditional approaches. The phase accumulator is 8-bits wide and the sine-weighted DAC uses the five most significant bits (MSBs) for phase to amplitude conversion. The DDS operates up to a 32-GHz clock frequency for all frequency control words (FCWs) and can synthesize sine-wave outputs from 125 MHz to 16GHz in 125-MHz steps. The spurious free dynamic range (SFDR) is measured over the Nyquist bandwidth to be 31.00 dBc for the fundamental output frequency of 125 MHz. Over the full range of FCWs, the worst case SFDR is 21.56 dBc at an FCW of 95, and the average SFDR is 26.95 dBc. The circuit is implemented with 1891 transistors and consumes 9.45 W of power.