Research of SiO2/InP structure prepared by photo-CVD

The SiO₂ film as an insulator in InP MOS structure was grown by mercury-sensitized photo induced chemical-vapor deposition (photo-CVD) utilizing gaseous mixture of monosilane (SiH₄) and nitrous oxide (N₄O) under 253.7 nm ultraviolet light irradiation. The PHOTOX SiO₂ film (i.e., SiO₂ film prepared by photo-CVD system) deposited at 250° C has a refractive index of 1.46 and breakdown field strength of 7.0 MV/cm. The 1 MHz capacitance-voltage characteristics of the InP MOS diode was measured to study the interface state densities. The minimum value is 1.2 × 10¹¹ cm⁻²eV⁻¹ for the sample prepared at a substrate temperature of 250° C.     

MOS device fabrication using sputter-deposited gate oxide and polycrystalline silicon layers

For applications in the MOS device fabrication the interface properties of sputtered SiO₂ and SiO₂-polycrystalline silicon layers on silicon substrates were investigated and improved to a quality which is equivalent to those of thermally grown SiO₂ with pyrolytical polycrystalline silicon (polySi). For testing these layers as gate oxide and Si electrodes of MOS transistors the well known Si gate process was varied to include sputter deposition and the optimal deposition, annealing and diffusion parameters were integrated.MOS transistors with sputtered SiO₂ and Si gate material layers and for comparison Al gate devices with sputtered SiO₂ have been fabricated and their threshold voltage behavior was tested.     

High-efficiency,thin-film InP concentrator solar cells

High-efficiency, thin-film InP solar cells grown heteroepitaxially on GaAs and Si single-crystal bulk substrates are being developed as a means of eliminating the problems associated with using single-crystal InP substrates (e.g., high cost, fragility, high mass density and low thermal conductivity). A novel device structure employing a compositionally graded Ga _x In_1−x As layer (∼8 μm thick) between the bulk substrate and the InP cell layers is used to reduce the dislocation density and improve the minority carrier properties in the InP. The structures are grown in a continuous sequence of steps using computer-controlled atmospheric-pressure metalorganic vapor-phase epitaxy (AP-MOVPE). Dislocation densities as low as 3×10⁷ cm⁻² and minority carrier lifetimes as high as 3.3 ns are achieved in the InP layers with this method using both GaAs or Si substrates. Structures prepared in this fashion are also completely free of microcracks. These results represent a substantial improvement in InP layer quality when compared to heteroepitaxial InP prepared using conventional techniques such as thermally cycled growth and post-growth annealing. The present work is concerned with the fabrication and characterization of thin-film InP solar cells designed for operation at high solar concentration (∼100 suns) which have been prepared from similar device structures grown on GaAs substrates. The cell performance is characterized as a function of the air mass zero (AM0) solar concentration ratio (1–100 suns) and operating temperature (25°–80° C). From these data, the temperature coefficients of the cell performance parameters are derived as a function of the concentration ratio. Under concentration, the cells exhibit a dramatic increase in efficiency and an improved temperature coefficient of efficiency. At 25° C, a peak conversion efficiency of 18.9% (71.8 suns, AM0 spectrum) is reported. At 80° C, the peak AM0 efficiency is 15.7% at 75.6 suns. These are the highest efficiencies yet reported for InP heteroepitaxial cells. Approaches for further improving the cell performance are discussed.     

Structural,compositional and electrical characterization of Si-rich SiOx layers suitable for application in light sensors

Metal-Oxide-Silicon (MOS) structures containing silicon nanoparticles (SiNPs) in three different gate dielectrics, single SiO_x layer (c-Si/SiNPs-SiO_x), two-region (c-Si/thermal SiO_x/SiNPs-SiO_x) or three-region (c-Si/thermal SiO₂/SiNPs-SiO_x/SiO₂) oxides, were prepared on n-type (100) c-Si wafers. The silicon nanoparticles were grown by a high temperature furnace annealing of sub-stoichiometric SiO_x films (x=1.15) prepared by thermal vacuum evaporation technique. Annealing in N₂ at 700 or 1000 °C leads to formation of amorphous or crystalline SiNPs in a SiO_x amorphous matrix with x=1.8 or 2.0, respectively. The three-region gate dielectric (thermal SiO₂/SiNPs-SiO₂/SiO₂) was prepared by a two-step annealing of c-Si/thermal SiO₂/SiO_x structures at 1000 °C . The first annealing step was carried out in an oxidizing atmosphere while the second one was performed in N₂. Cross-sectional Transmission Electron Microscopy and X-ray Photoelectron Spectroscopy have proven both the nanoparticle growth and the formation of a three region gate dielectric. Annealed MOS structures with semitransparent aluminum top electrodes were characterized electrically by current/capacitance–voltage measurements in dark and under light illumination. A strong variation of the current at negative gate voltages on the light intensity has been observed in the control and annealed at 700 °C c-Si/SiNPs-SiO_x/Al structures. The obtained results indicate that MOS structures with SiO_1.15 gate dielectric have potential for application in light sensors in the NIR–Visible Light–UV range.     

The effect of post-deposition thermal processing on MOS gate oxides formed by remote PECVD

The effects of post-deposition thermal exposure, at temperatures typical of MOS fabrication processes, on gate oxides formed by remote plasma enhanced chemical vapor deposition (RPECVD) is discussed. SiO₂ films were prepared by (1) thermal oxidation of silicon at temperatures from 700 to 1150° C, and (2) by RPECVD at a substrate temperature of 350° C. Post deposition thermal processing was achieved by rapid thermal annealing for 100 sec from 850–1200° C. Film properties were studied by infrared spectroscopy (IR), ellipsometry, and by measurements of stress, capacitance voltage characteristics, and dielectric breakdown. Post-formation, thermal processing in the range of 850–1200° C was shown to modify both thermally grown and deposited oxides, but it has been shown that RPECVD films could be stabilized against post-deposition changes by rapid thermal annealing at temperatures of about 900° C for periods of at least 100 sec.     

Resistivity changes of heavily-boron-doped CVD-prepared polycrystalline silicon caused by thermal annealing

Heavily-boron-doped polycrystalline Si films were deposited at 600°C on thermally grown SiO₂ by the thermal decomposition of SiH₄-BCl₃-H₂ mixture. Resistivity changes with isochronal or sequential annealing were systematically examined. Temperature dependence of equilibrium saturation carrier concentration was determined at 800 ～ 1100°C. Since as-deposited polycrystalline Si is in the super-saturated state, carrier concentration decreases from the super-saturated to equilibrium saturation value by annealings over 700°C for poly Si doped with over 2 × 10²⁰ cm^?3 resulting in anomalous resistivity change. Carrier concentration changes reversibly between saturation values with sequential annealing and is determined by the last annealing temperature when the annealing time is long enough. Mobility increases with annealing temperature, however, less increase is found for heavily doped poly Si, which is attributed to the suppression of grain growth caused by electrically inactive Si-B compounds.     

Studies of liquid-phase deposition-oxide/InP structure by liquid-phase deposition

Silicon-dioxide (SiO₂) growth on an indium-phosphide (InP) substrate by use of room-temperature (∼30°C) liquid-phase deposition (LPD) is demonstrated. The produced LPD-SiO₂ is of good quality and reliability because of the suppression of interdiffusion by use of relatively low temperatures. Because LPD is difficult without residual OH on the substrate, an InP surface rich in hydroxyls (In-OH) is created by pretreating the wafer substrate in a (29% NH₄OH:H₂O₂=1:1) solution. The LPD-SiO₂/InP is used to fabricate a metal-oxide semiconductor (MOS) capacitor with a device area of 1.12×10⁻⁴ cm², yielding a leakage-current density of 8.1×10⁻⁹ A/cm² at 3 MV/cm. A mechanism for the LPD deposition of SiO₂ on InP is also presented.     

Growth of CsLiB6O10 thin films on Si substrate by pulsed laser deposition using SiO2 and CaF2 as buffer layers

CsLiB₆O₁₀ (CLBO) thin films are grown on Si (100) and (111) substrates using lower index SiO₂ and CaF₂ as buffer layers by pulsed KrF (248 nm) excimer laser ablation of stoichiometric CLBO targets over a temperature range of 425 to 725°C. A CaF₂ buffer layer is grown on Si by laser ablation while SiO₂ is prepared by standard thermal oxidation. From extended x-ray analysis, it is determined that CaF₂ is growth with preferred orientation on Si (100) at temperatures lower than 525°C while on Si (111) substrate, CaF₂ is grown epitaxially over the temperature range; this agrees well with observed reflection high energy electron diffraction patterns. X-ray 2θ-scans indicate that crystalline CLBO are grown on SiO₂/Si and CaF₂/Si (100). Analysis of reflectance spectra from CLBO/SiO₂/Si yields the absorption edge at 182 nm. Surface roughness of the CaF₂ and CLBO/CaF₂/Si film are 19 and 15 nm, respectively. This relatively rough surface caused by the ablation of wide bandgap CaF₂ and CLBO limits the application of CLBO for waveguiding measurement.     

Large-Area Direct Hetero-Epitaxial Growth of 1550-nm InGaAsP Multi-Quantum-Well Structures on Patterned Exact-Oriented (001) Silicon Substrates by Metal Organic Chemical Vapor Deposition

We employ a simple two-step growth technique to grow large-area 1550-nm laser structures by direct hetero-epitaxy of III–V compounds on patterned exact-oriented (001) silicon (Si) substrates by metal organic chemical vapor deposition. Densely-packed, highly uniform, flat and millimeter-long indium phosphide (InP) nanowires were grown from Si v-grooves separated by silicon dioxide (SiO₂) stripes with various widths and pitches. Following removal of the SiO₂ patterns, the InP nanowires were coalesced and, subsequently, 1550-nm laser structures were grown in a single overgrowth without performing any polishing for planarization. X-ray diffraction, photoluminescence, atomic force microscopy and transmission electron microscopy analyses were used to characterize the epitaxial material. PIN diodes were fabricated and diode-rectifying behavior was observed.     

Strain distribution in InP grown on patterned Si: Direct visualization by cathodoluminescence wavelength imaging

InP has been grown on patterned Si substrates using a low temperature metalorganic chemical vapor deposition process which insures compatibility with integrated circuit technology. Two different patterns are investigated: wet chemically etched V-grooves and SiO₂-masked dry etched grooves. Reduction of feature size leads to drastic defect reduction and quantum efficiencies up to those of homoepitaxially grown InP. Strain relaxation and quantum efficiency are directly visualized by cathololuminescence wavelength imaging. On (001)-and {111}-facets of V-grooves distinct relaxation of the tensile thermally induced strain are found. Surprisingly, in the bottom of V-grooves, close to or even at the InP/Si interface, a high quantum efficiency is found with a recombination time constant typical for thick InP layers of high crystallographic quality.     

Structural and electrical characterization of CoNiO monolayer as copper diffusion barrier in integrated circuits

Diffusion barrier properties of CoNiO monolayer, deposited by Langmuir Blodgett (LB) technique, were studied against the diffusion of copper through SiO₂. Cu/CoNiO/SiO₂/Si and Cu/SiO₂/Si test structures were prepared and compared for this purpose. These test structures were annealed at temperatures starting from 100 °C up to 650 °C in vacuum. Samples were characterized using Energy Dispersive X-ray Spectroscopy (EDS), Atomic force microscopy (AFM), X-ray diffraction (XRD), scanning electron microscope (SEM), four probe resistivity measurement, Capacitance-Voltage (C‒V), Current-Voltage (I‒V) characterization techniques. EDS and AFM confirmed the composition and structure of the deposited monolayer. Thermal stability was studied using X-ray diffraction (XRD), Scanning Electron Microscope (SEM) and four probe techniques. Results indicated that structure with barrier was stable up to 600 °C whereas its counterpart could sustain only up to 300 °C. Sheet resistance of Cu/SiO₂/Si structure starts increasing at 300 °C and that of Cu/CoNiO/SiO₂/Si test structure was almost unchanged up to 600 °C in. SEM analysis of samples annealed at different temperatures also confirmed the XRD and four probe results. Biased Thermal Stress (BTS) was applied to the samples and its effect was observed using C‒V analysis. C‒V curves showed that in the presence of CoNiO barrier layer there was no shift in the C‒V curve even after 120 min of BTS while in the absence of barrier there was a significant shift in the C‒V curve even after 30 min of BTS. Leakage current density (j_L) was plotted against the BTS duration under same BTS conditions. It was found that the Cu/CoNiO/SiO₂/Si stack could survive about two times more than the Cu/SiO₂/Si stack.     

Effect of O+ implantation on silicon-silicon dioxide interface properties

A detailed investigation has been made by the MOS capacitance method, into the mechanism by which the fixed positive surface state charge, due to silicon rich oxide near SiSiO₂ interface, is controlled by O⁺ implantation into the oxide near the SiSiO₂ interface, and subsequent heat treatment. High dosage implantation of 3 × 10¹³ O⁺ ions cm^?2 results in damage in oxide which is occured by 450°C annealing. However, low dosage implantation of 3 × 10^?2 produces no detectable damage in the oxide, and increases the effective positive charge in the oxide at Si'SiO₂ interface. It is shown that prolonged 450°C heat treatment of 0⁺ ion implanted oxides results in an oxygen-silicon reaction in the silicon enriched oxide layer and reduces the fixed positive surface state charge. Subsequent heat treatments at 838°C increase the positive surface state charge to the original pre-ion implantation values, hence converting the oxide into the original silicon rich condition.     

MOS solar cells with oxides deposited by sol-gel spin-coating techniques

The metal-oxide-semiconductor (MOS) solar cells with sol-gel derived silicon dioxides (SiO₂) deposited by spin coating are proposed in this study. The sol-gel derived SiO₂ layer is prepared at low temperature of 450°C. Such processes are simple and low-cost. These techniques are, therefore, useful for largescale and large-amount manufacturing in MOS solar cells. It is observed that the short-circuit current (I _sc) of 2.48 mA, the open-circuit voltage (V _os) of 0.44 V, the fill factor (FF) of 0.46 and the conversion efficiency (η%) of 2.01% were obtained by means of the current-voltage (I–V) measurements under AM 1.5 (100 mW/cm²) irradiance at 25°C in the MOS solar cell with sol-gel derived SiO₂.     

Improved electrical properties on the anodic oxide/InP interface for MOS structures

The interface properties of the anodic oxide/n-type (111) InP metal oxide semiconductor (MOS) structures significantly improved while using the polishing agent HBr:K₂Cr₂O₇:H₂O (BCA). Annealing at 250°C dehydrates the grown oxides and has a strong effect on the surface potential. Composition of the oxides analyzed using x-ray photoelectron spectroscopy showed that the oxides are composed of In₂O₃, InPO₃, and InPO₄. MOS structures fabricated on BCA polished substrates show a lower surface state density of 6 × 10¹⁰ cm⁻² eV⁻¹ when compared to the substrates polished with bromine-methanol (8 × 10¹⁰ cm⁻² eV⁻¹).     

Mechanical stress and refractive index variation in dry SiO2

The variation of mechanical stress σ and refractive index n with the film thickness of SiO₂, thermally grown on Si in dry oxygen at an oxidation temperature of 850°C, is investigated. The results indicate that an inhomogeneity region for σ and n is formed during the film growth, beyond which the values of a and n remain constant (5 5×l08Nm^-2 and 1.47, respectively). It is shown, further, that ‘additional’ factors take effect, giving rise to structural changes unrelated to mechanical stress.     

Growth and crystal quality of inp crystals by the liquid encapsulated czochralski technique

The growth of InP single crystals by the liquid encapsulated Czochralski (LEC) technique has been studied from the standpoint of improving crystal quality. Twin-free crystals have been grown reproducibly in the <lll>P direction under the following conditions; (1) using starting material which does not contain fine InP particles, (2) controlling the cone shape of the crystals such that the angle with the growth axis is less than 19.68°, (3) arranging the.hot zone to produce a temperature at the top surface of the B₂O₃ encapsulant layer below 550°C. It has been confirmed that electrical properties of nominally undoped crystals are dominated by the impurity, Si, and the concentration of Si in an LEC crystal corresponds to that of the starting material. The dislocation densities of undoped LEC InP crystals depend on thermal stresses during the growth process. This knowledge has led to the growth of dislocation-free crystals.     

Selective epitaxy of cadmium telluride on silicon by MBE

CdTe B was grown on As-terminated Si(111) by molecular beam epitaxy (MBE). Nucleation and interface properties were studied by photoelectron spectroscopy, scanning tunneling microscopy, electron diffraction, and energy-dispersive spectroscopy of x-rays. Selective growth on Si(111) was investigated either by using SiO₂ as a mask, or by growing on a patterned CdTe seed layer. The highest temperature where CdTe nucleates on As-terminated Si(111) surfaces is typically in the range of 220–250°C. On a SiO₂ mask, CdTe nucleates at the same temperatures, leading to polycrystalline growth. However, homoepitaxy of CdTe is possible around 300°C. Hence, CdTe can be grown selectively on a patterned CdTe seed layer on Si(111). This is confirmed by scanning electron microscopy and scanning Auger microscopy.     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

The effects of gamma irradiation on low-pressure chemical-vapor-deposited silicon dioxide metal-oxide-silicon structures

The effects of gamma irradiation on as-deposited, oxygen-annealed, and dual-dielectric gate (undoped polysilicon/oxide) low-pressure chemical-vapor-deposited (LPCVD) silicon dioxide (SiO₂) metal-oxide-silicon (MOS) structures were investigated. As-deposited LPCVD SiO₂ MOS structures exhibit the largest shift in flatband voltage with gamma irradiation. This is most likely due to the large number of bulk oxide traps resulting from the nonstochiometric nature of as-deposited LPCVD SiO₂. Dual-dielectric (undoped polysilicon/annealed LPCVD SiO₂) MOS structures exhibit the smallest shift in flatband voltage and increase in interface state density compared to as-deposited and oxygen-annealed LPCVD SiO₂ MOS structures. The interface state density of dual-dielectric MOS structures increases from 5 × 10¹⁰ eV cm⁻² to 2–3 × 10¹¹ eV cm⁻² after irradiation to a gamma total dose level of 1 Mrads(Si). This result suggests that the recombination of atomic hydrogen atoms with silicon dangling bonds, either along grain boundaries or in crystallites of the undoped polysilicon layer in dual-dielectric (undoped polysilicon/annealed LPCVD SiO₂) MOS structures, probably reduces the number of atomic hydrogen atoms reaching the Si/SiO₂ interface to generate interface states.     

Deposition and characterization of Pb TiO3 thin films on silicon wafers using metalorganic sources

Ferroelectric PbTiO₃ thin films were deposited on bare silicon and Pt/SiO₂/Si substrates by metalorganic chemical vapor deposition in a temperature range from 270 to 550°C. The deposition of a single phase PbTiO₃ thin film did not occur on bare silicon substrates. Instead a double layer of lead-silicate and PbTiO₃ was formed owing to a serious diffusion of lead and oxygen ions into silicon substrates. But on Pt/SiO₂/Si substrates, a single phase PbTiO₃ oriented parallel to a-and c-axis was grown at a substrate temperature as low as 350°C even without a high temperature post-annealing. To get an optimal film, a precise control of input gas composition and also a deposition in a low temperature range from 350 to 400°C are necessary.