Low-Power, High-Performance Architecture of the PWRficient Processor Family

The dual-core PA6T-1682M system on chip (SoC) is the first design in the PWRficient family of high-performance, low-power processor designs that target server-class performance with low power consumption. the heart of the PA6T-1682M is the PA6T core, which implements the 64-bit IBM power architecture. The SoC implements extensive features that support embedded and mobile low-power applications.     

A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine

Accelerating a genetic algorithm (GA) by implementing it in a reconfigurable field programmable gate array (FPGA) is described. The implemented GA features: random parent selection, which conserves selection circuitry; a steady-state memory model, which conserves chip area; survival of fitter child chromosomes over their less-fit parent chromosomes, which promotes evolution. A net child chromosome generation rate of one per clock cycle is obtained by pipelining the parent selection, crossover, mutation, and fitness evaluation functions. Complex fitness functions can be further pipelined to maintain a high-speed clock cycle. Fitness functions with a pipeline initiation interval of greater than one can be plurally implemented to maintain a net evaluated-chromosome throughput of one per clock cycle. Two prototypes are described: The first prototype (c. 1996 technology) is a multiple-FPGA chip implementation, running at a 1 MHz clock rate, that solves a 94-row × 520-column set covering problem 2,200× faster than a 100 MHz workstation running the same algorithm in C. The second prototype (Xilinx XVC300) is a single-FPGA chip implementation, running at a 66 MHZ clock rate, that solves a 36-residue protein folding problem in a 2-d lattice 320× faster than a 366 MHz Pentium II. The current largest FPGA (Xilinx XCV3200E) has circuitry available for the implementation of 30 fitness function units which would yield an acceleration of 9,600× for the 36-residue protein folding problem.     

A Software-Configurable Processor Architecture

A software-configurable processor combines a traditional RISC processor with a field-programmable instruction extension unit that lets the system designer tailor the processor to a particular application. To add application-specific instructions to the processor, the programmer adds a pragma before a C or C++ function declaration, and the compiler then turns the function into a single instruction     

Rock: A High-Performance Sparc CMT Processor

Rock, Sun's third-generation chip-multithreading processor, contains 16 high-performance cores, each of which can support two software threads. Rock uses a novel checkpoint-based architecture to support automatic hardware scouting under a load miss, speculative out-of-order retirement of instructions, and aggressive dynamic hardware parallelization of a sequential instruction stream. It is also the first processor to support transactional memory in hardware.     

适用于SIMD体系结构的FPGA分页仿真模型研究

SIMD结构能有效地开发多媒体和复杂科学计算的并行性,成为产业应用和研究的热点.在大规模SIMD体系结构研究中,为缓解FPGA芯片容量对仿真系统规模的限制,提出了适用于SIMD体系结构的FPGA分页仿真模型,有效降低了SIMD结构对FPGA计算资源和存储资源的需求,提高了SIMD结构的可验证规模.对MASA流处理器的仿真实验结果表明,不采用任何仿真优化技术,FPGA芯片EP2S180可支持的最大仿真规模为8个cluster的MASA,采用分页仿真模型,EP2S180的最大仿真规模可增加至256个cluster的MASA,而且仿真时间的增量是可接受的.     

An FPGA-Based Network Intrusion Detection Architecture

Network intrusion detection systems (NIDSs) monitor network traffic for suspicious activity and alert the system or network administrator. With the onset of gigabit networks, current generation networking components for NIDS will soon be insufficient for numerous reasons; most notably because the existing methods cannot support high-performance demands. Field-programmable gate arrays (FPGAs) are an attractive medium to handle both high throughput and adaptability to the dynamic nature of intrusion detection. In this work, we design an FPGA-based architecture for anomaly detection in network transmissions. We first develop a feature extraction module (FEM) which aims to summarize network information to be used at a later stage. Our FPGA implementation shows that we can achieve significant performance improvements compared to existing software and application-specific integrated-circuit implementations. Then, we go one step further and demonstrate the use of principal component analysis as an outlier detection method for NIDSs. The results show that our architecture correctly classifies attacks with detection rates exceeding 99% and false alarms rates as low as 1.95%. Moreover, using extensive pipelining and hardware parallelism, it can be shown that for realistic workloads, our architectures for FEM and outlier analysis achieve 21.25- and 23.76-Gb/s core throughput, respectively.     

一种高性能分簇式超标量微处理器结构

随着超标量微处理器指令发射宽度的增大,流水线中各个部件的硬件复杂度以及连线长度迅速增加,特别是当工艺线宽越来越小时,连线延迟成为阻碍处理器性能提高的瓶颈。我们提出了一种分簇式超标量处理器结构,在维持发射宽度不变的前提下能够有效降低硬件复杂度,缩短连线长度,减小延迟时间。通过对该分簇的处理器进行模拟并估算它们的物理寄存器组的延迟和面积,我们发现,对于2×4分簇结构,在寄存器组面积减少12%的同时,处理器性能至少可获得16%的提升。     

高性能众核处理器芯片时钟网络设计

随着芯片工艺演进与设计规模增加,高性能众核处理器芯片时钟网络设计面临时序和功耗的全方位挑战。为降低芯片时钟网络功耗并缓解时钟网络分布受片上偏差影响导致的时钟偏斜,在H-Tree+MESH混合时钟网络结构的基础上,结合新一代众核处理器芯片面积大及核心时钟网络分布广的特点,基于标准多源时钟树设计策略构建多源时钟树综合（MRCTS）结构,通过全局H-Tree时钟树保证芯片不同区域间时钟偏斜的稳定可控,利用局部时钟树综合进行关键路径的时序优化以实现时序收敛。实验结果表明,MRCTS能在保证时钟延时、时钟偏斜等性能参数可控的基础上,有效降低时钟网络的负载和功耗,大幅压缩综合子模块的布线资源,加速关键路径的时序收敛,并且在相同电源电压和时钟频率的实测条件下,可获得约22.15%的时钟网络功耗优化。     

Anteater: A Service-Oriented Architecture for High-Performance Data Mining

Data mining focuses on extracting useful information from large volumes of data, and thus has been the center of much attention in recent years. Building scalable, extensible,and easy-to-use data mining systems,however,has proved to be difficult. In response, the authors developed Anteater, a service-oriented architecture for data mining that relies on Web services to achieve extensibility and interoperability, offers simple abstractions for users, and supports computationally intensive processing on large amounts of data through massive parallelism.     

SODA: A High-Performance DSP Architecture for Software-Defined Radio

Software-defined radio (SDR) belongs to an emerging class of applications with the processing requirements of a supercomputer but the power constraints of a mobile terminal. The authors developed the signal-processing on-demand architecture (SODA), a fully programmable architecture that supports SDR, by examining two widely differing protocols, W-CDMA and 802.11A. It meets power-performance requirements by separating control and data processing and by employing ultrawide SIMD execution     

Array Processor Architecture

Today's array processors provide a cost-effective tool for increasing the speed at which highly computation-bound processing jobs can be carried out. They are maturing and expanding with greatly improved hardware and software—improvements that are primarily a result of the accumulated experience of the vendors and users of these machines. All in all, it is a very competitive environment.     

一种基于高性能中间件的软件体系结构

软件体系结构是软件设计的基础,在不同的应用领域有具体的设计和表达。随着网络建设的完善,我国各级政府职能部门建立在网络上的应用系统日益增多,本文以交通管理部门应用为例,系统分析了政府部门应用系统的特点和要求,并利用软件体系结构的方法,提出了一种专为该类应用领域设计的基于高性能CORBA中间件技术的非复用连接和反应者/线程优先级体系结构,为政府特定领域的行业级应用软件设计提供了一种可行的解决方案。     

A High-Performance Architecture with a Macroblock-Level-Pipeline for MPEG-2 Coding

A high-performance parallel and pipelined architecture (MViP) has been proposed for MPEG-2 coding. A macrocell for use in an ASIC has been designed and implemented using ES2 0.7 μm dual-layer-metal CMOS technology. This macrocell consists of about 120,000 equivalent gates and is able to execute, in real time, the Loop of an MPEG-2 coder for main profile/main level (MP@ML) resolution when running at 40 MHz. MViP is made up of several specific-purpose units (SPUs), an RISC core processor, banks of internal memory and an optimized crossbar network which lets these pipelined SPUs and RISC core work in parallel at a macroblock-level-pipeline, greatly increasing silicon efficiency.     

高吞吐率浮点FFT处理器的FPGA实现研究

受浮点操作的长流水线延迟及FPGA片上RAM端口数目的限制,传统H可处理器的吞吐率通常只能达到每周期输出一个复数结果。本文用FPGA设计并实现了一种高吞吐率的IEEE754标准单精度浮点FFT处理器,通过改进蝶形计算单元的结构并重新组织FPGA片上RAM的访问,该处理器每周期平均可输出约两个复数计算结果,吞吐率约为传统FFT处理器吞吐率的两倍。对于1024点FFT变换,可在（512＋10）＊10=5220周期内完成。     

媒体处理器结构综述

有效处理多媒体应用正成为媒体应用领域最主要的瓶颈之一，目前已有多种针对媒体应用的处理器结构。该文根据媒体处理器结构的可编程性和发展过程，把媒体处理器分为3类：专用结构处理器，带媒体扩展指令的通用处理器和多核处理器。结合典型芯片对各种处理器结构进行了分析和综述，指出了媒体处理器结构的发展趋势。     

An Energy-Efficient Processor Architecture for Embedded Systems

We present an efficient programmable architecture for compute-intensive embedded applications. The processor architecture uses instruction registers to reduce the cost of delivering instructions, and a hierarchical and distributed data register organization to deliver data. Instruction registers capture instruction reuse and locality in inexpensive storage structures that are located near to the functional units. The data register organization captures reuse and locality in different levels of the hierarchy to reduce the cost of delivering data. Exposed communication resources eliminate pipeline registers and control logic, and allow the compiler to schedule efficient instruction and data movement. The architecture keeps a significant fraction of instruction and data bandwidth local to the functional units, which reduces the cost of supplying instructions and data to large numbers of functional units. This architecture achieves an energy efficiency that is 23× greater than an embedded RISC processor.     

一种神经网络并行处理器的体系结构

神经网络处理系统所能实现神经网络模型的种类越多其通用性越好,应用范围就越广泛.提出了一种神经网络并行处理器的体系结构,能以较高的并行度实现典型的前馈网络-BP网络和典型的反馈网络-Hopfield网络的算法.该处理器以SIMD(Single Instruction Multiple Data)为主要计算结构,并结合这两种网络算法的特点设计了一维脉动阵列和全联通的互连网络,能够方便灵活地实现处理单元之间的数据共享.实验结果表明该体系结构有效地提高了神经网络的运行速度.     

A High-Performance Workstation Using a Closely Coupled Architecture

The Syte workstation architecture closely couples the graphics system and the processor to improve interactive performance and reduce hardware and software overhead without added support mechanisms.     

一种高性能网络游戏服务器架构设计

网络游戏一般采用C/S结构,服务器架构设计是成功开发一款网络游戏的关键,本文对高性能网络游戏服务器架构设计进行了深入地研究。网络游戏服务器的物理结构一般分成区和组,一个区会包括多组服务器,本文设计出的服务器组架构包括LoginGate、LoginServer、GameGate、GameServer、DBServer和MServer等服务器。     

基于SystemC的网络处理器体系结构建模方法

随着各种新的网络业务不断出现,网络处理器得到了日益广泛的应用。文章采用基于SystemC的系统设计方法,构建一个用于网络处理器体系结构建模的平台。这个平台由一个可扩展的异构资源库和一个体系结构构造器组成。设计者只需提交配置信息表,体系结构构造器就能自动生成模型实例,得到的模型可以方便地进行细化和性能评价。这种方法能够便捷地完成各种网络处理器的体系结构建模,便于网络处理器的优化设计。