Construction of Maximum Run-Length Limited Codes Using Sequence Replacement Techniques

The sequence replacement technique converts an input sequence into a constrained sequence in which a prescribed subsequence is forbidden to occur. Several coding algorithms are presented that use this technique for the construction of maximum run-length limited sequences. The proposed algorithms show how all forbidden subsequences can be successively or iteratively removed to obtain a constrained sequence and how special subsequences can be inserted at predefined positions in the constrained sequence to represent the indices of the positions where the forbidden subsequences were removed. Several modifications are presented to reduce the impact of transmission errors on the decoding operation, and schemes to provide error control are discussed as well. The proposed algorithms can be implemented efficiently, and the rates of the constructed codes are close to their theoretical maximum. As such, the proposed algorithms are of interest for storage systems and data networks.     

An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment

To obtain satisfactory fault coverage for testing a logic circuit, linear feedback shift registers (LFSRs) have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based built-in self-test environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this paper we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test power wasted during the scan operation can also be significantly reduced.     

一种新的缩短随机测试序列长度的方法

本文提出了一种新的缩短随机测试序列长度的方法,它是在找到电路中难测故障分布的基础上,通过对电路的初始输入施加概率不等的“１”信号,使这些难测故障的测试率升至最大值,这样,就可以达到提高故障覆盖率和缩短测试序列长度的目的。     

第一类m子序列的构造

伪随机序列在流密码、信道编码、扩频通信等领域有着广泛的应用,m序列是优秀的伪随机序列.基于m序列,本文首次提出通过重构m序列移位寄存器状态图,构造一类称之为m子序列的移位寄存器状态图.根据重构的状态图,提出了第一类m子序列并予以证明.本文推导了第一类m子序列移位寄存器反馈函数式,分析了第一类m子序列具有良好的周期特性、游程特性、平衡特性以及较高的线性复杂度.仿真结果表明,m子序列自相关特性也具有很好的δ(t)函数特征.利用文中给出的构造方法,可以构造更多性能优良的m子序列.     

Finding unusual medical time-series subsequences: algorithms and applications.

In this work, we introduce the new problem of finding time series discords. Time series discords are subsequences of longer time series that are maximally different to all the rest of the time series subsequences. They thus capture the sense of the most unusual subsequence within a time series. While discords have many uses for data mining, they are particularly attractive as anomaly detectors because they only require one intuitive parameter (the length of the subsequence), unlike most anomaly detection algorithms that typically require many parameters. While the brute force algorithm to discover time series discords is quadratic in the length of the time series, we show a simple algorithm that is three to four orders of magnitude faster than brute force, while guaranteed to produce identical results. We evaluate our work with a comprehensive set of experiments on electrocardiograms and other medical datasets.     

Detection and visualization of tandem repeats in DNA sequences

One conspicuous feature of DNA is the extent to which nucleotide subsequences repeat in the genome. Several strongly repetitive tandem (or contiguous) repeats are known to be associated with genetic diseases, while weaker repetitive structures are thought to be representative of historical events associated with sequence repetition. Thus, it is important to develop sensitive and rapid automation of the detection and identification of repeat sequences. A new algorithm for examining periodic patterns in DNA sequences is developed. The algorithm uses the short-time periodicity transform to compute the closest periodic sequence of fixed length at each nucleotide position in a given sequence to be analyzed. Each such subsequence is then compared to its closest periodic sequence to provide a quantitative measure of the amount of repetition within the sequence. In addition to being used to detect the presence of repeat subsequences in DNA, the periodicity explorer algorithm provides a potentially useful visualization of periodic patterns in a DNA sequence through a graphical display of the relative energy in the optimal periodic projections of the analyzed sequences, i.e., the DNA periodogram. Computationally, the algorithm is linear in the length of the analyzed sequence.     

A new DFT methodology for sequential circuits

This paper introduce a new design for testability methodology for sequential circuits based on input/output pin utilization which exploits the possibility of applying test patterns in parallel. The goal is to reduce the test application time maintaining the same fault coverage as the one obtained using full scan. The proposed procedure includes necessary and sufficient conditions which are easily incorporated in a design system and produce the required implementation. Successful experimental results are presented on benchmark circuits:IC test length is reduced on an average by 44% of full scan.This work is partly supported by research grants from the Natural Sciences and Engineering Research Council of Canada and equipment grants from the Canadian Microelectronics Corporation.     

Test Set Compaction Using Relaxed Subsequence Removal

Recent work observed that a subset of states are frequently visited during the simulation of a test set for a sequential circuit. Re-visiting a state implies that a cycle has been traversed in the state diagram. Removal of subsequence responsible for the cycle can lead to static compaction. The size of a cycle is the number of vectors in its subsequence. In this work, we extend the subsequence removal technique to provide significantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to identify more or larger cycles in a test set. State relaxation creates more opportunities for subsequence removal and hence, results in better compaction. Relaxation of a state is possible since not all memory elements in a finite state machine have to be specified for a state transition. The proposed technique has several advantages: (1) test sets that could not be compacted by existing subsequence removal techniques can now be compacted, (2) the size of cycles in a test set can be significantly increased by state relaxation and removal of the larger sized cycles leads to better compaction, (3) only two fault simulation passes are required as compared to trial and re-trial methods that require multiple fault simulation passes, and (4) significantly higher compaction is achieved in short execution times as compared to known subsequence removal methods. Experiments on ISCAS89 sequential benchmark circuits and several synthesized circuits show that the proposed technique consistently results in significantly higher compaction in short execution times.     

参数重用的HEVC多描述视频编码

为了提高视频编码的容错性能,保证视频经不可靠信道传输后的重建质量。本文提出了一种面向高效视频编码标准（High Efficiency Video Coding,HEVC）的基于参数重用的多描述视频编码方法。原始视频进行空间梅花下采样,生成四个行列交错的子序列,其中两个子序列采用标准编码器进行编码,并在编码过程中提取视频中每个编码单元（Coding Unit,CU）的深度信息、预测单元（Predicting Unit,PU）的分割方式以及帧内预测模式。而其余两个子序列利用已编码的视频序列信息,进行简化的编码过程。选取一个经标准编码的子序列,与一个简化编码的子序列,结合生成描述1,其余子序列生成描述2,不同描述分信道传输。多描述的编码结构可以保证即使只接收到单一描述也能保证视频的重建质量,参数重用的方法利用子序列间的相关性,减少了冗余信息,降低了编码开销。实验结果表明,参数重用的HEVC多描述视频编码针对高清视频编码效果明显,边缘解码质量PSNR值仅略低于中心解码0.7 dB,有效地提高了高清视频编码的容错性能。进行简化编码子序列的平均编码时间节省了91.7%,实现了高编码效率、低复杂度的HEVC容错编码。      

一种基于LSH的时间子序列匹配查询算法

提出了一种基于LSH（locality sensitive hashing,局部敏感散列）算法处理时间子序列匹配问题的方法LSHSM。不同于FRM和DualMatch方法,该方法不需要对时间序列做DFT、DWT等特征变换,而是直接把序列看成高维数据点,利用LSH能处理高维数据的特性来查找相似时间子序列。实验采用3种不同的时间序列数据集,通过与线性扫描算法比较,验证了算法的有效性,性能有很大的提高。     

An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation

This paper presents a novel seed-based test pattern generator (SB-TPG). The core of SB-TPG is a seed sequence generator. A coverage-driven seed generation algorithm has been proposed to generate the optimized seeds. The test sequence generated by SB-TPG is a single input change (SIC) sequence that can significantly reduce test power for test-per-clock built-in self-test (BIST). Further, seed-masking technique has been put forward to filter those power-consuming seeds, thus reducing test power for test-per-scan BIST. Experimental results show that SB-TPG can achieve high fault coverage with short test length, low power and small hardware overhead.     

A New Multi‐site Test for System‐on‐Chip Using Multi‐site Star Test Architecture

As the system‐on‐chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.     

Random Test Generation With Input Cube Avoidance

Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We investigate a complementary view whereby the goal is to avoid the assignment of certain input values in order not to prevent faults from being detected. We describe a procedure for computing input cubes (or incompletely specified input vectors) that should be avoided during test generation for target faults. We demonstrate that avoiding such input cubes leads to the detection of target faults after the application of limited numbers of random input vectors. This indicates that explicit test generation is not necessary once certain input values are precluded. Other potential uses of the computed input cubes are in a deterministic test generation procedure to reduce the search space, and during built-in test generation to preclude input vectors that will not lead to the detection of target faults. We consider stuck-at faults in full-scan circuits. We also extend the discussion to four-way bridging faults.      

一种基于编码的低硬件开销的测试数据压缩方法

提出了一种新的测试数据压缩/解压缩的算法,称为混合游程编码,它充分考虑了测试数据的压缩率、相应硬件解码电路的开销以及总的测试时间.该算法是基于变长-变长的编码方式,即把不同游程长度的字串映射成不同长度的代码字,可以得到一个很好的压缩率.同时为了进一步提高压缩率,还提出了一种不确定位填充方法和测试向量的排序算法,在编码压缩前对测试数据进行相应的预处理.另外,混合游程编码的研究过程中充分考虑到了硬件解码电路的设计,可以使硬件开销尽可能小,并减少总的测试时间.最后,ISCAS 89 benchmark电路的实验结果证明了所提算法的有效性.     

基于谱分析下的时间序列的平稳性检验

将时间序列分为S个子序列片断，用周期图方法估计时间序列的谱密度，在此基础上用3σ原理和两因素方差分析比较各子序列的异同，用以分别检验时间序列的均值函数和协方差函数的平稳性。较其它方法避免了复杂的计算，同时给出了检验统计量和判别准则，克服了人为主观因素的影响。     

An Efficient Test Data Compression Technique Based on Codes

提出了一种新的测试数据压缩/解压缩的算法,称为混合游程编码,它充分考虑了测试数据的压缩率、相应硬件解码电路的开销以及总的测试时间.该算法是基于变长-变长的编码方式,即把不同游程长度的字串映射成不同长度的代码字,可以得到一个很好的压缩率.同时为了进一步提高压缩率,还提出了一种不确定位填充方法和测试向量的排序算法,在编码压缩前对测试数据进行相应的预处理.另外,混合游程编码的研究过程中充分考虑到了硬件解码电路的设计,可以使硬件开销尽可能小,并减少总的测试时间.最后,ISCAS 89 benchmark电路的实验结果证明了所提算法的有效性.     

A robust O(N log n) algorithm for optimal decoding of first-orderΣ-Δ sequences

An exact recursive formula is derived to describe the structure of an ideal first-order Σ-Δ output sequence as a function of its input. Specifically, it is shown that every Σ-Δ sequence generated by the constant input x∈[0, 1] can be decomposed into a shorter E-A subsequence whose input x'∈[0, 1) may be used to recover that of the original Σ-Δ sequence. This formula is applied to develop an O(N log N) algorithm for decoding an N-length sequence. Without knowledge of the modulator's initial state, it exhibits an average improvement, over all initial states, of 4.2 dB in output signal-to-noise ratio (SNR) compared with a near-optimal linear finite impulse response (FIR) filter. The regularity of the ideal first-order Σ-Δ structure with constant inputs permits the algorithm to be extended to bandlimited and noise-corrupted data. A simple error correction procedure is demonstrated, and it is shown that the recursive algorithm can outperform FIR filters on sequences of length N<64 having input SNRs as low as 30 dB     

On Concurrent Test of Core-Based SOC Design

In this paper, a method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based System-On-Chip (SOC) designs is presented. The primary objective for concurrent SOC test is to reduce test application time under the constraints of SOC pins and peak power consumption. The methodology used in this paper is not limited to any specific Test Access Mechanism (TAM). Additionally, it can also be applied to SOC budgeting at design phase to predict a tradeoff between test application time and SOC pins needed. The contribution of this paper is the formulation of the problem as a well-known 2-dimensional bin-packing problem. A best-fit heuristic algorithm is adopted to achieve optimal solution.     

基于变周期重播种LFSR的测试生成

基于重播种的LFSR结构的伪随机测试生成中包含的冗余测试序列较多,因而其测试序列长度仍较长,耗费测试时间长,测试效率不高。针对此状况,提出基于变周期重播种的LFSR结构的测试生成方法。该方法可以有效地跳过伪随机测试生成中的大量冗余测试序列。在保证电路测试故障覆盖率不变的条件下,缩短总测试序列的长度。分析结果表明,同定长重播种方法相比,该方法能以较少的硬件开销实现测试序列的精简,加快了测试的速度,提高了电路测试诊断的效率。     

Performance evaluation of an efficient reduced-complexity time synchronization approach for OFDM systems

This paper presents a performance analysis of a recently proposed preamble-based reduced-complexity (RC) two-stage synchronization technique. The preamble, composed of two identical subsequences, is first used to determine an uncertainty interval based on Cox and Schmidl algorithm. Then, a differential correlation-based metric is carried using a new sequence obtained by element wise multiplication of the preamble subsequence and a shifted version of it. This second step is performed to fine tune the coarse time estimate, by carrying the differential correlation-based metric over the uncertainty interval of limited width around the coarse estimate, thus leading to low computational load. In this paper, we first discuss some complexity issues of the RC approach compared to previously proposed algorithms. Then, we study the effect of the training sequence class and length choices on the synchronization performance in the case of multipath channels. The impact of the uncertainty interval width on the trade-off between performance and complexity is also studied. The two-stage approach was found to provide almost equal performance to those obtained by the most efficient differential correlation-based benchmarks. However, it has a very reduced computational load, equivalent to that of sliding correlation-based approaches.