共查询到20条相似文献,搜索用时 140 毫秒
1.
2.
3.
一种基于DDS芯片AD9850的信号源 总被引:18,自引:0,他引:18
直接数字合成 (DDS)是一种重要的频率合成技术 ,具有分辨率高、频率变换快等优点 ,在雷达及通信等领域有着广泛的应用前景。文中介绍了一种高性能DDS芯片AD985 0的基本原理和工作特点 ,阐述了如何利用此芯片设计一种频率在 0~ 5 0kHz内变化、相位正交的信号源 ,给出了AD985 0芯片和MCS5 1单片机的硬件接口和软件流程 相似文献
4.
5.
本文介绍了直接数字频率合成(DDS)技术的基本原理和高性能直接数字频率合成芯片AD9954的特性和内部结构,并对采用AD9954芯片和单片机构成的频率合成器实现频率、幅度控制的原理进行了分析。 相似文献
6.
直接数字频率合成技术 (DirectDigitalSynthesis ,简单DDS)是近年来发展起来的一种新型信号合成技术。由于采用了全数字结构 ,它具有合成信号相对频带宽、频率转换时间短、频率分辨率高及合成信号相位连接等优点。介绍了DDS的基本原理 ,详细描述了DDS芯片AD70 0 8特点 ,并给出了基于AD70 0 8芯片的 5MHz扫频信号发生器。 相似文献
7.
一种高精度直接数字式频率源的设计 总被引:1,自引:0,他引:1
郑毅 《电气电子教学学报》2003,25(4):45-47,66
直接数字频率合成(DDS)是近年来发展非常迅速的一种新型频率合成技术,它具有频率分辨率高、相位噪声低、频率切换时间短等特点。首先简要介绍DDS的工作原理及其性能,然后阐述如何利用AD9851芯片设计一个高精度直接数字式合成频率源。 相似文献
8.
本文在阐述频率合成基本原理的基础上,重点讨论锁相环数字频率合成技术,并以目前在移动通信中常用的锁相环频率合成芯片MB1504为例进行分析。 相似文献
9.
10.
频率合成技术是目前研制信号源的关键技术.该文介绍了一种基于直接数字频率合成(DDS)技术的正弦波方波信号源设计方案。该系统采用AD9850为核心芯片,以超低功耗单片机MSP430F5438为控制芯片,可输出频率范丽为1Hz-10MHz的正弦波和方波.且具有频率设定、多档步进调整和幅度调节的功能。结果表明,该方案设计的信... 相似文献
11.
杨建生 《电子工业专用设备》2007,36(2):58-62
芯片规模封装技术一直倍受高性能、小形状因素解决方案在各类应用中的关注。芯片规模封装与球栅阵列(BGA)封装之间的区别变得不可分辨,已成为“细间距BGA”的同义词。芯片规模封装成本也是业界关注的焦点之一。芯片规模晶圆级封装是提供小形状、高性能和低成本的最快途径。论述了集成无源器件加工、低成本化的晶圆级芯片规模封装技术。 相似文献
12.
Clearfield H.M. Young J.L. Wijeyesekera S.D. Logan E.A. 《Advanced Packaging, IEEE Transactions on》2000,23(2):247-251
Chip scale packaging continues to draw attention for applications that require high performance or small form factor solutions. The term chip scale package (CSP) has become synonymous with “fine pitch BGA” as the distinction between a ball grid array (EGA) and some chip scale packages becomes nearly indistinguishable. The cost of chip scale packages also continues to draw attention as one of the barriers to wide scale industry adoption. Sometimes lost in the chip scale debate is the discussion about wafer level chip scale packages, which offer the fastest path to small form factor, high performance and cost effective solutions. In this paper, we describe an approach to wafer level chip scale packaging that is an extension of integrated passive device processing, which results in low cost 相似文献
13.
14.
15.
The placement of error-correcting-code (ECC) systems on dynamic-RAM (DRAM) chips poses many practical problems, among which are increased access time and chip size. The authors describe an optimized, self-contained, and self-timed on-chip ECC system embedded in a high-speed 16-Mb DRAM chip. This chip also has redundant word and bit lines. The combination of redundancy and on-chip ECC produces a synergistic effect which results in a major increase in fault tolerance for the hard manufacturing defects. It also improves the reliability of the chip, regardless of manufacturing defects. This improvement is attained with only a 5-ns penalty in access time and an 11% increase in chip size 相似文献
16.
文章基于目前公钥密码加密芯片加密速度慢的缺点提出了一种新的方案,即根据一种改进的二次背包算法设计加密芯片。新的加密芯片由一块已有的DSPCore和我们自己所设计的计算单元组成。这样既可以发挥DSP软件扩展性好又可以加快加密速度。最后通过对整块芯片进行仿真得到了比较满意的性能指标。 相似文献
17.
RFID设备微小芯片视觉定位算法研究与实现 总被引:1,自引:0,他引:1
微小芯片的精密操作是电子封装设备的关键技术,其中芯片的视觉定位是精密操作中的难点之一。为此研究了射频识别(RFID)标签封装设备中芯片的视觉定位,提出一种基于Hough变换的微小芯片视觉定位算法。该算法利用So-bel边缘检测方法提取出芯片的边缘,采用Hough变换提取芯片4个角圆心坐标,以此计算芯片的中心绕贴装轴心的旋转角度和平移距离,实现芯片的精密定位。目前提出的算法已成功应用到RFID封装设备HEI-D3000上,实验结果表明,与常规的模板匹配算法相比,这里提出的芯片快速定位算法效率高、稳定性好,对光照不均、纹理特征以及芯片大角度旋转不敏感,提高了RFID封装设备在市场中的竞争力。 相似文献
18.
为了减少人眼判读对血型分析结果的人为因素干扰,设计了自动血型图像判读系统。对该系统所采用的硬件组成和软件识别算法进行研究。采用DSP芯片、SDRAM芯片、FLASH芯片、图像编码芯片、图像解码芯片、U盘/SD卡读写芯片等设计了本系统的硬件;采用灰度变换、平滑滤波、模板匹配、阈值处理、颜色分量提取等算法设计了本系统的软件识别算法。实验结果表明:本系统采用的算法可以有效地分割出血型卡中的微柱小管,并实现红细胞分布的有效识别;同时,采用颜色分量提取的方法可以有效地区分血型卡的种类。本系统基本满足血型图像自动判读的要求。 相似文献
19.
Saito H. Nakajima M. Okamoto T. Yamada Y. Ohuchi A. Iguchi N. Sakamoto T. Yamaguchi K. Mizuno M. 《Solid-State Circuits, IEEE Journal of》2010,45(1):15-22
A dynamic-reconfigurable memory chip is fabricated, by which on-chip memories of an SoC chip can be moved to the memory chip to increase the efficiency of memory usage, and stacked on a logic chip by using three dimensional packaging technology. In the memory chip, many RAM-macros are arrayed and they are connected through two dimensional mesh network interconnects. By using memory-specified network interconnects, area overhead of network interconnects for the memory chip is reduced by 63% and the latency overhead by 43%. Signal lines between the two chips are directly connected by 10-?m-pitch inter-chip electrodes, resulting in fast and low-energy inter-chip transmission. 相似文献
20.
A system level implementation of a large area hybrid detector is presented. The detector used in this system consists of an array of hydrogenated amorphous silicon photodiodes directly connected to a CMOS readout chip, which is vertically integrated over the sensor array using flip-chip bonding. In particular, the proposed solution relies on a stack of interconnection layers, deposited on top of the photodiode array, to route each individual pixel output to a separate pre-amplifier channel. This avoids the need for a geometrical matching between the sensor array and the chip contact pads. As a consequence, conventional non-pixelated readout chip can be used and easy-scalable large area detectors can be produced. The CMOS chip is connected to an electronic board, providing the interfaces needed to read the signals as well as providing voltage references and power to the chip. The signals are collected and pre-processed by an FPGA chip, providing a very compact and flexible setup. 相似文献