A Low-Noise Terahertz SIS Mixer Incorporating a Waveguide Directional Coupler for LO Injection

We have developed a low-noise heterodyne waveguide Superconductor-Insulator-Superconductor (SIS) mixer with a novel local oscillator (LO) injection scheme for the Atacama Large Millimeter/submillimeter Array (ALMA) band 10, over the frequency range 0.78–0.95 THz. The SIS mixer uses radio frequency (RF) and LO receiving horns separately and a waveguide 10 dB LO coupler integrated in the mixer block. The insertion loss of the waveguide and coupling factor of the coupler were evaluated at terahertz frequencies at both room and cryogenic temperatures. The double-sideband (DSB) receiver noise temperatures were below 330 K (7.5hf/k _B) at LO frequencies in the range 0.801–0.945 THz. The minimum temperature was 221 K at 0.873 THz over the intermediate frequency range of 4–12 GHz at an operating temperature of 4 K. This waveguide heterodyne SIS mixer exhibits great potential for practical applications, such as high-frequency receivers of the ALMA.     

IF Conversion Gain of Glow Discharge Lamps X-Band Mixers for High LO Power Levels

Inexpensive glow discharge indicator lamps mounted in a waveguide mount are investgated as mixers at relatively high X-band Iocal oscillator (LO) power levels. The IF conversion efficiency was found to drop off for LO power levels greater than about 30-40 mW, although no damage occurs to the lamps at higher power levels. Because of the small lamp size relative to waveguide cross section, sensitivity is much less than in the free space configuration. For many reasons the use of such devices as mixers should be much more promising at millimeter-wave frequencies than at microwave frequencies.     

A Tuning Circuit with Two Half-Wave Distributed Junctions for All-NbN SIS Mixers

A novel broadband tuning circuit composed of two low-current-density half-wave NbN/MgO/NbN tunnel junctions connected by a half-wave NbN/MgO/NbN microstrip line has been successfully tested in a quasi-optical mixer at frequencies above 700 GHz. The circuit had a designed center frequency of 870 GHz, was integrated in a center-fed twin-slot antenna, and was fed via a quarter-wave impedance transformer. Heterodyne measurments showed double-side-band receiver noise temperatures equivalent to 6-9 quanta from 675 to 810 GHz for a mixer with a current density of 6.7 kA/cm². The RF bandwidth was broader than that of a conventional mixer using a full-wave junction with the same current density.     

Performance of Arrays of SIS Junctions in Heterodyne Mixers

We have made a systematic experimental study of the performance of millimeter-wave quasiparticle heterodyne mixers which use arrays of SIS tunnel junctions. Sets of arrays with N =1, 5, 10, 25, and 50 junctions in series were fabricated by photolithography. All of the arrays in a given set were made on a single silicon wafer so that their response time parameter omega/sub S/R/sub N/C would be the same. Junction areas were scaled so that the total impedance was the same for each array in a set. Sets of arrays from four wafers with values of omega/sub S/R/sub N/C ranging from 2.6 to 13 were evaluated in mixers at 33 and 36 GHz. These measurements showed that the signal power required to saturate the mixers varies as N/sup 2/ and that the conversion efficiency is nearly independent of N for all values of omega/sub S/R/sub N/C. The mixer noise temperature is independent of N for large values of omega/sub S/R/sub N/C. Therefore, the dynamic range of an SIS quasiparticle mixer can increase in proportion to N/sup 2/. For small values of as omega/sub S/R/sub N/C, however, the mixer noise increases systematically with N. This correlation suggests that the junction capacitance affects the coupling between junctions that can contribute to the noise.     

Simulation of Sub-harmonic SIS Mixers with a Full Five-Port Model

The performance of superconductor-insulator-superconductor (SIS) sub-harmonic mixers is thoroughly investigated in this paper. On account of the importance of the harmonic effect, a full five-port model combined with an enhanced Newton solution is applied to calculate the local oscillator (LO) waveform. The mixer performance is studied as functions of principal parameters including the embedding admittances, LO power and bias voltage. The results are compared with those from the quasi five-port model.     

A Novel Circuit Architecture for High Performance of High-order Subharmonic Mixers

A novel circuit architecture for high performance of high-order subharmonic (SH) mixers is proposed in this paper. According to the specified harmonic mixing order, one or more mixer diodes sub-arrays and corresponding power divider as well as phase shift network for RF and LO signals are arranged in the circuit. This proposed SH mixer circuit has improved conversion loss, wide dynamic range and high port isolation for high-order SH mixers. By phase cancellation of idle frequencies, the proposed SH mixer circuit can eliminate complicated design procedure of idle frequency circuits; by phase cancellation of leakage LO power to RF and IF port, and leakage RF power to LO port, the mixer circuit can get high port isolation in LO-IF/RF and RF-LO. The increased antiparallel diode pairs in each sub-array will also lead to well performance by lowering effective series resistance. The proposed SH mixer circuit can be easily realized with power divider and phase shift network for RF and LO signals.     

一种新的大信号射频功率器件建模方法

对小信号网络分析而言,单一的S参数已足够描述器件的特性.但对大信号网络分析而言,则需要更多的数学工具来描述器件的特性.本文采用了一个新的适用于描述大信号非线性特性的描述函数——非线性散射函数.利用非线性散射函数可以完成对大信号射频功率器件的精确建模.     

A Novel Three-Dimensional Packaging Method for Al-Metalized SiC Power Devices

A novel three-dimensional packaging method for Al-metalized SiC power devices has been developed by means of Au stud bumping technology and a subsequent vacuum reflow soldering process with Au-20Sn solder paste. Al-metalized electrodes of a SiC power chip can be robustly assembled to a direct bonded copper (DBC) substrate with this method. The bump shear strength of a Au stud bump on an Al electrode of a SiC chip increased with bonding temperature. The die shear strength of a SiC chip on the DBC substrate increased with the number of Au stud bumps which were preformed on the Al electrode. The bonded SiC-SBD chips on a DBC substrate were aged at 250 ${^circ}{rm C}$ in a vacuum furnace and the morphologies, die shear strength and electrical properties were investigated after a certain aging time. After 1000 h aging at 250 ${^circ}{rm C}$, the electrical resistance of the bonded SiC-SBD chips only increased about 0.4%, the residual die shear strength was much higher than that of the IEC749 (or JEITA) standard value, and little morphological change was observed by a micro-focus X-ray TV system. Very little diffusion between Au stud bumps and Au-20Sn solder was observed by scanning electron microscope (SEM) equipped with an energy dispersed X-ray analyzer (EDX). Intermetallic compounds (IMC) evolved at the interface of chip/solder and chip/Au stud bumps after 1000 h aging at 250 ${^circ}{rm C}$. With this method, power devices with Al bond pads can be three-dimensionally packaged.      

A Fast and Reliable Method for Computer Analysis of Microwave Mixers

In this paper, a numerical method is presented for analyzing microwave mixers. Particular consideration is given to the solution of the nonlinear pumping problem of real Schottky-barrier diodes. The new technique has a significantly improved convergence rate, which is demonstrated by means of direct comparisons with other methods. A convergence test procedure is proposed and applied which uses randomly generated harmonic impedances. The proposed numerical technique for solving the nonlinear and linear problem is extended to the analysis of balanced mixers. Fabricated planar balanced mixers are analyzed, both theoretically and experimentally, in a separate paper.     

A Low LO Power Mixer Utilizing the Body Effect

We propose a single-stacked CMOS mixer that can operate at low local oscillator (LO) power condition with a new switching mechanism. Gating the body terminal makes it possible for the mixer to operate in a more ideal switching mode by utilizing the body effect. Biasing at near pinch-off region gives rise to beneficial aspect, low power dissipation. This circuit is composed of all PMOS transistors which draw only 0.275 mA from a supply voltage of 1.8 V. This circuit features gain and noise enhancement characteristic, low power consumption, and simple topology. The proposed mixer achieves conversion gain of 18 dB, noise figure of 9.1 dB with 0 dBm LO power, and power consumption as low as 0.5 mW.     

微波混频器频域全非线性分析法

本文首先建立了微波混频器件的频域计算模型,以及相应的频域谱平衡迭代算法,然后对多频信号激励下的微波混频器进行了分析,以此研究了混频器的频率变换特性。     

一种新的DC-DC混合电源寿命预计方法

随着国产DC-DC混合电源产品的快速发展,其寿命越来越长,如何快速、准确地评价产品的寿命成为一项十分重要且紧迫的问题。瓷介电容和厚膜电阻是DC-DC混合电源中最容易发生失效的部位,是影响DC-DC混合电源寿命的关键元器件。通过对瓷介电容和厚膜电阻进行加速寿命试验,得到实际的失效率,进而通过可靠性预计的方法,获得DC-DC混合电源准确的寿命信息。     

Novel Miniature and Broadband Millimeter-Wave Monolithic Star Mixers

In this paper, three monolithic star mixers using a new miniature dual balun are proposed. The first one is a double spiral transformer mixer, and the second one is a trifilar transformer mixer. Both of these are fabricated using a commercial GaAs pseudomorphic HEMT process. The third is a 3-D transformer mixer, which is fabricated using a commercial CMOS process. These mixers exhibit bandwidths over 25-45 GHz (57%) with local oscillator isolations better than 20 dB. These star mixers are smaller than (lambda/6timeslambda/6) for the mixer core area. Compared with traditional star mixers, these mixers demonstrate 80% size reduction, and achieve good performance with the smallest chip size among all star mixers using monolithic microwave integrated circuit processes.     

A Novel Three-Phase PFC Rectifier Using a Harmonic Current Injection Method

This paper proposes a novel circuit topology for a three-phase power factor correction (PFC) rectifier using a harmonics current injection method. In consideration of lower cost, the harmonics injection method is more suitable than a conventional six-arm pulse width modulation (PWM) rectifier. The harmonics injection current is simply generated by only one switching leg. As a result, the proposed circuit has the advantage of only two switches. An optimal injection current is achieved in order to obtain an input current of sinusoidal waveforms. This paper discusses the basic operation and optimal design method for the proposed circuit. In addition, the validity of the proposed circuit is confirmed by simulation and experimental results. An input current of almost sinusoidal waveform was obtained and an input current total harmonic distortion (THD) of 8.5% was obtained at a load of approximately 1 kW.     

A Novel Control Method for Piezoelectric-Transformer Based Power Supplies Assuring Zero-Voltage-Switching Operation

In this paper, a new control strategy that allows zero-voltage-switching (ZVS) operation of power converters using piezoelectric transformers (PTs) is proposed. The control circuit operates in a closed loop by measuring the phase between the PTs resonant current and the switching pattern and adjusting the switching frequency to the optimum value so that ZVS operation is assured. An innovative nonlinear regulator based on an analog multiplexer is presented. The regulator automatically swaps the signs of the sensed signal and the reference signal to allow generation of the adequate control action. A laboratory prototype for a 6 W resonant inverter was tested; obtained experimental results are also shown.     

一种0.9V低电压低本振功率CMOS有源混频器

设计了一种可工作于0.9 V低电压和-5 dBm本振功率的CMOS有源混频器.通过在MOS管栅极和衬底间引入耦合电容,利用衬底效应加快MOS管的导通和截止,使开关对的开关状态更理想,有效地降低混频器的噪声并提高其线性特性.采用0.18 μm CMOS工艺设计,在2.45 GHz本振信号和2.44 GHz射频信号输入下,实验结果表明该混频器可有效地实现混频且具有较好的性能指标:电压转换增益为12.4 dB,输入三阶截断点为-0.6 dBm,输入1dB压缩点为-3.4 dBm,单边带噪声系数为12 dB.     

大脉宽微波功率组件瞬态热阻的新型计算方法

微波功率组件通常在脉冲条件下工作,当脉宽时间超过芯片响应时间时,传统基于线性叠加原理的瞬态热阻计算方法将导致结果显著偏小.根据微波功率组件脉冲均一重复的特征,结合组件瞬态升温曲线,文中提出了一种求解隐式方程的新型瞬态热阻计算方法.对比发现,在所有脉宽范围内新方法的计算精度均高于传统方法,尤其在大脉宽条件下更明显.该方法...     

A Novel Power Optimization Method by Minimum Comparator Number Algorithm for Pipeline ADCs

The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.     

Effect of Magnetic Field on Performance of SIS Mixers Measured at 385–500 GHz

We have investigated the effect of a moderately strong magnetic field (up to 1200 Gauss, 13 quantum fluxes within a single junction) on the heterodyne mixing performance of a 385-500GHz superconductor-insulator-superconductor mixer. Both experimental and numerical results indicate that the mixer conversion gain can be significantly reduced by a magnetic field. Surprisingly, the mixer noise shows very weak dependence. The overall receiver noise increase is merely caused by the intermediate frequency noise contribution amplified by a factor of gain reduction. At the expense of little system noise degradation, a relatively strong magnet field can make the mixer more stable at the bias point corresponding to its noise minimum     

A Novel Method for Power Analysis Based on Combinational Logic in Block Cipher Circuit

In this paper, we propose a method that builds power model template according to input transi- tions of combinatorial logic circuit. By computing its cor- relation with the overall power consumption of a crypto- graphic circuit, we are able to recover the secret key. Sev- eral simulation-based experiments have been conducted, which verifies the feasibility of our method and shows that the combinatorial logic is also faced with the problem of information leakage in power analysis cases. Compared with DPA （Differential power analysis） and CPA （Corre- lation power analysis）, our attack is fairly effective against the cryptographic circuits whose protection is only imple- mented on the register parts of the sequential circuit. In addition, a few topics for further research, as well as the ad- vices for more precise power model and countermeasures, are presented at the end of the paper.