Obtaining FPGA soft error rate in high performance information systems

Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. The vulnerability of FPGA-based designs to soft errors is higher than ASIC implementations since the majority of chip real estate is dedicated to memory bits, configuration bits, and user bits. Moreover, Single Event Upsets (SEUs) in the configuration bits of SRAM-based FPGAs result in permanent errors in the mapped design.FPGAs are widely used in the implementation of high performance information systems. Since the reliability requirements of these high performance information sub-systems are very stringent, the reliability of the FPGA chips used in the design of such systems plays a critical role in the overall system reliability. In this paper, we compare and validate the soft error rate of FPGA-based designs used in the Logical Unit Module board of a commercial information system with the field error rates obtained from actual field failure data. This comparison confirms that our analytical tool is very accurate (there is an 81% overlap in FIT rate range obtained with our analytical modeling framework and the field failure data studied). It can be used for identifying vulnerable modules within the FPGA for cost-effective reliability improvement.     

A fast,flexible, and easy-to-develop FPGA-based fault injection technique

By technology down scaling in nowadays digital circuits, their sensitivity to radiation effects increases, making the occurrence of soft errors more probable. As a consequence, soft error rate estimation of complex circuits such as processors is becoming an important issue in safety- and mission-critical applications. Fault injection is a well-known and widely used approach for soft error rate estimation. Development of previous FPGA-based fault injection techniques is very time consuming mainly because they do not adequately exploit supplementary FPGA tools. This paper proposes an easy-to-develop and flexible FPGA-based fault injection technique. This technique utilizes debugging facilities of Altera FPGAs in order to inject single event upset (SEU) and multiple bit upset (MBU) fault models in both flip-flops and memory units. As this technique uses FPGA built-in facilities, it imposes negligible performance and area overheads on the system. The experimental results show that the proposed technique is on average four orders of magnitude faster than a pure simulation-based fault injection. These features make the proposed technique applicable to industrial-scale circuits.     

DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs

Registers are one of the circuit elements that can be affected by soft errors. To ensure that soft errors do not affect the system functionality, Triple Modular Redundancy (TMR) is commonly used to protect registers. TMR can effectively protect against errors affecting a single flip-flop and has a low overhead in terms of circuit delay. The main drawback of TMR is that it requires more than three times the original circuit area as the flip-flops are triplicated and additional voting logic is inserted. Another alternative is to protect registers using Error Correction Codes (ECCs), but those typically require a large circuit delay overhead and are not suitable for high speed implementations. In this paper, DMR + an alternative to TMR to protect registers in FPGAs, is presented. The proposed scheme exploits the FPGA structure to achieve a reduction in the FPGA resources (LUTs and Flip-Flops) at the cost of a certain overhead in delay. DMR + can correct all single bit errors like TMR but is more vulnerable to multiple bit errors. To evaluate the benefits, the DMR + technique has been implemented and compared with TMR considering standalone registers and also some simple designs.     

Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs

Asynchronous serial transceivers have been recently used for data serializing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the asynchronous serial transmission but they have serious challenges to use this technology. In this paper, we present a new FPGA architecture corresponding with a new routing algorithm to use the asynchronous data serializing technique in modern FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (18.81% and 48.73%, respectively) by using the asynchronous data serializing without any performance degradation in cost of reasonable overhead in area and power consumption. The resulting improvements will increase for larger and more complex FPGAs.     

Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations

In order to meet superior performance metrics along with denser logic integration and device miniaturization, FPGAs have become more susceptible to transistor related aging, coupled with manufacturing defects owing to increased complexity in photolithographic techniques, thereby reducing the reliability and lifetime. In this paper, we propose certain built-in circuit techniques that are integrated with the original design, to localize the source of any hard or soft errors, if any, with tolerable penalty in performance, against acceptable time and/or hardware redundancy. Circuit realization on FPGA has been achieved through primitive instantiation and constrained placement, such that the exact location from which the fault has emanated can be traced, and bypassed for mapping any subsequent logic on the same FPGA. The adopted design paradigm which had earlier proved its potential for high performance FPGA based designs, has now been adopted to facilitate fault localization.     

Sequential Element Design With Built-In Soft Error Resilience

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements     

A Fault Tolerant Technique for FPGAs

In this paper we present a fault tolerant (FT) technique for field programmable gate arrays (FPGAs) that is based on incrementally reconfiguring circuits and applications that have been previously placed and routed. Our technique targets both logic faults and interconnect faults, and our algorithms can be applied to either static or run-time reconfigurable FPGAs. The algorithm for reconfiguring designs in the presence of logic faults uses a matching technique. The matching technique requires no preplaced, spare logic resources and is capable of handling groups of faults. Experimental results indicate there is little or no impact on circuit performance for low numbers of reconfigured logic blocks. For interconnect faults, we present a rip-up and reroute strategy. Our strategy is based on reading back the FPGA configuration memory, so no netlist is required for rerouting around faulty resources. Experimental results indicate high incremental routability for low numbers of interconnect faults. We also lay the foundation for applying our approach to yield enhancement.     

Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs

This paper studies the implementation of Double Error Correction Orthogonal Latin Squares (OLS) in Xilinx Field Programmable Gate Arrays (FPGAs). Several existing options to implement the decoder are considered and evaluated. The results show that the decoder complexity can be significantly optimized by appropriately selecting the implementation that is better suited to the internal FPGA structure. A new implementation tailored for the FPGA structure is proposed, which has a more efficient physical resource utilization compared with the existing ones. It is shown that the improvement on resource utilization is also highly correlated with the soft error vulnerability. The proposed decoder scheme has a reduced soft error cross section compared with other implementations. Based on these results, it seems that optimizing the ECC implementation for FPGAs can be effective and may be useful for other codes.     

Application-Specific Bridging Fault Testing of FPGAs

In this paper, a new technique for testing the interconnects of any arbitrary design mapped into an FPGA is presented. In this technique, only the configuration of logic blocks used in the design is changed, and the structure of the design remains unchanged. The test vector and configuration generation problem is systematically converted to a Boolean satisfiability (SAT) problem, and state of the art SAT-solvers are exploited for test vector and configuration generation. Experimental results on various benchmark circuits show that only two test configurations are required to test for all bridging faults, achieving 100% fault coverage, with respect to the fault list. Moreover, test vector and configuration generation time is less than a second for all benchmark designs.     

Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs

Dependability evaluation of embedded systems due to the integration of hardware and software parts is difficult to analyze. In this paper, we have proposed an experimental method to determine sensitivity to soft errors in an embedded system exploiting Altera SRAM-based FPGAs. The evaluation is performed using both the hardware and software parts of the embedded system in a single framework. To do this, the HDL hardware model of the target system as well as the C-written software codes of the target system, are required. Both permanent and transient faults are injected into the partially- or fully-synthesizable hardware of the target system and this can be performed during the design cycle of the system. The fault injection is composed of injecting SEUs into user design memory, and used configuration memory of the exploited FPGA. Using the experimental results, the sensitivity of Altera FPGAs to SEU faults are analyzed and derived. The analytical results reveal that the configuration memory is more significant than design memory to the SEUs due to the relative number of SRAM bits. Moreover, in this framework, in the case of injecting SEUs into user memory, the fault injection experiments are accelerated by the cooperation between a simulator and the FPGA.     

Fault Tolerance Mechanisms for FPGA-Based Regular Expression Matching

Traditional fault-tolerance techniques relying on spatial and temporal redundancy typically imply high power, delay, and area overheads. Cost-effective solutions often depend on system’s design and hardware platform at hand. Particularly for Field-Programmable Gate Arrays (FPGAs), soft errors on the configuration memory are a significant dependability threat. In this work, we present an extended and comprehensive fault tolerance mechanism especially suited for dealing with configuration faults on FPGA-based systems that must deal multiple failure modes. Each failure mode may present different criticality and probability of occurrence, and these properties are measured and exploited to provide low-cost solutions when compared to standard approaches such as triple modular redundancy. The exploited properties are typically found in critical monitoring systems that may trigger security- or safety-critical alarms and warnings in general. In such systems, failing to trigger an alarm when necessary is frequently regarded as more critical than providing an occasional false alarm. For instance, Regular Expression Matching (REM), a compute-intensive mechanism heavily used to perform Deep Packet Inspection in critical network applications, presents such properties, and it can be greatly accelerated by FPGAs to meet performance constraints in high-throughput networks. Therefore, we use FPGA-based REM engines as a case study to demonstrate the effectiveness of the proposed techniques. Additionally, a mutually-aware placement and scrubbing mechanism is introduced to reduce the repair time, improving the system reliability and availability. Experimental results show that the failure rate and the repair time can be reduced by 95 and 90% respectively while avoiding the costs of triplication.     

Characterizing,modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.     

Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.     

Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering

Modern FPGAs have a great market share in hardware prototyping, massive parallel systems and reconfigurable architectures. Although the field-programmability of FPGAs is an effective feature in the growth and diversity of their applications; it has caused security concerns for IPs/Designs on FPGAs. Recent researches show that a reliable mechanism is required to protect the IPs/applications on FPGAs against malicious manipulations during all stages of design lifecycle, especially when they are operating in the field. In this paper, we propose a new tamper-resistant design methodology (Security Path methodology) and a revised security-aware FPGA architecture. This methodology protects the configured design against tampering attacks in parallel with the normal operation of the circuit. When the attack is discovered, the normal data flow is obfuscated and the circuit is blocked. Experimental results show that this methodology provides near full coverage in tampering detection with overhead of 12.32 % in power, 12 % in delay and 38 % in area.     

FPGA上分布式Viterbi译码器实现技术

分布式Viterbi译码器是一种物理分散、逻辑统一的译码器。它在多个现场可编程阵列（FPGA）上实现多功能模块,以充分利用各FPGA的容裕量,达到系统资源分配的平衡。通过一个大规模设计中分布式Viterbi译码器实例的剖析,说明分布式结构设计的特点及实现技术。这里给出的Viterbi译码器实例对其他分布式FPGA器件的设计也有较高的参考价值。     

Very small FPGA application-specific instruction processor for AES

This paper presents two low-area designs for the advanced encryption standard on field-programmable gate arrays (FPGAs). Both these designs are believed to be the smallest to date. The first design is an 8-bit application-specific instruction processor, which supports key expansion (currently programmed for a 128-bit key), encipher and decipher. The design utilizes less than 60% of the resources of the smallest available Xilinx Spartan II FPGA (XC2S15). The average encipher-decipher throughput is 2.1 Mbps when clocked at 70 MHz. The design has numerous applications where low area and low power are priorities. The second design, using the Xilinx PicoBlaze soft core is included to provide an embedded 8-bit microcontroller comparison baseline.     

An efficient EDAC approach for handling multiple bit upsets in memory array

Ionizing radiation and electromagnetic interference (EMI) can cause single event upset (SEU) in memory elements. This threat is one of the major concerns when considering the design of electronic systems for critical applications. Single Error Correction - Double Error Detection (SEC-DED) codes can be used to avoid data corruption caused by soft errors, protecting the memory against single errors. However, the presence of multiple bit upsets is becoming more frequent as technology scales down. Hereafter, we present an Error Detection and Correction (EDAC) approach, namely Parity per Byte and Duplication (PBD), to protect data stored in memory. The technique was described in VHDL, coupled with the LEON3 softcore processor, and mapped into a commercial FPGA. The obtained results have shown that the proposed approach is very effective to detect and correct multiple bit-flips in memory arrays.     

Low-leakage soft error tolerant port-less configuration memory cells for FPGAs

As technology scales the area constraint is becoming less restrictive, but soft error rate and leakage current are drastically increased with technology down scaling. Therefore, in nano-scaled CMOS technology, the reduction of soft error rate and leakage current is the most important challenge in designing field programmable gate arrays (FPGA). To overcome these difficulties, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents a new family of configuration memory cells for FPGAs in nano-scaled CMOS technology. When zeros are stored in the cells, the injected glitch due to particle strike is removed from the stroked node by pull-up or pull-down network of the cells. Thus, our proposed cells are completely hardened and cannot flip from particle strikes at the sensitive cell nodes when zeros are stored in the cells. Furthermore, in the proposed cells, when zeros are stored, the sub-threshold leakage current components are reduced by using stacks of transistors in series. These new cells are port-less and the storage nodes of cells are manipulated through the transistors which apply the supply voltages to the cell. Simulation results show that the proposed cells are working correctly during their configuration and idle cycles and that our cells have a lower soft error rate and leakage current in 22-nm, as well as 65-nm technologies.