Blueshift of electroluminescence from single n-InP nanowire/p-Si heterojunctions due to the Burstein-Moss effect

Single-crystalline n-type InP nanowires (NWs) with different electron concentrations were synthesized on Si substrates via the vapor phase transport method. The electrical properties of the InP nanowires were investigated by fabricating and measuring single NW field-effect transistors (FETs). Single InP NW/p(+)-Si heterojunctions were fabricated, and electroluminescence (EL) spectra from them were studied. It was found that both the photoluminescence (PL) spectra of the InP NWs and the EL spectra of the heterojunctions blueshift from 920 to 775?nm when the electron concentrations of the InP NWs increase from 2 × 10(17) to 1.4 × 10(19)?cm(-3). The blueshifts can be attributed to the Burstein-Moss effect rather than the quantum confinement effect in the InP NWs. The large blueshifts observed in this study indicate a potential application of InP NWs in nano-multicolour displays.     

Synthesis and properties of single-crystal FeSi nanowires

We report for the first time the chemical synthesis of free-standing single-crystal nanowires (NWs) of FeSi, the only transition-metal Kondo insulator and the host structure for ferromagnetic semiconductor Fe(x)Co(1-x)Si. Straight and smooth FeSi nanowires are produced on silicon substrates covered with a thin layer of silicon oxide through the decomposition of the single-source organometallic precursor trans-Fe(SiCl3)2(CO)4 in a simple chemical vapor deposition process. Unlike typical vapor-liquid-solid (VLS) NW growth, FeSi NWs form without the addition of metal catalysts, have no catalyst tips, and depend strongly on the surface employed. X-ray spectroscopy verifies the identity and the room-temperature metallic nature of FeSi NWs. Room-temperature electrical transport measurements using NW devices show an average resistivity of 210 micro Omega cm, similar to the value for bulk FeSi. Investigations into the low-temperature physical properties of the first one-dimensional Kondo insulator and the possible new NW growth mechanism are underway. This unique synthetic approach to FeSi NWs will be generally applicable to many other transition-metal silicides.     

Strain accommodation in Ga-assisted GaAs nanowires grown on silicon (111)

We study the mechanism of lattice parameter accommodation and the structure of GaAs nanowires (NWs) grown on Si(111) substrates using the Ga-assisted growth mode in molecular beam epitaxy. These nanowires grow preferentially in the zincblende structure, but contain inclusions of wurtzite at the base. By means of grazing incidence x-ray diffraction and high-resolution transmission electron microscopy of the NW-substrate interface, we show that the lattice mismatch between the NW and the substrate is released immediately after the beginning of NW growth through the inclusion of misfit dislocations, and no pseudomorphic growth is obtained for NW diameters down to 10 nm. NWs with a diameter above 100 nm exhibit a rough interface towards the substrate, preventing complete plastic relaxation. Consequently, these NWs exhibit a residual compressive strain at their bottom. In contrast, NWs with a diameter of 50 nm and below are completely relaxed because the interface is smooth.     

Role of confinement on carrier transport in Ge-Si(x)Ge(1-x) core-shell nanowires

We examine the impact of shell content and the associated hole confinement on carrier transport in Ge-Si(x)Ge(1-x) core-shell nanowires (NWs). Using NWs with different Si(x)Ge(1-x) shell compositions (x = 0.5 and 0.7), we fabricate NW field-effect transistors (FETs) with highly doped source/drain and examine their characteristics dependence on shell content. The results demonstrate a 2-fold higher mobility at room temperature, and a 3-fold higher mobility at 77K in the NW FETs with higher (x = 0.7) Si shell content by comparison to those with lower (x = 0.5) Si shell content. Moreover, the carrier mobility shows a stronger temperature dependence in Ge-Si(x)Ge(1-x) core-shell NWs with high Si content, indicating a reduced charge impurity scattering. The results establish that carrier confinement plays a key role in realizing high mobility core-shell NW FETs.     

Growth of high-density titanium silicide nanowires in a single direction on a silicon surface

Understanding the growth mechanisms of nanowires is essential for their successful implementation in advanced devices applications. In situ ultrahigh-vacuum transmission electron microscopy has been applied to elucidate the interaction mechanisms of titanium disilicide nanowires (TiSi2 NWs) on Si(111) substrate. Two phenomena were observed: merging of the two NWs in the same direction, and collapse of one NW on a competing NW in a different direction when they meet at the ends. On the other hand, as one NW encounters the midsection of the other NW in a different direction, it recedes in favor of bulging of the other NW at the midsection. Since crystallographically the nanowires are favored to grow on Si(110) only in the [1 -1 0] direction, this crucial information has been fruitfully exploited to focus on the growth of a high density of long and high-aspect-ratio Ti silicide NWs parallel to the surface on Si(110) in a single direction. The achievement in growth of high-density NWs in a single direction represents a significant advance in realizing the vast potential for applications of silicide NWs in nanoelectronics devices.     

Development of ultra-high density silicon nanowire arrays for electronics applications

This article reviews our recent progress on ultra-high density nanowires (NWs) array-based electronics. The superlattice nanowire pattern transfer (SNAP) method is utilized to produce aligned, ultra-high density Si NW arrays. We fi rst cover processing and materials issues related to achieving bulk-like conductivity characteristics from 10 20 nm wide Si NWs. We then discuss Si NW-based fi eld-effect transistors (FETs). These NWs & NW FETs provide terrifi c building blocks for various electronic circuits with applications to memory, energy conversion, fundamental physics, logic, and others. We focus our discussion on complementary symmetry NW logic circuitry, since that provides the most demanding metrics for guiding nanofabrication. Issues such as controlling the density and spatial distribution of both p-and n-type dopants within NW arrays are discussed, as are general methods for achieving Ohmic contacts to both p-and n-type NWs. These various materials and nanofabrication advances are brought together to demonstrate energy effi cient, complementary symmetry NW logic circuits.     

Fabry–Perot Microcavity Modes in Single GaP/GaNP Core/Shell Nanowires

Semiconductor nanowires (NWs) are attracting increasing interest as nanobuilding blocks for optoelectronics and photonics. A novel material system that is highly suitable for these applications are GaNP NWs. In this article, we show that individual GaP/GaNP core/shell nanowires (NWs) grown by molecular beam epitaxy on Si substrates can act as Fabry‐Perot (FP) microcavities. This conclusion is based on results of microphotoluminescence (μ‐PL) measurements performed on individual NWs, which reveal periodic undulations of the PL intensity that follow an expected pattern of FP cavity modes. The cavity is concluded to be formed along the NW axis with the end facets acting as reflecting mirrors. The formation of the FP modes is shown to be facilitated by an increasing index contrast with the surrounding media. Spectral dependence of the group refractive index is also determined for the studied NWs. The observation of the FP microcavity modes in the GaP/GaNP core/shell NWs can be considered as a first step toward achieving lasing in this quasidirect bandgap semiconductor in the NW geometry.     

Selective area growth of GaN nanowires using metalorganic chemical vapor deposition on nano-patterned Si(111) formed by the etching of nano-sized Au droplets

We report on the selective area growth of GaN nanowires (NWs) on nano-patterned Si(111) substrates by metalorganic chemical vapor deposition. The nano-patterns were fabricated by the oxidation of Si followed by the etching process of Au nano-droplets. The size of formed nano-pattern on Si(111) substrate was corresponding to the size of Au nano-droplet, and the diameter of GaN NWs grown was similar to the diameter of fabricated nano-pattern. The interesting phenomenon of using the nano-patterned Si(111) substrates is the formation of very clear substrate surface even after the growth of GaN NWs. However, in the case of GaN NWs grown using Au nano-droplets, there was several nanoparticles including GaN bulk grains on the Si(111) substrates. The smooth surface morphology of nano-patterned Si(111) substrates was attributed to the presence of SiO₂ layer which prevents the formation of unnecessary GaN particles during the GaN NW growth. Therefore, we believe that nano-patterning method of Si(111) which was obtained by the oxidation of Si(111) substrate and subsequent Au etching process can be utilized to grow high-quality GaN NWs and its related nano-device applications.     

Influence of O contamination and Au cluster properties on the structural features of Si nanowires

Silicon nanowires (Si NWs) are the emerging nanostructures for future nanodevices. In this work we have prepared them by electron beam evaporation (EBE) through the vapor-liquid-solid (VLS) mechanism. We discuss the growth of epitaxial NWs by EBE and the possibility to control their orientation and length by changing the experimental conditions. Moreover, the effects of the surface contamination and of the Au cluster preparation on the NWs structural properties and density will be discussed. We demonstrate that any O contamination has to be avoided since just a very thin native SiO₂ layer stops ad-atom diffusion on the surface and inhibits the NWs growth. Au cluster preparation has a determinant role too: by varying the procedure for their formation, it is possible to change NWs density and length. In particular, we observed that by evaporating Au on the heated substrate, the droplets active to promote NW growth are immediately formed and a faster growth process starts. The growth rate is about a factor of 4 times higher than in the sample where the Au is evaporated at room temperature and the cluster formed after a subsequent thermal annealing. On the contrary, the slower process allows the atom arrangement and ordering in an epitaxial manner, and a precise control of NW orientation can be achieved.     

Ion beam doping of silicon nanowires

We demonstrate n- and p-type field-effect transistors based on Si nanowires (SiNWs) implanted with P and B at fluences as high as 10(15) cm (-2). Contrary to what would happen in bulk Si for similar fluences, in SiNWs this only induces a limited amount of amorphization and structural disorder, as shown by electrical transport and Raman measurements. We demonstrate that a fully crystalline structure can be recovered by thermal annealing at 800 degrees C. For not-annealed, as-implanted NWs, we correlate the onset of amorphization with an increase of phonon confinement in the NW core. This is ion-dependent and detectable for P-implantation only. Hysteresis is observed following both P and B implantation.     

Composition and local strain mapping in Au-catalyzed axial Si/Ge nanowires

For most applications, heterostructures in nanowires (NWs) with lattice mismatched materials are required and promise certain advantages thanks to lateral strain relaxation. The formation of Si/Ge axial heterojunctions is a challenging task to obtain straight, defect free and extended NWs. And the control of the interface will determine the future device properties. This paper reports the growth and analysis of NWs consisting of an axial Si/Ge heterostructure grown by a vapor-liquid-solid process. The composition gradient and the strain distribution at the heterointerface were measured by advanced quantitative electron microscopy methods with a resolution at the nanometer scale. The transition from pure Ge to pure Si shows an exponential slope with a transition width of 21?nm for a NW diameter of 31?nm. Although diffuse, the heterointerface makes possible strain engineering along the axis of the NW. The interface is dislocation-free and a tensile out-of-plane strain is noticeable in the Ge section of the NW, indicating a lattice accommodation. Experimental results were compared to finite element calculations.     

Lateral self-aligned p-type In2O3 nanowire arrays epitaxially grown on Si substrates

Lateral orientated growth of In2O3 nanowire (NW) and nanorod (NR) arrays has been achieved by a vapor transport and condensation method on (001) and (111) surfaces of Si substrates. The single crystalline In2O3 NWs and NRs were grown along [211] in parallel to the Si +/-[110] and lying in the substrate plane. The electrical measurements show that the In2O3 NWs are p-type semiconductor. By N+ doping, the resistivity of the In2O3 NWs has been tuned. The lateral self-aligned In2O3 NW and NR arrays on Si can offer some unique advantages for fabricating parallel nanodevices that can be integrated directly with silicon technology.     

Semi-transparent,flexible, and electrically conductive silicon mesh by capillarity-driven welding of vapor-liquid-solid-grown nanowires over large areas

Bottom-up synthesis of semiconductor nanowires (NWs) by the vapor-liquid-solid (VLS) mechanism has enabled diverse technological applications for these nanomaterials. Unlike metallic NWs, however, it has been challenging to form large-area interconnected NW networks. Here, we generate centimeter-scale meshes of mechanically and electrically interconnected Si NWs by sequentially growing, collapsing, and joining the NWs using a capillarity-driven welding mechanism. We fabricate meshes from VLS-grown NWs ranging in diameter from 20 to 100 nm and find that the meshes are three-dimensional with a thickness ranging from ~ 1 to ~ 10 microns depending on the NW diameter. Optical extinction measurements reveal that the networks are semi-transparent with a color that depends on the absorption and scattering characteristics of individual NWs. Moreover, active voltage contrast imaging of both centimeter- and micron-scale meshes reveals widespread electrical connectivity. Using a sacrificial layer, we demonstrate that the mesh can be liberated from the growth substrate, yielding a highly flexible and transparent film. Electrical transport measurements both on the growth substrate and on liberated, flexible films reveal electrical conduction across a centimeter scale with a sheet resistance of ~ 160–180 kΩ/square that does not change significantly upon bending. Given the ability to encode complex functionality in semiconductor NWs through the VLS process, we believe these meshes of networked NWs could find application as neuromorphic memory, electrode scaffolds, and bioelectronic interfaces.

     

Quantum confinement and electroluminescence in ultrathin silicon nanowires fabricated by a maskless etching technique

We present a novel approach for the direct synthesis of ultrathin Si nanowires (NWs) exhibiting room temperature light emission. The synthesis is based on a wet etching process assisted by a metal thin film. The thickness-dependent morphology of the metal layer produces uncovered nanometer-size regions which act as precursor sites for NW formation. The process is cheap, fast, maskless and compatible with Si technology. Very dense arrays of long (several micrometers) and small (diameter of 5-9?nm) NWs have been synthesized. An efficient room temperature luminescence, visible with the naked eye, is observed when NWs are optically excited, exhibiting a blue-shift with decreasing NW size in agreement with quantum confinement effects. A prototype device based on Si NWs has been fabricated showing a strong and stable electroluminescence at low voltages. The relevance and the perspectives of the reported results are discussed, opening the route toward novel applications of Si NWs.     

Lateral, Ge, nanowire growth on SiO2

Vapor-liquid-solid (VLS) nanowires (NWs) typically grow in [111] directions. Previously, the authors have demonstrated guided Si NW growth, engineering the VLS NWs to grow in a [110] direction against a SiO(2) surface. In this work, the authors demonstrate guided high-quality Ge nanowire growth against a SiO(2) surface in the substrate plane to bridge between two Si mesas. The authors explore the interfaces between a Ge NW and the two Si device-layer mesas and report high-quality, epitaxial interfaces between the Ge NW and both Si mesas.     

Si/a-Si core/shell nanowires as nonvolatile crossbar switches

Radial core/shell nanowires (NWs) represent an important class of nanoscale building blocks with substantial potential for exploring fundamental electronic properties and realizing novel device applications at the nanoscale. Here, we report the synthesis of crystalline silicon/amorphous silicon (Si/a-Si) core/shell NWs and studies of crossed Si/a-Si NW metal NW (Si/a-Si x M) devices and arrays. Room-temperature electrical measurements on single Si/a-Si x Ag NW devices exhibit bistable switching between high (off) and low (on) resistance states with well-defined switching threshold voltages, on/off ratios greater than 10(4), and current rectification in the on state. Temperature-dependent switching experiments suggest that rectification can be attributed to barriers to electric field-driven metal diffusion. Systematic studies of Si/a-Si x Ag NW devices show that (i) the bit size can be at least as small as 20 nm x 20 nm, (ii) the writing time is <100 ns, (iii) the retention time is >2 weeks, and (iv) devices can be switched >10(4) times without degradation in performance. In addition, studies of dense one-dimensional and two-dimensional Si/a-Si x Ag NW devices arrays fabricated on crystalline and plastic substrates show that elements within the arrays can be independently switched and read, and moreover that bends with radii of curvature as small as 0.3 cm cause little change in device characteristics. The Si/a-Si x Ag NW devices represent a highly scalable and promising nanodevice element for assembly and fabrication of dense nonvolatile memory and programmable nanoprocessors.     

Growth of InAs quantum dots on GaAs nanowires by metal organic chemical vapor deposition

InAs quantum dots (QDs) are grown epitaxially on Au-catalyst-grown GaAs nanowires (NWs) by metal organic chemical vapor deposition (MOCVD). These QDs are about 10-30 nm in diameter and several nanometers high, formed on the {112} side facets of the GaAs NWs. The QDs are very dense at the base of the NW and gradually sparser toward the top until disappearing at a distance of about 2 μm from the base. It can be concluded that these QDs are formed by adatom diffusion from the substrate as well as the sidewalls of the NWs. The critical diameter of the GaAs NW that is enough to form InAs QDs is between 120 and 160 nm according to incomplete statistics. We also find that these QDs exhibit zinc blende (ZB) structure that is consistent with that of the GaAs NW and their edges are faceted along particular surfaces. This hybrid structure may pave the way for the development of future nanowire-based optoelectronic devices.     

In(x)Ga(₁-x)As nanowires on silicon: one-dimensional heterogeneous epitaxy, bandgap engineering, and photovoltaics

We report on the one-dimensional (1D) heteroepitaxial growth of In(x)Ga(1-x)As (x = 0.2-1) nanowires (NWs) on silicon (Si) substrates over almost the entire composition range using metalorganic chemical vapor deposition (MOCVD) without catalysts or masks. The epitaxial growth takes place spontaneously producing uniform, nontapered, high aspect ratio NW arrays with a density exceeding 1 × 10(8)/cm(2). NW diameter (～30-250 nm) is inversely proportional to the lattice mismatch between In(x)Ga(1-x)As and Si (～4-11%), and can be further tuned by MOCVD growth condition. Remarkably, no dislocations have been found in all composition In(x)Ga(1-x)As NWs, even though massive stacking faults and twin planes are present. Indium rich NWs show more zinc-blende and Ga-rich NWs exhibit dominantly wurtzite polytype, as confirmed by scanning transmission electron microscopy (STEM) and photoluminescence spectra. Solar cells fabricated using an n-type In(0.3)Ga(0.7)As NW array on a p-type Si(111) substrate with a ～ 2.2% area coverage, operates at an open circuit voltage, V(oc), and a short circuit current density, J(sc), of 0.37 V and 12.9 mA/cm(2), respectively. This work represents the first systematic report on direct 1D heteroepitaxy of ternary In(x)Ga(1-x)As NWs on silicon substrate in a wide composition/bandgap range that can be used for wafer-scale monolithic heterogeneous integration for high performance photovoltaics.     

ZnO nanowire co-growth on SiO2 and C by carbothermal reduction and vapour advection

Vertically aligned ZnO nanowires (NWs) were grown on Au-nanocluster-seeded amorphous SiO(2) films by the advective transport and deposition of Zn vapours obtained from the carbothermal reaction of graphite and ZnO powders. Both the NW volume and visible-to-UV photoluminescence ratio were found to be strong functions of, and hence could be tailored by, the (ZnO+C) source-SiO(2) substrate distance. We observe C flakes on the ZnO NWs/SiO(2) substrates which exhibit short NWs that developed on both sides. The SiO(2) and C substrates/NW interfaces were studied in detail to determine growth mechanisms. NWs on Au-seeded SiO(2) were promoted by a rough ZnO seed layer whose formation was catalysed by the Au clusters. In contrast, NWs grew without any seed on C. A correlation comprising three orders of magnitude between the visible-to-UV photoluminescence intensity ratio and the NW volume is found, which results from a characteristic Zn partial pressure profile that fixes both O deficiency defect concentration and growth rate.     

Growth, defect formation, and morphology control of germanium-silicon semiconductor nanowire heterostructures

By the virtue of the nature of the vapor-liquid-solid (VLS) growth process in semiconductor nanowires (NWs) and their small size, the nucleation, propagation, and termination of stacking defects in NWs are dramatically different from that in thin films. We demonstrate germanium-silicon axial NW heterostructure growth by the VLS method with 100% composition modulation and use these structures as a platform to understand how defects in stacking sequence force the ledge nucleation site to be moved along or pinned at a single point on the triple-phase circumference, which in turn determines the NW morphology. Combining structural analysis and atomistic simulation of the nucleation and propagation of stacking defects, we explain these observations based on preferred nucleation sites during NW growth. The stacking defects are found to provide a fingerprint of the layer-by-layer growth process and reveal how the 19.5° kinking in semiconductor NWs observed at high Si growth rates results from a stacking-induced twin boundary formation at the NW edge. This study provides basic foundations for an atomic level understanding of crystalline and defective ledge nucleation and propagation during [111] oriented NW growth and improves understanding for control of fault nucleation and kinking in NWs.