A high-frequency fully differential BiCMOS operational amplifier

A high-frequency fully differential BiCMOS operational amplifier design for use in switched-capacitor circuits is presented. The operational amplifier is integrated in a 3.0-GHz, 2-μm BiCMOS process with an active die area of 1.0 mm×1.2 mm. This BiCMOS op amp offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45° phase margin, and a slew rate of 150 V/μs. The differential output range is 12 V. The circuit is operated from a ±5-V power supply and dissipates 125 mW. The op amp is unity-gain stable with 7 pF of capacitive loading at each output. The op amp is a two-stage, pole-split frequency compensated design that uses a PMOS input stage for infinite input resistance and an n-p-n bipolar second stage for high gain and high bandwidth. The frequency compensation network serves both the differential- and common-mode amplifiers so the differential- and common-mode amplifier dynamics are similar. A dynamic switched-capacitor common-mode feedback scheme is used to set the output common-mode level of the first and second stages     

Digital-Compatible Testing Scheme for Operational Amplifier

This paper presents a digital-compatible testing scheme for operational amplifier (op amp). In the proposed scheme, the op amp device under test (DUT) is configured to a unity-gain buffer which is responded to a testing pulse, could be realized by a ring oscillator circuit. The output of the configured unity-gain buffer is digitized by simple digital counter and then the digitized counting number is compared to a predetermined critical value to evaluate the op amp DUT. The digitized counting number is sensitive to the specification of op amp DUT and easily to be observed in the digital domain. The testing parameters of testing setup of stimulus, testing result, testing accuracy, and testing time are also investigated to detail the proposed scheme. Digital compatibility and simplicity are main advantages of the proposed testing scheme. In addition, no complicated analog comparator and reference voltages are required. Behavioral and circuit level simulations are performed to show the effectiveness of the proposed scheme.     

Multistage amplifier topologies with nested Gm-Ccompensation

This paper presents a multistage amplifier for low-voltage applications (<2 V). The amplifier consists of simple (noncascode) low gain stages and is stabilized using a nested transconductance-capacitance compensation (NGCC) scheme. The resulting topology is similar to the well known nested Miller compensation (NMC) multistage amplifier, except that the proposed topology contains extra G _m feedforward stages which are used to enhance the amplifier performance. The NGCC simplifies the transfer function of the proposed multistage amplifier which, in turn, simplifies its stability conditions. A comparison between the NGCC and NMC shows that the NGCC has wider bandwidth and is easier to stabilize. A four-stage NGCC amplifier has been fabricated using a 2-μm CMOS process and is tested using a ±1.0 V power supply. A dc gain of 100 dB has been measured. A gain bandwidth product of 1 MHz with 58° of phase margin and power of 1.4 mW can be achieved. The op amp occupies an active area of 0.22 mm². Step response shows that the op amp is stable     

High-speed GaAs operational amplifier

An operational amplifier has been designed and fabricated using GaAs MESFETs. This amplifier is a general-purpose monolithic GaAs op amp designed as as a stand-alone component. The amplifier has a differential input, an open-loop gain in excess of 60 dB, and is internally compensated. The high open-loop gain (60 dB at 100 kHz) was achieved by using gain stages with positive feedback. The op amp incorporates a current-mirror level-shifting stage which allows the op amp to operate over a wide power-supply range (/spl plusmn/5-9 V). Previous designs have diodes to achieve level shifting, a practice that precludes operation over a wide supply range. This op amp is a true analog to its silicon counterparts, but it has a higher gain-bandwidth product.     

High-gain microwatt composite cascode op amps

This article discusses the composite cascode stage, both single-ended and differential, operating in the weak inversion or moderate inversion region. The gain of the MOS composite cascode differential stage can exceed 100,000?V/V, a figure that has never been reported in the literature. For low-frequency applications, this configuration can be used to fabricate op amps that have high-gain, low-power and low-nonlinear distortion. Two different architectures, both having two gain stages are reported. The first op amp uses the Widlar architecture to achieve a gain of 117?dB, a power dissipation of 110?µW and uses a compensation capacitor of only 3.5?pF. The second op amp uses a class AB stage for the second and final stage and utilises the parasitic capacitance at the output of the first stage for compensation. This self-compensating op amp has a gain of 110?dB and a power dissipation of 21?µW.     

High performance op amps in a 40V BiCMOS process and their applications

This paper describes the design of three high-performance op amps in a 40V BiCMOS technology. The first circuit is a low-noise op amp with MOS inputs. A thermal noise level as low as with a 1/f noise corner frequency of 100 Hz is achieved. For applications that can tolerate a lower input impedance, a more economical bipolar input low-noise op amp has been designed, yielding an even better noise performance for source impedances up to 20 k. The third circuit is an internally compensated high-gain-bandwidth (GBW=15 MHz) op amp that can drive loads from 0 to 20 pF. A fourth-order low-pass switched-capacitor filter making use of the latter op amp is discussed next. Finally the applications of this 40V BiCMOS process are illustrated.     

Low-voltage operational amplifier with rail-to-rail input and output ranges

An operational amplifier is described which can perform precision signal operations in nearly the full supply voltage range, event when this range is as low as 1.5 V totally. The untrimmed input offset voltage is typically 0.3 mV in an input common-mode (CM) voltage range which extends beyond both supply voltages for about 200 mV. The output voltage can reach each supply rail within 150 mV. A nested-loop frequency-compensation scheme yields a stable unity-gain bandwidth of 0.6 MHz while the low-frequency open-loop voltage gain is 110 dB. The op amp is integrated in a standard low-cost bipolar process and the chip measures 1.5/spl times/1.7 mm/SUP 2/.     

低功耗恒定跨导轨对轨运算放大器设计技术研究

为了解决轨对轨运算放大器输入级跨导随共模输入电压变化的影响,采用实时共模电压监测技术,动态跟踪轨对轨运放输入级的跨导变化,通过对偏置电流的高精度定量补偿,从而实现了对输入级跨导的恒定性控制。基于0.18μm CMOS工艺进行了具体电路的设计实现,结果表明:在电源电压3.3 V、负载电阻100Ω、负载电容1 nF的条件下,运放增益为148 dB、相位裕度为61°、功耗为39.6μW,共模输入范围高达0~3.3 V,输入级跨导变化率仅为2.1%。     

New low-voltage class AB/AB CMOS op amp with rail-to-rail input/output swing

A new low-voltage CMOS Class AB/AB fully differential opamp with rail-to-rail input/output swing and supply voltage lower than two V/sub GS/ drops is presented. The scheme is based on combining floating-gate transistors and Class AB input and output stages. The op amp is characterized by low static power consumption and enhanced slew-rate. Moreover the proposed opamp does not suffer from typical reliability problems related to initial charge trapped in the floating-gate devices. Simulation and experimental results in 0.5-/spl mu/m CMOS technology verify the scheme operating with /spl plusmn/0.9-V supplies and close to rail-to-rail input and output swing.     

一种适合VLSI库的Rail-to-Rail运算放大器

介绍了一种适于 VLSI库单元的轨到轨 (Rail-to-Rail)运算放大器。低电压、低功耗、输入输出动态幅度达到 Rail-to-Rail的运放模块是研究的核心。文章分析了该运放模块的输入、输出级 ,并分析了 cascodedMiller频率补偿技术。芯片采用新加坡特许半导体制造公司 0 .6μm N阱 CMOS工艺 ,芯片面积 0 .0 2 4mm2 。测试结果表明 :该运放模块在 3 V工作电压下直流增益 90 d B,共模输入范围 -0 .4～ 4V,输出动态范围 0～ 2 .9V,单位增益带宽 7MHz,相位裕量 70°,静态功耗仅有 0 .3 m W,特别适合作为 VLSI的库单元     

Compact High Gain CMOS Op Amp Design using Comparators

This paper discusses the design of high gain, general purpose op amps. The op amp is based on a novel cascaded design using comparators and with structural simplicity approaching that of digital circuits. Ideally, the design tool presented here can be used to optimize gain and CMRR independent of the other op amp performance parameters. The designed op amp has 140 dB open-loop gain and 43 MHz unity gain frequency (GBW) in Berkeley Spice3f Level-2 simulation. The circuit is implemented using a 2.0 m nwell CMOS process through MOSIS. The op amp is self-biased and requires only power supplies of ±2.5 V. It occupies an area of 113 m×474 m.     

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

A technique that combines the high-frequency behavior of a single-stage op amp with the high DC gain of a multistage design is presented. This technique is based on the concept that a very high DC gain can be achieved in combination with any unity-gain frequency achievable by a (folded-) cascode design. Bode-plot measurements for an op amp realized in a 1.6-μm process show a DC gain of 90 dB and a unity-gain frequency of 116 MHz (16-pF load). Settling measurements with a feedback factor of 1/3 show a fast single-pole settling behavior corresponding to a closed-loop bandwidth of 18 MHz (35-pF load) and a settling accuracy better than 0.03%. This technique does not cause any loss in output voltage swing. At a supply voltage of 5.0 V an output swing of about 4.2 V is achieved without loss in DC gain. The above advantages are achieved with a 30% increase in chip area and a 15% increase in power consumption     

Operational amplifier with 1-V rail-to-rail multipath-driven outputstage

A bipolar operational amplifier (op amp) with a rail-to-rail multipath-driven output stage that operates at supply voltages down to 1 V is presented. The bandwidth of this output stage is as high as possible, viz, equal to that of one of the output transistors, loaded by the output capacitance. The output voltage can reach both supply rails within 100 mV and the output current is ±15 mA. The op amp is designed to be loaded by a 100-pF capacitor and the unity-gain bandwidth is 3.4 MHz at a 60° phase margin. The voltage gain is 117 dB and the CMRR is 100 dB. The frequency behavior of the multipath-driven (MPD) topology has an improved performance when compared to that of previously presented low-voltage output stages. A figure of merit F_M for low-voltage op amps has been defined as the bandwidth-power ratio     

A precision low-power analog front end in 180 nm CMOS for wireless implantable capacitive pressure sensors

This paper presents a new capacitance to voltage analog-front end (AFE) designed in 180 nm CMOS technology for wireless implantable applications. This AFE consists of a Low-dropout regulator (LDO), bandgap reference (BGR), switched-capacitor (SC) sampler, SC op-amp and oscillator. The LDO regulates the wireless power supply coming from an off-chip rectifier and provides a stable and accurate DC voltage. Capacitance is converted to a discrete voltage by a SC sampling circuit and then amplified by a SC op-amp. Both of SC sampling and SC op amp circuits form a correlated double sampling scheme. This AFE is designed to sense a capacitance range from 6 pF to 7 pF (300–1000 mmHg) corresponding to a 0.68 V–1.07 V discrete output voltage with a sampling frequency of 1.63 KHz. This AFE has a sensitivity of 0.39 mV/fF, average power consumption of 201 μW and 3.25% accuracy operating over a 2.1 V–3.3 V rectified wireless supply voltage and −40 °C ~125 °C temperature range.     

A dual current feedback op amp in CMOS technology

A CMOS circuit configuration implementing a current feedback or transimpedance op amp (CFB op amp) is presented. The architecture of the circuit is derived from similar bipolar CFB op amps. The properties of the CMOS implementation are similar to those of its bipolar counterparts, i.e., a high slew rate and a bandwidth which is independent of the closed-loop gain when the op amp is used with current feedback. Further, it is shown how two CFB op amps can be connected to achieve a non-slew-rate-limited voltage-mode op amp.     

A high-voltage IC for a transformerless trunk and subscriber line interface

A new high-voltage, junction-isolated, complementary bipolar technology has been used to fabricate an IC for a transformerless trunk and subscriber line interface. The new technology provides both vertical p-n-p and n-p-n transistors with BV/SUB CE0/ greater than 60 V, betas of 100, and f/SUB T/'s of 200 MHz. It permits the straightforward op amp realization of a new op amp circuit configuration in transformerless line circuits. The new configuration uses the high-voltage IC plus some low voltage control circuitry to provide limited current battery-feed, loop-closure detection, reverse-battery signaling, two-wire to four-wire conversion, lightning protection, power-down capability, and longitudinal performance which is independent of the battery-feed current magnitude.     

0．6VCMOS轨至轨运算放大器

为适应低压低功耗设计的应用,设计了一种超低电源电压的轨至轨CMOS运算放大器。采用N沟道差分对和共模电平偏移的P沟道差分对来实现轨至轨信号输入．。当输入信号的共模电平处于中间时,P沟道差分对的输入共模电平会由共模电平偏移电路降低,以使得P沟道差分对工作。采用对称运算放大器结构,并结合电平偏移电路来构成互补输入差分对。采用0．13μm的CMOS工艺制程,在0．6V电源电压下,HSpice模拟结果表明,带10pF电容负载时,运算放大器能实现轨至轨输入,其性能为：功耗390μw,直流增益60dB,单位增益带宽22MHz,相位裕度80°。     

Changing technology-banish the 741! [op amp]

Pick up a current electronics text and you're likely to find the 741 op amp not only used, but also showcased. It's the op amp of choice for lab experiments, treatment of innards, etc. This is truly amazing when you consider that the 741 is nearly 30 years old! Of course op amps should be presented they can be used to implement a remarkable range of circuit functions. An inexpensive op amp can give near-ideal performance in certain practical applications. Getting something to work is infectious-the first op amps gave a whole generation the opportunity to build analog functions that really worked. But, like all technologies, op amp development never ceased; there have been some serious developments over the last 30 years!     

Input switch configuration suitable for rail-to-rail operation ofswitched op amp circuits

A switch configuration to be used at the input of switched op amp circuits is introduced. The circuit is an extension of the gate-source bootstrapping technique such that rail-to-rail operation of the input switch becomes possible. Simulations show the usefulness of the proposed circuit down to 0.9 V     

Fully differential switched opamp with enhanced common modefeedback

A switched op amp with a fast common mode feedback (CMFB) circuit is presented. The proposed fully differential two stage amplifier needs CMFB only for the second stage, and thus a fast and simple passive CMFB circuit may be used. The amplifier is capable of 1 V operation and has no limitation on the maximum supply voltage