Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

A physical-based noise macromodel for fast simulation of switching noise generation

Efficient prediction of the substrate noise generated by large digital sections is currently a major challenge in System-on-a-Chip design. A macromodel to accurately and efficiently predict the substrate noise generated by digital standard cells is presented. The macromodel is generated from identification of the physical elements relevant to noise generation. Techniques to directly or indirectly compute the values of the elements in the cell macromodel are proposed. Using this macromodel, prediction of the noise generated by large digital sections can be easily done following a methodology based on high-level logic simulation. As a first step to validation, the macromodel accuracy is demonstrated in some circuits consisting of a reduced number of gates.     

Evolution of substrate noise generation mechanisms with CMOS technology scaling

Substrate noise is a major obstacle for single-chip integration of mixed-signal systems. To reduce this problem and to assess its evolution with CMOS technology scaling, the different mechanisms that generate substrate noise and their dependencies on different parameters need to be well understood. In this paper, we show that with downscaling of the technology, substrate noise due to supply coupling becomes the dominant coupling mechanism when the chip substrate is directly biased with the digital ground. With Kelvin ground substrate biasing on the other hand, source/drain capacitive coupling becomes the dominant coupling mechanism. Further, we show that with downscaling, the peak value of the supply coupling noise component becomes more dependent on the relative ratio of the switching capacitance to the nonswitching capacitance, which is formed by the circuit decoupling and the nonswitching circuit elements, rather than the Ldi/dt noise. These insights illustrated in a quantitative framework are believed to be very useful for the systematic use of digital low-noise design techniques in future CMOS technologies.     

A comparison by simulation and by measurement of the substrate noise generated by CMOS, CSL, and CBL digital circuits

Current-steering logic (CSL) and current-balanced logic (CBL) are logic families that have been proposed with the objective of reducing the substrate noise in mixed-signal integrated circuits. These two families are compared here with conventional CMOS by simulation, using a substrate model extracted from the layouts, and also by measurements on a test chip. With small, low-power cells, noise reduction of CSL and CBL with respect to CMOS is only marginal; the same result is obtained with large, high-power (buffer) cells, if the supply wire inductance is very low. For large cells with typical wire bonding supply inductance (of the order of 10 nH), CBL cells provide significant noise reduction and are more effective than CSL cells; these become even noisier than CMOS cells for large inductance values. The results here, considering the real substrate noise, are more reliable than previous evaluations considering only the amplitude of the supply current spikes.     

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /spl mu/m EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption.     

Characterisation and simulation of digital device electromagnetic noise under non-ambient temperature conditions

Presented is a new approach to the evaluation of electromagnetic emissions of electronics circuits under thermal stress. Near-field radiations, of essentially magnetic-type owing to the current switching of CMOS chips, have been measured in different external temperature conditions. Electrical equivalent models are proposed to investigate thermal influences on the electromagnetic compatibility characteristics of a printed circuit board excited by digital sources.     

On the Monte Carlo simulation of digital communication systems in Gaussian noise

We consider the general problem of the simulation of highly reliable systems operating in the presence of Gaussian noise. Our methodology uses importance sampling which has been shown to be a particularly effective method in the general discipline of rare-event simulation. The methods we propose are optimal in a certain sense, i.e., they are efficient. We also give a new class of simulation distributions that are universally efficient in the sense that they depend only on a single scalar parameter, regardless of the dimensionality of the underlying system or of the error sets to be simulated.     

Millimeter-wave generation and digital modulation in an InGaAs-InPheterojunction phototransistor: model and experimental characterizationof dynamics and noise

This paper describes the use of an InGaAs-InP photoheterojunction bipolar transistor (photo-HBT) for millimeter-wave generation and digital modulation. Optical mixing of two coherent signals generates the carrier, and a digital drive signal to the base is used for the modulation. We describe an advanced large signal model of the photo-HBT that takes into account distributed effects at high frequencies and all noise sources, including optical amplifier noise and noise correlations due to the high operation frequency and the nonlinear mixing processes. The model enables one to predict carrier-to-noise ratio dependence on frequency, optical power, and the transistor operating point. Frequency- and time-domain responses of the modulated millimeter- wave carrier and bit error rates are also calculated. Experiments at 10 and 45 GHz with modulation rates ranging between 50 Mb/s and 2.5 Gb/s were performed, and a superb fit to the calculated responses is found     

Analytical modeling and simulation of phase noise interference inOFDM-based digital television terrestrial broadcasting systems

This paper deals with the problem of modeling of phase noise in OFDM systems and the impact it may have on the bit error rate performance of such systems subject to a number of system variables and to a number of channel conditions which may be encountered when such systems are deployed for certain applications such as high speed wireless LANs and Digital Television Terrestrial Broadcasting (DTTB). The phase noise processes, the sources of which are the transmitter's and receiver's local oscillator, are modeled using what is believed to be commercially realizable phase noise masks. Such masks represent the long-term averaged power spectral densities of the local oscillator output signal     

Accurate and efficient simulation of synchronous digital switching noise in systems on a chip

A new method is presented to compress switching information in large synchronous digital circuits. This is combined with an efficient generation of digital cell library noise signatures and results in an accurate estimation of the switching noise in digital circuits. It provides a practical approach to generating the digital switching noise for simulating substrate coupling noise in mixed-signal ICs. Nearly two orders of magnitude reduction in the memory and simulation time are achieved using this approach without significant loss of accuracy.     

Real-time digital simulation for systems control

This paper discusses techniques employed in the discrete modeling of physical systems for digital simulation and control applications. Traditional numerical integration techniques provide accurate means of model making but prove too slow for real-time simulation of complex systems or systems with fast response. For rapid digital simulation, a simplified discrete approximation is sought for the linear integro-differential operators of a continuous system. This discrete operator, a digitized transfer function, yields difference equations hopefully permitting real-time approximation of continuous system performance on a digital computer. Determination of the discrete operator is the essential goal of each of the simulation schemes described herein, though differing initial assumptions and approximations alter the resulting forms. After a brief review of these approaches to simulation, techniques for improved approximations for linear system transforms and for discrete parameter optimization and identification are developed. The optimum discrete transfer function which minimizes the sum of error squared between a linear continuous system output and a linear discrete system output is obtained. By adjusting gain parameters in the discrete transfer function, the simulation result is shown to be improved for various inputs and system nonlinearities. Application of standard variational methods to optimize the desired parameters leads to a two-point nonlinear boundary-value problem which is resolved via the techniques of quasilinearization and differential approximation. The procedure for application of various simulation methods is summarized, and the effectiveness of the methods is shown by the simulation of a second-order, nonlinear system for various inputs and sample intervals.     

Transmission-line parameter approximation for digital simulation

This paper compares closed-form approximations for coplanar waveguide and microstrip transmission-line parameters to accurate measurements and full-wave calculations. We suggest improved approximations and demonstrate the limitations of our proposed and current approximations for the efficient simulation of digital interconnects     

Conditions for minimum noise generation in backward-wave amplifiers

The noise figure of a backward-wave amplifier can be minimized by optimizing the standing-wave ratio and position of the standing wave of noise power on the beam in the precircuit region. These optimum conditions are presented as detailed functions of tube parameters for the common types of backward-wave amplifiers and are compared with the characteristics of conventional traveling-wave tubes. The problem of achieving maximum tuning range while maintaining a noise figure close to the theoretical minimum value is discussed and general design criteria and methods are evolved. Although the voltage-tuned characteristics of backward-wave amplitiers impose rigorous requirements on the noise space-charge-wave transducer, it is shown that wide low-noise tuning ranges are possible even with no programming of the noise reducing electrodes.     

MOSFET substrate current model for circuit simulation

A simple, accurate MOSFET substrate current model suitable for a circuit simulator is presented. The effect of substrate bias on substrate current is modeled without introducing additional parameters. The accuracy of this model is demonstrated by its ability to fit the experimental data for both standard and LDD devices with average errors of less than 6%. The new model is compared with the substrate current models reported in the literature. In addition, the temperature dependence of the substrate current in the range of 0-120°C is also modeled. The new model has been implemented in a circuit-level hot-electron reliability simulator, and the results obtained from simulation of an inverter circuit are presented     

Discrete simulation of colored noise and stochastic processes and1/fα power law noise generation

This paper discusses techniques for generating digital sequences of noise which simulate processes with certain known properties or describing equations. Part I of the paper presents a review of stochastic processes and spectral estimation (with some new results) and a tutorial on simulating continuous noise processes with a known autospectral density or autocorrelation function. In defining these techniques for computer generating sequences, it also defines the necessary accuracy criteria. These methods are compared to some of the common techniques for noise generation and the problems, or advantages, of each are discussed. Finally, Part I presents results on simulating stochastic differential equations. A Runge-Kutta (RK) method is presented for numerically solving these equations. Part II of the paper discusses power law, or 1/f^α, noises. Such noise processes occur frequently in nature and, in many cases, with nonintegral values for α. A review of 1/f noises in devices and systems is followed by a discussion of the most common continuous 1/f noise models. The paper then presents a new digital model for power law noises. This model allows for very accurate and efficient computer generation of 1/f^α noises for any α. Many of the statistical properties of this model are discussed and compared to the previous continuous models. Lastly, a number of approximate techniques for generating power law noises are presented for rapid or real time simulation     

Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies

Substrate noise is a major obstacle for mixed-signal integration. While the power consumption scales linearly with the clock frequency, substrate noise does not have this scaling due to the resonances in the transfer function of the supply current to the substrate. This paper addresses a practical technique to estimate the substrate noise frequency spectrum of a large mixed-mode System-on-Chip (SoC) with multiple supplies and embedded memories. The results have been verified with substrate noise measurements on a 60-MHz 220-Kgates telecom SoC implemented in a 0.35 /spl mu/m CMOS process on an EPI-type substrate. We compute a linear chip-level substrate model together with the single-cycle representation of piecewise-linear noise sources of three supply regions used in this ASIC. Based on this model we accurately estimate the four major resonances in the substrate noise spectrum and their relative magnitudes with 2 dB relative error at the major resonance with respect to measurements. We also present substrate noise measurements at different operating modes of the WLAN receiver. These measurements show that output I/O buffers generate significant substrate noise where an increase of 44% is measured for substrate noise peak-to-peak value due to the additional simultaneous switching of six output I/O buffers with already fully switching datapath and two output I/Os.     

A BiCMOS active substrate probe-card technology for digital testing

An active substrate silicon probe card has been implemented by forming a polyimide membrane on a silicon substrate. The probe card combines tungsten probe tips and aluminum interconnects in the polyimide membrane with active test circuitry integrated in the substrate. A monolithic prototype of the probe card designed to enhance the capabilities of conventional digital test systems has been fabricated in a 2-μm BiCMOS technology. The benefits of the proposed probe-card technology could be further exploited by integrating the timing measurement unit of a digital tester into the probe-card substrate. An integrated tester architecture based on time digitization is described. A prototype of a tester combining a time digitizer and two test channels has been integrated in a 0.6 μm BiCMOS technology. The time digitizer in the experimental circuit employs a two-stage ring oscillator that is phase-locked to an external reference and makes use of phase interpolation to achieve a timing resolution of 90 ps     

Virtual view generation for 3D digital video

Virtual reality systems use digital models to provide interactive viewing. We present a 3D digital video system that attempts to provide the same capabilities for actual performances such as dancing. Recreating the original dynamic scene in 3D, the system allows photorealistic interactive playback from arbitrary viewpoints using video streams of a given scene from multiple perspectives