Golden-Free Processor Hardware Trojan Detection Using Bit Power Consistency Analysis

Processor is the core chip of modern information system, which is severely threatened by hardware Trojan. Side-channel analysis is the most promising method for hardware Trojan detection. However, most existing detection methods require golden chips as reference, which significantly increases the test cost and complexity. In this paper, we propose a golden-free detection method that exploits the bit power consistency of processor. For the data activated processor hardware Trojan, the power model of processor is modified. Two decomposition methods of power signal are proposed: the differential bit power consistency analysis and the contradictory equations solution. With the proposed method, each bit power can be calculated. The bit consistency based detection algorithms are proposed, the deviation boundaries are obtained by statistical analysis. Experimental measurements were done on field programmable gate array chip with open source 8051 core and hardware Trojans. The results showed that the differences between the two methods were very small. The data activated processor hardware Trojans were detected successfully.     

DSP系统的通信与控制接口设计

介绍了一种采用TMS320C548构造的低速率话音编解码DSP系统的通信与控制接口的设计方法。着重介绍了DSP系统内部通信与控制接口的硬件结构和软件设计方法。     

An all-digital bit detector for compact disc players

A bit detector is described which is suitable for integration using digital VLSI technology. In the bit detector the signal is sampled at a fixed clock frequency which is not related to the bit rate of the input signal. The incoming bits are detected by comparing the digitized input signal with the output of an all-digital phase-locked loop (PLL), which regenerates the bit clock that is present in the input signal. The design must be sufficiently robust to handle deviations in the physical size of the pits and disturbances like dropouts. Experimental optimization of the bit detector was performed with the aid of a hardware realization     

基于统计分析的SoC定点硬件加速器字长设计

在由通用RISC处理器核和附加定点硬件加速器构成的定点SoC(System-on-Chip)芯片体系架构基础上,提出了一种新颖的基于统计分析的定点硬件加速器字长设计方法。该方法利用统计参数在数学层面上求解计算出满足不同信噪比要求下的最小字长,能有效地降低芯片面积、功耗和制作成本,从而在没有DSP协处理器的低成本RISC处理器核SoC芯片上运行高计算复杂度应用。     

Implementation of media processors

Conventional standard processors do not correspond well to the characteristics of multimedia signal processor algorithms. Therefore, special architectural approaches are necessary for multimedia processors to deliver the required high processing power with efficient use of hardware resources. Programmable approaches offer a high degree of flexibility. In order to attain multimedia signal processor performance, architectural strategies for programmable processors are based on parallelization and adaptation principles. The future multimedia signal processor implementation hinges upon an optimal trade-off between the two design spaces, which can be effectively addressed by a codesign approach     

基于FPGA的32位浮点FFT处理器的设计

介绍了一种基于FPGA的1024点32位浮点FFT处理器的设计。采用改进的蝶形运算单元,减小了系统的硬件消耗,改善了系统的性能。详细讨论了32位浮点加法器/减法器、乘法器的分级流水技术,提高了系统性能。浮点算法的采用使得系统具有较高的处理精度。     

An NMOS Microprocessor for Analog Signal Processing

A special purpose microprocessor for real time processing of analog signals is described. Design and implementation of architecture allowing a user programmable and erasable read only memory (EPROM), a 25 bit digital processor and a 9 bit analog acquisition system on the same substrate is discussed. The relationship between the device's resources and specific signal processing building blocks is discussed.     

一种高资源效率的Fast-RCSC极化码译码器

针对现有极化码软输出译码器存在的高资源消耗与低资源效率,设计了一种快速低复杂度软取消(Fast Reduced Complexity Soft-Cancelation,Fast-RCSC)译码算法及其译码器硬件架构。Fast-RCSC算法对内部特殊结点进行完整计算,在减少译码周期的同时仍有较好译码性能。基于不同特殊结点公式之间存在相似性,进而通过对引入的特殊结点模块进行计算结果复用以及计算模块分时复用,减少特殊结点模块资源消耗。通过共用存储单元以及对不足存储单元数据宽度的数据进行合并,降低存储资源消耗。在华润上华(Central Semiconductor Manufacturing Corporation,CSMC)180nm工艺下综合结果表明,设计的译码器在码长为1024的情况下,面积为2.92mm²,资源效率为245.2Mbps/mm²,相比现有软输出译码器有不同程度的提升。     

A second-generation digital signal processor

The architecture, implementation, and applications of the TMS32020, a second-generation VLSI digital signal processor, are described. The processor has many special features which provide a significant advance over previous VLSI digital signal processors. Its multiprocessor capabilities further distinguish it, allowing for much more flexibility in overall system design. The architecture of the device allows a dual bus structure to be maintained on-chip, while external bus hardware requirements are minimized via the multiplexing of these buses externally. Some of the notable features incorporated onto the device include two large on-chip RAM blocks, large external program/data address spaces, single-cycle multiply/accumulate instructions, hardware and instructions for efficient memory management, and a versatile multiprocessor interface.     

基于NiosⅡ的光纤光栅传感系统解调技术的研究

基于Altera公司的32位嵌入式软核处理器NiosⅡ, 设计了一种四通道分布式光纤光栅传感网络的并行波长解调系统, 对解调系统的光路和硬件电路进行设计。解调系统的硬件电路以现场可编程门阵列(FPGA)为核心, 对整形为矩形脉冲的光电转换信号电压进行采集和信号处理, 可与上位机实现通用非同步收发传输器(UART)和通用串行总线(USB)通信, 在上位机上实现光纤光栅波长解调的动态显示和光栅中心波长标定, 可高速、高精度并行解调上百个外界被测信号。与目前具有同样功能的其他波长解调系统相比, 具有灵活、稳定、易维护、高速、高精度等优点, 可被应用到大型多点安全监测工程。给出具体的波长解调和标定的实例, 精度可达到±2 pm。     

高性能通用DSP寄存器扩展设计实现方法

本文提出一种高性能通用DSP扩展寄存器的设计及实现方法,该方法是我国自主研发的高性能通用DSP中实现寄存器堆扩展的一种新方法,其优点是在不影响现有指令集及指令机器码位宽的前提下,实现对处理器内部寄存器堆的成比例扩展。通过在我国自主研制DSP上的实际应用,证明了该扩展方法的有效性和实用性。     

MicroBlaze在AVS视频编码器软硬件协同设计中的应用

介绍了Xilinx公司的32位软核处理器MicroBlaze的结构,分析了国家音视频编解码标准AVS的技术特点,简述了软硬件协同设计的AVS视频编码器的体系结构及软硬件划分,重点阐述了在此体系中MicroBlaze处理器及相应软件的设计.     

ML7204和PicoBlaze软核处理器实现低速话音编解码系统

语音信号压缩编码是数字语音信号处理的主要方面．在现有的语音编码中,G．729A算法在8kb／s的码率下取得了较好的语音质量,具有广阔应用前景,因此提出采用PicoBlaze和ML7204实现G．729A语音压缩／解压详细的软硬件实现方案,并描述了G．729A语音编解码器ML7204的工作原理、性能、接口,以及FPGA内嵌IP核微处理器PicoBlaze的特点和使用方法。给出硬件电路设计原理,以及各部分的具体实现方法和原理图。并给出软件流程和主要代码。实验结果表明,系统提供话音点到点的时延仅为25mS,而语音质量平均意见MOS值达到4．2。在可懂度和清晰度等性能优异,该系统设计可应用于无线移动网、数字多路复用系统和计算机通信系统。     

基于NiosII的图形用户接口的设计

采用SOPC可编程片上系统技术,将NiosII32位处理器软核嵌入到FPGA现场可编程门阵列中。通过VGA显示控制模块,构建VGA显示系统,该系统具有体积小、功耗低、可靠性强等特点。同时,通过软硬件结合设计,使得系统更有利于修改和重复使用。     

高性能PLC专用指令集处理器设计与仿真

该高性能PLC专用指令集处理器采用自主设计的PLC专用指令集,符合PLC指令特征,可减少该PLC专用指令集处理器执行的指令数,并采用32位RISC体系结构加快PLC程序的执行速度.该高性能PLC专用指令集处理器采用哈佛总线结构,寄存器组采用位编址模式,位处理器可加速PLC布尔运算,功能块单元可提高功能块指令执行的精度,并采用四级流水线提高PLC指令的执行速度.现已完成了该高性能PLC专用指令集处理器的系统功能仿真,经测试仿真结果正确.     

Hardware/compiler codevelopment for an embedded media processor

Embedded and portable systems running multimedia applications create a new challenge for hardware architects. A microprocessor for such applications needs to be easy to program like a general-purpose processor and have the performance and power efficiency of a digital signal processor. This paper presents the codevelopment of the instruction set, the hardware, and the compiler for the Vector IRAM media processor. A vector architecture is used to exploit the data parallelism of multimedia programs, which allows the use of highly modular hardware and enables implementations that combine high performance, low power consumption, and reduced design complexity. It also leads to a compiler model that is efficient both in terms of performance and executable code size. The memory system for the vector processor is implemented using embedded DRAM technology, which provides high bandwidth in an integrated, cost-effective manner. The hardware and the compiler for this architecture make complementary contributions to the efficiency of the overall system. This paper explores the interactions and tradeoffs between them, as well as the enhancements to a vector architecture necessary for multimedia processing. We also describe how the architecture, design, and compiler features come together in a prototype system-on-a-chip, able to execute 3.2 billion operations per second per watt     

ADSP-TS101s技术在声纳信号处理中的应用

阐述了基于ADSP TS101s的声纳数字信号处理机的设计原理和实现方法。首先详细介绍了所设计的数字信号处理机的硬件电路结构及其强大的处理能力,然后叙述了程序设计流程及主控软件设计流程。该数字信号处理机采用3片ADSP TS101s,其通讯采用链路口互联方式,大大提高了系统的实时性;此外,其工作模式和系统参数可以通过主控计算机设置,方便用户使用。消声水池试验结果表明,该信号处理机能够满足声纳信号处理技术研究的要求。     

基于开源SoC平台的语音编解码器设计

以LEON开源SoC平台为基础,构建MELP声码器片上系统,给出实现过程中用到的一系列开源软、硬件开发组件。MELP算法是一种低比特率、高质量的语音编解码算法,面向移动设备和保密电话。选用LEON2做为SoC平台的处理器,MELP算法直接运行于LEON2处理器之上,计算密集型模块采用软硬件协同设计的思想,设计成隶属于总线的IP核。原型系统构建在Statix2-EP2S60开发板之上,采用CYGWIN作为工作站。同时给出传统NiosII处理器与LEON2的性能差异作为对比,这更预示着开源平台将成为未来SoC设计的一种新的选择。     

基于低硬件复杂度、高速CORDIC的SVD模块设计与实现

为降低实现高阶矩阵SVD时的硬件复杂度和计算延时,本文改进了CORDIC迭代结构,设计了一种用于SVD的低硬件复杂度、高速CORDIC计算单元.本文以2×2矩阵为例,基于XilinxVirtex6硬件平台设计并实现了使用优化后CORDIC计算单元的SVD模块,在19bit位宽下吞吐率达25.9Gbps.对比Xilinx IP core中同类模块,本文设计节省27.6%寄存器,27.7%查找表,实时性提高14%.对高阶矩阵,本文给出资源消耗趋势曲线,可证明优化后CORDIC计算单元能降低16阶矩阵SVD模块约40%的硬件复杂度.