A Family of Special Purpose Microprogrammable Digital Signal Processor IC's in an LPC Vocoder System

This paper discusses a family of digital signal processor integrated circuits designed to be the fundamental buitding blocks of an LPC vocoder, specifically LPC analysis, AMDF pitch extraction, and LPC synthesis. The IC's are custom designs intended to minimize silicon real estate for extremely high performance, novel DSP architectures, and high computational demand algorithms. Each IC shares a common architecture, that of a single internal data bus connecting input and output FIFO's, multiple arithmetic logic units, registers, and a microcode control bus. Each application is microprogrammed in register transfer language providing considerable flexibility. The CMOS design of each IC allows it to implement the high performance digital signal processing algorithms with minimal power consumption. The LPC synthesis IC allows various common filter topologies and residual excitation. The AMDF IC extracts the commonly used features for pitch and voicing. The LPC analyzer IC is microprogrammed to implement a flow form PARCOR LPC analysis. Algorithm architecture tradeoffs between computational load and memory are discussed.     

数字信号处理器分布式寄存器的写回设计

针对分布式寄存器文件应用于高性能超长指令字（VLIW）数字信号处理器而造成的分支流水线与写回控制信号的同步问题,提出了一种面向分布式本地寄存器文件的写回策略。其中包括指令执行周期的产生,写回信号缓存以及写回控制单元。采用了面积功耗性能评估方法,结果证明了该策略能充分发挥分布式寄存器文件在功耗方面的优势,相对于运用集中式寄存器文件可以减少50％的功耗,同时对于传统流水线写回控制方法可以节省60％的面积开销。     

浅谈数字信号处理器

本文对数字信号处理器进行了概括和分析,涉及了数字信号处理器的发展,并结合其软硬件特点,讨论了数字信号处理器的优势,提出了数字信号处理器现阶段所面临的问题和挑战。     

信号处理机的高速ADC模块动态性能在线测试

本文介绍了一种基于DSP技术在线测试信号处理机的高速ADC转换电路动态性能参数的方法。实现了电路板的ADC器件及周边电路性能的在线评估，对工程实践有一定的指导作用。     

基于ADSP-TS101的数字信号处理机实现

介绍一种由高速数字信号处理器(DSP)ADSP TS101实现的雷达数字信号处理机。作为雷达信号处理系统的一部分,主要利用快速傅里叶变换(FFT)算法完成雷达回波中各距离单元内运动目标的积累检测,另外还包括恒虚警处理。系统在设计中较好地利用了DSP芯片的内部资源,充分发挥了DSP芯片的性能,实现高速实时处理,达到较好的系统性能。     

基于优化DA算法的高速FIR滤波器设计

首先概述FIR滤波器的传统FPGA实现方式,在理论上分析基于FIR滤波器的DA(Distributed Arithmetic)算法及内部实现构架图,并提出可根据应用速率要求优化DA算法;最后通过MATLAB仿真和QuartusII仿真来验证其可行性。     

数字信号处理器芯片新进展

数字信号处理器(DSP)芯片及其应用近年来得到了飞速发展.简单地介绍了这一领域的领头羊德州仪器(TI)公司和模拟设备(AD)公司的几代DSP芯片的性能,重点比较了两公司市场上具有最高性能的浮点DSP产品:TI 的TMSC6701和AD 的ADSP-21160.     

一种高性能数字信号处理器TMS320C25

ＴＭＳ３２０Ｃ２５是一种高性能数字信号处理器。本文将介绍ＴＭＳ３２０Ｃ２５的内部结构、存储器组织、系统组成及应用。     

A High Performance LSI Digital Signal Processor for Communication

This paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSP's. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described in some detail.     

A CORDIC Arithmetic Processor Chip

A monolithic processor computes products, quotients, and several common transcendental functions. The algorithms are based on the well-known principles of "CORDIC," but recourse to a subtle novel corollary results in a scale factor of unity. Compared to older machines, the overhead burden is significantly reduced. Also, expansion of the functional repertoire beyond the circular domain, i.e., addition to the menu of hyperbolic and linear operations, is a relatively trivial matter, in terms of both hardware cost and execution time. A bulk CMOS technology with conservative layout rules is used for the sake of high reliability, low-power consumption, and good cycle speed.     

第一讲数字信号处理器概论

IC技术讲座是本刊2005年推出全新的技术类栏目。为了让工程师在设计开发中完善和拓展基础理论与系统知识，丰富应用经验，中电网同清华大学等北京知名院校共同创办了这个栏目，特约知名学者、教授以及著名半导体公司的应用工程师撰写，以系列讲座的方式对热点IC技术进行全面而系统的介绍，涵盖最新技术要点。最先开设的讲座将围绕三大课题：DSP、FPGA和嵌入式系统，每个课题都将连载6期。本期课题从数字信号处理器开始。     

TI数字信号处理器的ROM自举

主要讨论TI TMS320C6200系列通用数字信号处理器的芯片自举（boot)方式,针对开发者在实现自举时可能遇到的困难,给出了ROM自举的具体实现方法。     

TMS320C50数字信号处理器的特点及应用技巧

本文介绍了ＴＭＳ３２０Ｃ５０的特点，并结合作者的使用心得从ＴＭＳ３２０Ｃ５０中断的使用流水线的保护等五个方面探讨了ＴＭＳ３２０Ｃ５０的使用技巧。     

数字信号处理器中FFT的实现

本文深入探讨了FFT算法的特点,并对FFT算法在DSP上的实现方法进行了详细的分析.通过分析阐述并总结了利用DSP实现FFT算法的步骤及规律.     

一种数字信号处理器的地址生成单元设计

介绍了aDSP处理器中地址生成单元的设计。详细讨论了位倒序寻址模式、模块循环寻址模式和快速判零逻辑的设计实现，并使用门控时钟的方法来解决这些复杂结构引起的功耗增加问题。所有设计按照可综合要求进行RTL编码，经过VCS逻辑仿真和Design Compiler综合验证后成功应用于国家863项目高性能低功耗DSP中。     

A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation

As DSP (Digital Signal Processing) applications become more complex, there is also a growing need for new architectures supporting efficient high-level language compilers. We try to synthesize a new DSP processor architecture by adding several DSP processor specific features to a RISC core that has a compiler friendly structure, such as many general-purpose registers and orthogonal instructions. The synthesized digital signal processor supports single-cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping capabilities in addition to ordinary RISC instructions. The compiler for the new architecture is quickly implemented by developing a code-converter that modifies the assembly codes that are generated by the RISC compiler. The performance effects of adding each of these as well as all the combined features are evaluated using seven DSP-kernel benchmarks, a QCELP vocoder, and an MPEG video decoder. The effects of CPU clock frequency change due to the addition of these features are also considered. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.     

一种数字信号处理器的动态功耗管理方案

动态功耗管理是一种系统级低功耗设计技术，降低功耗的思路是根据系统当前负载动态调整时钟频率或者关闭时钟。文章以数字信号处理器为模型，提出了一种系统属性可调节的动态功耗管理方案，它支持通过软硬件配合对功耗进行灵活的动态管理，其管理策略采用了适应性预测算法，并引入非确定性因子。实验结果表明，该方案可以大大降低数字信号处理器的功耗。     

一种数字信号处理器地址产生单元的设计

针对数字信号处理中常用的循环寻址、位反序寻址等寻址方式,提出了一种数字信号处理器专用地址产生单元的设计实现,并对电路的结构做了进一步优化.仿真结果表明,提出的设计在不影响速度的前提下实现了面积和功耗的大幅减少,从而有效地提高了处理器的性能.     

一种可抗干扰的MFSK信号数字解码算法

多频制数字频率调制(MFSK)是2FSK方式的直接推广,这种信号的解调通常是在接收端将其还原为模拟信号,然后将频率变化转换为某一特征量幅度的变化,再加以判断,这类常规的解调方法效率和速度受到一定的制约且易受干扰。提出一种基于分析2FSK信号频谱特性的MFSK信号直接数字解码算法,该方法具有抗干扰能力强,快速简单,准确可靠且易于实现等优点,从理论上证明该算法的可行性,并证明了其有效性。     

高性能通用DSP寄存器扩展设计实现方法

本文提出一种高性能通用DSP扩展寄存器的设计及实现方法,该方法是我国自主研发的高性能通用DSP中实现寄存器堆扩展的一种新方法,其优点是在不影响现有指令集及指令机器码位宽的前提下,实现对处理器内部寄存器堆的成比例扩展。通过在我国自主研制DSP上的实际应用,证明了该扩展方法的有效性和实用性。