共查询到18条相似文献,搜索用时 156 毫秒
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随着深亚微米工艺技术条件的应用和芯片工作频率的不断提高 ,芯片互连线越来越成为一个限制芯片性能提高和集成度提高的关键因素 :互连线延迟正逐渐超过器件延迟 ;互连线上信号传输时由于串扰引起的信号完整性问题已成为深亚微米集成电路设计所面临的一个关键问题。文中分析了芯片中器件和互连线的延迟趋势 ,模拟分析了 0 .1 8μm CMOS工艺条件下的信号完整性问题。 相似文献
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《固体电子学研究与进展》2013,(6)
在频率源芯片窄带应用时,输出信号有较好的积分均方根抖动性能(RMS jitter),需要压控振荡器(VCO)有较出色的相噪特性。通过分析VCO的结构特点,确定电感是影响片上VCO相位噪声的关键性因素,通过HFSS软件建模的方式,将高品质因素(Q)值的键合线电感引入到片上VCO设计中。采用0.18μm SiGe BiCMOS工艺,设计了整块频率源芯片,并着重优化了VCO输出信号的相位噪声。经过实测,在开环状态下,VCO输出信号为2.2GHz,在1 MHz频偏处的相位噪声为-136dBc/Hz;在环路带宽80kHz,芯片输出信号相噪2.2GHz时,整颗芯片输出信号的带内本底噪声为-220dBc/Hz,杂散为-70dBc,积分均方根抖动为207.666fs。 相似文献
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研究了高速电路领域中的一类重要的电源完整性问题,即电源地平面之间激发的地弹噪声问题。地
弹噪声的存在严重破坏了电源/ 地平面的完整性,导致供电电压幅度的不稳定,严重之时甚至导致电路的误判。针
对这一问题,设计了一种超宽带电磁带隙结构。实验结果表明,这种电磁带隙结构可以在0. 5 ~5. 5GHz(11 倍频程)
频段内实现优于30dB 的噪声抑制能力。文章还探讨了带隙结构作为电源平面时信号传输的完整性。研究表明,如
果电路工作频率高达GHz 或更高,在电源/ 地平面采用这种带隙结构,可以有效地避免地弹噪声带来的影响,并保证
电源和信号的完整性。 相似文献
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半导体技术快速发展,双倍数据速率同步动态随机存取存储器(Double Data Rata Synchronous Dynamic
Random Access Memory, DDR SDRAM)的信号完整性问题已成为设计难点。文中提出了一种基于ANSYS 软
件和IBIS 5. 0 模型的DDR4 SDRAM 信号完整性仿真方法。利用IBIS 5. 0 模型中增加的复合电流(Composite Current)
、同步开关输出电流等数据,对DDR4 SDRAM 高速电路板的信号完整性进行更准确的仿真分析。仿真结果
表明:高速信号在经过印制板走线和器件封装后,信号摆幅和眼图都有明显恶化;在仿真电路的电源上增加去耦
电容后,信号抖动和收发端同步开关噪声(Synchronous Switching Noise, SSN)都得到明显改善;在不加去耦电容的
情况下,将输入信号由PRBS 码换成DBI 信号,接收端的同步开关噪声有所改善,器件功耗可以降为原来的一半。 相似文献
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As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis. 相似文献
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Xiaoning Qi Gyure A. Yansheng Luo Lo S.C. Shahram M. Singhal K. 《Electron Device Letters, IEEE》2006,27(8):696-698
The on-chip inductive impact on signal integrity has been a problem for designs in deep-submicrometer technologies. The inductive impact increases the clock skew, max timing, and noise of bus signals. In this letter, circuit simulations using silicon-validated macromodels show that there is a significant inductive impact on the signal max timing (/spl sim/ 10% pushout versus RC delay) and noise (/spl sim/2/spl times/RC noise). In nanometer technologies, process variations have become a concern. Results show that device and interconnect process variations add /spl sim/ 3% to the RLC max-timing impact. However, their impact on the RLC signal noise is not appreciable. Finally, inductive impact in 65- and 45-nm technologies is investigated, which indicates that the inductance impact will not diminish as technology scales. 相似文献
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Jun Fan Drewniak J.L. Knighten J.L. Smith N.W. Orlandi A. Van Doren T.P. Hubing T.H. DuBroff R.E. 《Electromagnetic Compatibility, IEEE Transactions on》2001,43(4):588-599
Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach 相似文献
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为了能够消除高速PCB技术中信号完整性的问题,需要在高速PCB设计过程中解决时序、噪声、电磁干扰等关键问题.研究了HDMI高清音视频系统的高速PCB设计过程中出现的串扰、电磁干扰、振铃和电源完整性等信号问题,提出削弱或消除以上噪声的方法.用Altium Designer,PADS软件绘制电路原理图和PCB,借助Hyper Lynx和ADS仿真软件进行前端和后端可靠性验证,最后通过对完成布线的PCB进行信号完整性验证.测试结果表明此方案设计的HDMI高清音视频系统工作稳定,在智能设备的升级替换和建设方面有重要的借鉴作用. 相似文献
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基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。 相似文献