Modification of transconductance characteristics for ion-implanted GaAs/AlGaAs heterojunction MESFETs

Inverted GaAs/AlGaAs heterostructures grown by MOCVD have been used to fabricate conventional ion-implanted MESFETs. Two types of GaAs/AlGaAs heterojunctions are studied. One type has a compositionally graded AlGaAs layer which provides a built-in field and corresponding quantum well at the heterointerface. The other type has a constant-composition AlGaAs layer. 0.5 mu m gate devices fabricated using the ungraded AlGaAs layer show a maximum extrinsic transconductance G/sub m/ of 280 mS/mm and a small G/sub m/ variation over a gate voltage range of 1.5 V. In comparison, devices fabricated using the graded AlGaAs layer exhibit higher transconductance over all the gate voltages and an enhancement of G/sub m/ up to 420 mS/mm at low gate bias.<>     

Optimization of transconductance in JFETs and MESFETs

It is shown that the transconductance vs channel depth curve has a maximum. An analytical expression for this optimum value is derived and is shown to agree with computer simulations and experimental results.     

Microwave performance of ion-implanted InP JFETs

These devices have a planar structure with the channel and gate regions formed by the selective implantation of silicon and beryllium into an Fe-doped semi-insulating InP substrate. The nominal gate length is 2 μm with a channel doping of 10¹⁷ cm^-3 and thickness of 0.2 μm. The measured values of f_T and f_max are 10 and 23 GHz, respectively. Examination of the equivalent circuit parameters and their variation with bias led to the following conclusions: (a) a relatively gradual channel profile results in lower than desired transconductance, but also lower gate-to-channel capacitance; (b) although for the present devices, the gate length and transconductance are the primary performance-limiting parameters, the gate contact resistance also reduces the power gain significantly; (c) the output resistance appears lower than that of an equivalent GaAs MESFET, and requires a larger V_DS to reach its maximum value; and (d) a dipole layer forms and decouples the gate from the drain with a strength that falls between that of previously reported GaAs MESFETs and InP MESFETs     

Submicrometer GaAs MESFET with shallow channel and very high transconductance

A 0.5-µm GaAs MESFET with a 25-nm thin channel, 400- mS/mm maximum transconductance, and 580-mS/V.mm K value is presented. This extremely high K value was obtained using an electron-beam fabricated recessed-gate MESFET structure on a highly doped (9.10¹⁷cm^-3) MBE-grown channel layer with 2600-cm²/V.s mobility. The use of thin channels and a buried p-layer also reduced the output conductance and other short-channel effects dramatically. As a result, these scaled MESFET's are very promising for high-speed digital logic circuits.     

Integrated amplifiers using fully ion-implanted InP JFETs with hightransconductance

Monolithically integrated amplifiers have been fabricated using JFETs with a gate length of 1.5 μm and a maximum transconductance of 110 mS/mm, the highest ever reported for ion-implanted InP JFETs. The amplifiers utilized both a conventional direct-coupled design and a new symmetrical design. The conventional direct-coupled amplifier shows a maximum gain of 8 (18 dB) while the symmetrical amplifier design exhibits the same gain without DC offset regardless of the FET threshold voltage and the power supply voltage used     

Low-frequency transconductance dispersion in InAlAs/InGaAs/InPHEMT's with single- and double-recessed gate structures

The effects of trapping mechanisms on the transconductance of single- and double-recessed InAlAs/InGaAs/InP HEMT's are examined. Measurements at room temperature indicate transconductance dispersion occurring primarily between 100 Hz and 1 MHz. A detailed examination of the dispersion yields two mechanisms with different activation energies which were determined by measuring the transition frequencies as functions of temperature. One mechanism, causing negative dispersion, has an activation energy of 0.17 eV and was found only in the double-recessed structure. The other mechanism, causing positive dispersion and common to both structures, has a dominant transition with an activation energy of 0.51 eV at low fields. The first mechanism appears to be associated with surface states, while the second is caused by electron traps in the InAlAs or its interface with the InGaAs channel. Transient response measurements were also used to examine the location of the traps and to study the field dependence of the characteristic times     

Interpretation of transconductance dispersion in GaAs MESFET usingdeep level transient spectroscopy

The negative transconductance dispersion in a GaAs metal-semiconductor field-effect transistor (MESFET) was interpreted using both surface leakage current and capacitance deep level transient spectroscopy (DLTS) measurements. The transconductance of the device was reduced by 10% in the frequency range of 10 Hz ~1 kHz. The transition frequency shifted to higher frequency region with the increase of device temperature. The activation energy for the change of the transition frequency was determined to be 0.66±0.02 eV. It was found that the activation energy for the conductance of electrons on the surface of GaAs was 0.63±0.01 eV. In the DLTS spectra, two types of hole-like signals with activation energies, 0.65±0.07 eV (H1) and 0.88±0.04 eV (H2), were observed. The activation energy of H1 trap agrees well with those obtained from the transconductance dispersion and surface leakage current measurements. This demonstrates that surface state H1 causes the generation of surface leakage current, leading to the transconductance dispersion in the MESFET. Using the experimental results, a model for the evolution of hole-like signal by surface states in the capacitance DLTS is proposed     

Characterization of the frequency dispersion of transconductance and drain conductance of GaAs MESFET

Frequency dispersions of the transconductance and the drain conductance of ion-implanted gallium arsenide (GaAs) metal-semiconductor field-effect transistors (MESFETs) are measured and analyzed. In the linear region of the MESFET (low drain voltage), a positive transconductance dispersion is observed, which is caused by the deep-level traps at the surface between the source and the gate. In the saturation region (high drain voltage), however, a negative transconductance dispersion becomes dominant. The drain conductance does not show a dispersion in the linear region, while a distinct positive dispersion is observed in the saturation region with the same activation energy as the negative transconductance dispersion. The difference of the dispersion activation energy of the MESFET with and without the p-buried layer beneath the channel indicates that the negative transconductance and the drain conductance dispersion are caused by the deep-level traps at the channel-substrate interface. Because there exists the high electric field at the drain edge of the gate and an electron accumulation layer is formed, the potential in the channel becomes lower when the drain current is larger with high gate voltage. The emission of electrons from electron traps with lower potential is the cause of the negative frequency dispersion.     

结型场效应晶体管低频噪声测试方法研究

在深入研究JFET低频噪声特性及产生机理的基础上,提出了一种通过测试宽频带功率谱密度得到其规定频率处等效输入噪声电压功率谱密度和噪声系数的测试方法,并给出了低频噪声测试的偏置电路、测试设备和测试方法。结合3DJ4和3DJ6型JFET器件的测试结果表明,采用本文提出的方法可适用于JFET的低频噪声的测试。     

High-speed DCFL circuits with very shallow junction GaAs JFETs

High-speed DCFL (direct-coupled FET logic) circuits implemented with advanced GaAs enhancement-mode J-FETs are discussed. A divide-by-four static frequency divider operates at up to 6 GHz with a power consumption of 20 mW/flip-flop. A high channel concentration of more than 1×10¹⁸ cm^-3 together with a very shallow junction depth of less than 30 nm for the p⁺-gate results in a transconductance as high as 340 mS/mm at a gate length of 0.8 μm. Open-tube diffusion of Zn using diethylzinc and arsine makes it possible to control a very shallow p⁺-layer less than 10 nm thick. The propagation delay time, as measured with a ring oscillator, was 22 ps/gate with a power consumption of 0.42 mW/gate     

Time dependent analysis of an ion-implanted GaAs OPFET

A time-dependent analysis of the electrical characteristics of an ion implanted GaAs optical field effect transistor (OPFET) has been carried out. Both the cases of light turning on and off at a reference time t=0 have been considered. The photovoltaic effect across the Schottky junction and the depletion width modulation in the active layer have been taken into account. The threshold voltage, channel charge, channel conductance, drain-source current, transconductance, and gate-source capacitance of the device under light turning on and off conditions have been evaluated. When light is turned on, all the parameters increase with time before reaching the steady-state value and when light is turned off, these parameters decrease with time and reach their respective values corresponding to dark condition. The time under on condition is less than that under off condition     

GaAs field-effect transistors with ion-implanted channels

Schottky-barrier-gate n channel depletion-mode field-effect transistors have been fabricated in GaAs by the use of sulphurion implantation directly into semi-insulating Cr-doped substrates to produce the channel. This technique eliminates the need for the growth of a thin epitaxial layer, as is usually done, and results in better uniformity of device characteristics over the wafer area. Performance of these devices at 1 to 12 GHz is described, and low-frequency characteristics are given.     

Trap studies in GaInP/GaAs and AlGaAs/GaAs HEMT's by means oflow-frequency noise and transconductance dispersion characterizations

The presence of traps in GaInP/GaAs and AlGaAs/GaAs HEMT's was investigated by means of low frequency noise and frequency dispersion measurements. Low frequency noise measurements showed two deep traps (E _a1=0.58 eV, E_a2=0.27 eV) in AlGaAs/GaAs HEMT's. One of them (E_a2) is responsible for the channel current collapse at low temperature. A deep trap (E_a1'=0.52 eV) was observed in GaInP/GaAs HEMT's only at a much higher temperature (~350 K). These devices showed a transconductance dispersion of ~16% at 300 K which reduced to only ~2% at 200 K. The dispersion characteristics of AlGaAs/GaAs HEMT's were very similar at 300 K (~12%) but degraded at 200 K (~20%). The low frequency noise and the transconductance dispersion are enhanced at certain temperatures corresponding to trap level crossing by the Fermi-level. The transition frequency of 1/f noise is estimated at 180 MHz for GaInP/GaAs HEMT's and resembles that of AlGaAs/GaAs devices     

Chromium redistribution in ion-implanted GaAs

In this paper we attempt to find systematic differences between the annealing conditions for ion implanted GaAs where Cr is observed to redistribute and the conditions where it does not. For samples where Cr redistribution was observed, we also separate electrical from chemical and/or strain interactions. The results indicate that electrical interactions are at least a limiting factor and in most cases a dominant factor in Cr redistribution. For this reason it appears that Cr redistribution in ion implanted samples can be minimized or eliminated by annealing at temperatures such that the background free carrier concentration screens out any internal electric fields.     

Low-frequency noise of ion-implanted double-drift IMPATT diodes

The low-frequency open circuit noise spectral density S(f) of an ion-implanted 60-GHz double-drift-region IMPATT diode was measured as a function of the dc avalanche current I0. Over an intermediate current range the noise follows an S(f)=a²VB0²/I0relationship where VB0is the reverse breakdown voltage and a²≃4.5 × 10^-20A/Hz.     

A new approach to fabrication of GaAs JFETs

A new approach to JFETs is preparing gallium assenide junction field-effect transistor (JFET) presented in this paper, applying Be ion implantation for the first time along with a method of flat and homogeneous ohmic metallization. Several characteristics of FET I–V curve are also discussed.It is revealed that Be ion implantation is sufficiently feasible to obtain a buried p-type gate for the GaAs JFET. Ohmic metallization to GaAs is improved in flatness and homogeneity by simultaneous heating of substrates with Au/Ge deposition. An ion milling process for fine patterning associated with the improved metallization, proves to be useful for device micro-technology. Finally, d.c. characteristics comparable to those of the MESFET are demonstrated by the fabricated JFET, with marked advantages in the process.     

Backgate-induced characteristics of ion-implanted GaAs MESFET's

Three important characteristics of GaAs ion-implanted MESFET's associated with the phenomenon of backgating have been identified and measured. These include a negative backgate capacitance, initiation and/or control of low-frequency oscillations, and enhancement of g-r noise, all related to the deep-level electron traps present in the semi-insulating substrate beneath the implanted layer. Low-frequency oscillations have been observed mostly in devices with high gate-leakage current under conditions involving zero to large negative backgate bias. The frequency of oscillations and the backgate negative-capacitance magnitude have been found to decrease and increase, respectively, with the increase of the negative backgate bias voltage. This implies a decrease in the capture/emission cross section of traps at high fields.     

Realisation of very high transconductance GaAs MESFETs

By using a model which considers velocity overshoot, it is shown that the performance of GaAs MESFETs in enhancement mode depends strongly on the geometrical and electrical characteristics of the access region between source and gate. The sheet resistance of the unrecessed epilayer, and the distance between the source-end of the recessed region and the gate, have to be as small as possible. 300 nm gate length MESFETs with very low values for these parameters were realised with an n-GaAs active layer (6×10¹⁷ cm^-3). These devices exhibit very high microwave transconductances (800 mS/mm) with good cutoff frequencies (up to 55 GHz). This result suggests that very high transconductance MESFETs can be fabricated from not-too-heavily doped active layers provided that the characteristics of the source-gate access region is properly optimised     

Transient capless annealing of ion-implanted GaAs

A method for high-temperature capless activation of implanted gallium arsenide has been developed that uses high-purity semi-insulating PBN LEC gallium arsenide [1] both as implant host and stabilizing medium. This capless technology, "transient capless annealing," has shown high activation of implanted dose (85 percent) with high uniformity (± 4.5 percent) and abrupt (500 Å/decade) carrier concentration depth profiles at 1.5 × 10¹⁷cm^-3doping. Hall measurements taken from activated films show an electron mobility of 4500 cm²/V . s at room temperature. S-band integrated circuits fabricated by transient capless annealing of discretely implanted²⁹Si⁺delivered 20 dB of gain and 29 dB . m of output power between 3.0 and 3.6 GHz. The high-throughput batch-processing nature of transient capless annealing makes this process commercially attractive for high-yield integrated-circuit production in gallium arsenide.