TO系列塑料封装离层探讨

文章研究了TO系列塑料封装功率器件产品产生离层的原因。同时,研究了TO系列塑料封装功率器件产品在上芯、压焊、塑封工序中的原材料、塑封模具、工艺参数等对离层的影响,并通过SAT图片,对影响离层的因素进行了论证,提出了如何预防或减轻TO系列塑料封装产品离层的产生。实验结果表明:塑封工艺参数的合理选择、塑封模具结构的合理选用、塑封料优选对TO系列塑料封装离层有较好的改善作用,并且在塑封生产线上易于实现。文章在这些方面做了相关尝试,取得了较好的效果。     

引线框架塑料封装集成电路分层及改善

分层是塑料集成电路封装过程和可靠性试验后常见的问题,如何解决分层问题是封装材料供应商、封装工程师、可靠性试验工程师共同研究与改善的课题。通过对封装产品结构、材料、工艺方法等方面进行深入的解析,详细阐述了引线框架塑料封装集成电路分层产生机理,描述了分层对集成电路的危害以及如何预防分层的发生,进而提出了有效的改善措施。结果表明,这些措施的应用能够有效预防分层问题的发生,提高塑料封装集成电路的可靠性。     

集成电路封装开裂产生原因分析及对策

塑封体开裂是集成电路封装影响产品可靠性的致命不良,具有产品损失大、不易发现、隐患时间长等特点。本文探讨在制造过程中的开裂预防与控制方法。     

集成电路封装芯片弹坑问题浅探

论述了集成电路封装过程中因芯片铝垫出现弹坑造成的危害,分析和总结出了造成芯片弹坑问题的主要原因,通过从工艺、设备、制具、材料、方法等综合考虑,提出了预防芯片表面产生弹坑的方法和对策。根据长期实践跟踪的结果,这些方法的应用能够对预防和改善弹坑的发生起到很好的效果,为集成电路设计及封装过程如何预防弹坑问题提供了参考。伴随集成电路芯片小型化、多功能化和铜线工艺、植球工艺等封装技术的广泛应用,通过各级人士在集成电路的设计、封装材料的优化、制程工艺的优化等各方面共同努力,弹坑问题会得到更好的预防和解决。     

塑封器件的耐湿性问题

目前国外集成电路(IC)封装的主流是塑料封装,而且最常用的是环氧树脂低压递模法(transfer molding)的树脂封装.IC80%,分立器件90%以上,民用器件几乎100%采用塑料封装.其中环氧塑封占90%,硅酮塑封已退居次要地位.这种变化是由于管芯制造技术(钝化技术等)的进步和塑封材料可靠性的提高,日益扩大了塑封的适用范围.国外64KDRAM原来完全采用陶瓷封     

塑封倒装焊焊点开裂分析及改善研究

随着科技的发展,半导体元器件小型化、高性能、轻量化的需求日益迫切,塑封倒装焊技术得到了广泛应用。因为基板的易形变性及各封装材料间的热膨胀系数不匹配,焊点开裂成为影响封装可靠性的重要因素之一。为了研究倒装焊产品在封装制程中焊点开裂的失效原因,利用有限元分析（ANSYS）软件建立倒装焊塑封封装体有限元模型,模拟回流焊过程中的塑封基板形变与凸点应力分布,并分析焊点开裂失效的原因。结果表明,在回流焊过程中,基板形变量大于裸芯,外围凸点倾斜较大,承受的应力及应变能最大,外沿凸点为最易失效点,采用加载具作业可显著降低失效风险。     

集成电路封装用绝缘胶漏电失效分析

在电子元器件封装领域中,塑封器件正逐步替代气密性封装器件。目前工业级塑封器件已不能满足器件的高可靠性要求,工业级塑封器件在严酷的环境应力试验中经常出现失效。研究了工业级塑封器件在可靠性筛选试验中出现失效的问题,通过X射线观察和芯片切面分析等方法,查明了造成器件失效的原因,并提出了优化改进措施。     

PBGA封装的耐湿热可靠性试验研究

塑封电子器件作为一种微电子封装结构形式得到了广泛的应用,因此湿热环境下塑封电子器件的界面可靠性也越来越受到人们的关注.为了研究塑封器件及其所用材料在高湿和炎热(典型的热带环境)条件下的可靠性,采用耐湿温度循环的试验方法,以塑封球栅平面阵列封装(PBGA)器件为例进行测试.试验结果表明,芯片是最容易产生裂纹的地方,试验后期器件产生的裂纹主要出现在芯片和DA材料界面处及芯片、DA材料和EMC材料三种材料的交界处.空洞缺陷是使界面层间开裂的主要原因,在高温产生的蒸汽压力和热机械应力的作用下,界面上的微孔洞扩张并结合起来,导致器件最后失效.     

基于封装工艺识别翻新塑封集成电路

塑封集成电路在高可靠性领域应用越来越广泛,国内已有相当数量的塑封集成电路应用于国防领域。但是,目前大部分关键塑封集成电路依赖进口,采购渠道不是很通畅,市场中存在大量的翻新件。文章基于塑封集成电路封装工艺,简要介绍如何识别翻新塑封集成电路。     

集成电路封装热阻分析

集成电路热阻是集成电路特别是功率型电路的主要可靠性参数。在一定功率下,它决定了电路工作时的结温,在进行系统热设计、可靠性预计时都要考虑电路的热阻。集成电路热阻测试方法是我国微电子工业尚待解决的问题,也是当前研究重点之一。本文介绍采用统一热分布的标准芯片测试电路热阻的方法,并分析不同封装形式、不同粘片工艺、不同芯片面积以及不同生产厂对电路热阻的影响。     

Impact of flip-chip packaging on copper/low-k structures

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.     

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.     

Comprehensive treatment of moisture induced failure-recent advances

This paper describes a comprehensive treatment of moisture induced failure in integrated circuit (IC) packaging with emphasis on recent advances. This includes advanced technique for modeling moisture diffusion under dynamic boundary conditions such as experienced by packages during solder reflow, autoclave, and temperature-humidity cycling; advanced characterization technique for moisture sorption and diffusion properties of packaging materials including effect of edge diffusion on transverse diffusivity, anisotropic diffusivity in organic laminates, impact of non-Fickian sorption; advanced techniques for modeling vapor pressure during solder reflow; advanced techniques for modeling dynamic delamination propagation during solder reflow; interfacial fracture strength as a function of temperature and moisture; as well as plastic analysis of popcorn cracking.     

On the crack and delamination risk optimization of a Si-interposer for LED packaging

3D-integration becomes more and more an important issue for advanced LED packaging solutions as it is a great challenge for the thermo-mechanical reliability to remove heat from LEDs to the environment by heat spreading or specialized cooling technologies. Thermal copper-TSVs provide an elegant solution to effectively transfer heat from LED to the heat spreading structures on the backside of a substrate. But, the use of copper-TSVs generates also novel challenges for reliability as well as also for reliability analysis and prediction, i.e. to manage multiple failure modes acting combined – interface delamination, cracking and fatigue, in particular. In this case, the thermal expansion mismatch between copper and silicon yields to risky stress situations.To overcome cracking and delamination risks in the vicinity of thermal copper-TSVs the authors performed extensive simulative work by means of fracture mechanics approaches – an interaction integral approach within a simulative DoE and the X-FEM methodology to help clarifying crack propagation paths in silicon. The results provided a good insight into the role of model parameters for further optimizations of the intended thermal TSV-approaches in LED packaging applications.     

Effects of underfill materials on the reliability of low-K flip-chip packaging

The reliability of low-K flip-chip packaging has become a critical issue owing to the low strength and poor adhesion qualities of the low-K dielectric material when compared with that of SiO₂ or fluorinated silicate glass (FSG). The underfill must protect the solder bumps and the low-K chip from cracking and delamination. However, the material properties of underfill are contrary to those required for preventing solder bumps and low-K chip from cracking and delamination. This study describes the systematic methodologies for how to specify the adequate underfill materials for low-K flip-chip packaging. The structure of the test vehicle is seven copper layers with a low-K dielectric constant value of 2.7-2.9, produced by the chemical vapor deposition (CVD) process. Initially, the adhesion and the flow test of the underfill were evaluated, and then the low-K chip and the bumps stress were determined using the finite element method. The preliminary screened underfill candidates were acquired by means of the underfill adhesion and flow test, and balancing the low-K chip and the bumps stress simulation results. Next, the low-K chips were assembled with these preliminary screened underfills. All the flip-chip packaging specimens underwent the reliability test in order to evaluate the material properties of the underfill affecting the flip-chip packaging stress. In addition, the failed samples are subjected to failure analysis to verify the failure mechanism. The results of this study indicate that, of the underfill materials investigated, those with a glass transition temperature (T_g) and a Young’s modulus of approximately 70–80 °C and 8–10 GPa, respectively, are optimum for low-K flip-chip packaging with eutectic solder bumps.     

Prediction of Delamination Related IC & Packaging Reliability Problems

This paper presents our effort to predict delamination related IC & packaging reliability problems. These reliability problems are driven by the mismatch between the different material properties, such as thermal expansion, hygro-swelling, and/or the degradation of interfacial strength. First of all, a test technique is presented to measure the interfacial strength between packaging materials. Secondly, several reliable non-linear Finite Element models are developed, able to predict the reliability impact of delamination on wire failures, different package structures, and passivation cracks in IC-packages.     

Investigation of the underfill delamination and cracking inflip-chip modules under temperature cyclic loading

In this paper, stress singularity in electronic packaging is described and three general cases are summarized. The characteristics of each stress singularity are briefed. In order to predict the likelihood of delamination at a bimaterial wedge, where two interfaces are involved, a criterion is proposed and the corresponding parameters are defined. The propagation of a crack inside a homogeneous material with the effects of delamination and stress singularity is predicted by the maximum hoop stress criterion. The proposed criteria are adopted in the analysis of a flip-chip with underfill under thermal cyclic loading. A finite element (FE) model for the package is built and the proper procedures in processing FE data are described. The proposed criterion can correctly predict the interface where delamination is more likely to occur. It can be seen that the opening stress intensity factor along the interface (or peeling stress) plays a very important role in causing interfacial failure. The analytical results are compared with experimental ones and good agreement is found. The effects of delamination and cracking inside the package on the solder balls are also mentioned. Further investigation into the fatigue model of the underfilled solder ball is discussed     

Interface delamination in plastic IC packages induced by thermal loading and vapor pressure - a micromechanics model

A micromechanics model and an associated computational scheme are proposed to study interface delamination in plastic integrated circuit (IC) packages induced by thermal loading and vapor pressure. The die and die-pad are taken as elastic materials, while the die-attach and molding compound are taken as elasto-visco-plastic materials. The interface between molding compound and the die-pad is characterized by a cohesive law. The key parameters of this law are the interface strength and interface energy. The vapor-induced pressure along the interface is incorporated by way of a micromechanics model. Parametric studies are conducted to understand interface properties and vapor pressure effects on interface delamination. Under purely thermal loading, both weak and strong interfaces are highly resistant to interface failure. However, the combined effects of thermal loading and vapor pressure arising from moisture trapped within the interface can cause total delamination at the interface. Once delamination has initiated at a weak interface, no significant increase in thermal loading and vapor pressure is required for the delaminated zone to grow to a macro-crack and subsequently to catastrophic failure referred to as popcorn cracking. The critical factors controlling the occurrence of popcorn cracking are the interface adhesion strength and interface vapor pressure.     

Analysis of Cu/low-k bond pad delamination by using a novel failure index

For the development of state-of-the-art Cu/low-k CMOS technologies, the integration and introduction of new low-k materials is one of the major bottlenecks owing to the bad thermal and mechanical integrity of these materials and the inherited weak interfacial adhesion. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily result in cracking, delamination and chipping of the IC back-end structure if no appropriate measures are taken. This paper presents a methodology for optimizing the thermo-mechanical reliability of bond pads by using a 3D multi-scale finite element approach. An important characteristic of this methodology is the use of a novel energy-based failure index, which allows a fast qualitative comparison of different back-end structures. The usability of the methodology will be illustrated by a case study in which several bond pad structures are analysed.