A 2Gb/s throughput GaAs digital time switch LSI using LSCFL

A GaAs four-channel digital time switch LSI with a 2.0-Gb/s throughput is developed. This switch consists of 4-bit shift registers, data latches, a counter, a control unit, and I/O buffer gates. The LSI includes 1176 devices (FET's, diodes, and resistors) and its equivalent gate number is 231 gates. Low Power Source Coupled FET Logic (LSCFL) operating in a true/complementary mode is used to ensure high-speed and low-power performance. MESFET's with 0.55-µm gate length are fabricated by the buried p-layer SAINT process, which satisfactorily suppresses short channel effects. Dislocation-free wafers are also used to provide high chip yields of 75 percent. The propagation delay time of the LSCFL basic circuit is 48 ps/gate with 1.4-mW/equivalent gate. The total power dissipation including input and output buffers is 0.64 W. The LSI speed performance is evaluated by measuring toggle frequency of the 1/4 frequency divider. The divider operates typically at 5.1 GHz, maximum 7.5 GHz. The newly developed high-speed digital time switch LSI makes possible time division switching services in TV and high-definition TV transmission systems.     

A 622-Mb/s 8×8 ATM switch chip set with shared multibufferarchitecture

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8-μm BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8×8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing     

A simple 8×8 optoelectronic crossbar switch

The authors demonstrate the operation of an 8×8 optoelectronic crossbar switch consisting of integrated arrays of eight 1×8 GaAs metal-semiconductor-metal (MSM photodiodes connected in a current summing network to the input of Si bipolar transimpedance amplifiers. The MSM devices are also connected to TTL transistor-transistor logic) driven CMOS analog multiplexers which, in the `off' state, switch the detectors into an open-circuit mode. This particular combination of detectors and switching network gives a very high interchannel isolation, reduced circuit complexity, and low input noise. Data rates of 200 Mbit's and switch reconfiguration times of -100 ns are achieved. System noise is calculated and measured, and the advantages of using fully integrated GaAs crossbar switch arrays are quantitatively discussed     

8×8 optoelectronic crossbar switch

An optoelectronic crossbar switch has been fabricated and tested at 100-175 Mbit/s. The optoelectronic switching is achieved using bias switched detectors     

A 2.5 Gb/s ATM switch chip set

The design and implementation of two application specific integrated circuits used to build an ATM switch are described. The chip set is composed of the CMC which is an input/output processor of ATM cells implemented on a BICMOS 0.7 μm technology and the ICM, a 0.7 μm CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output. The main advantage of the high-speed link rates in the range of Gb/s, is the exploitation of statistical gain with bursty high peak rate sources. Another feature of the high speed ATM switches is that the number of interface devices and stages is reduced on an ATM network. To demonstrate the usefulness of the switch, an evaluation of the network efficiency improvement by using statistical gain is presented in the paper     

DPSK 32×10 Gb/s transmission modeling on 5×90 kmterrestrial system

Reduction of DWDM nonlinear fiber penalties by the use of DPSK modulation and an optically preamplified self-homodyning receiver is discussed. Maintaining a constant instantaneous channel power by phase shift keying, we can anticipate reduction of cross-phase modulation penalties. Our modeling results show 0.9-dB benefit in Q performance for 50-GHz spaced, 32×10 Gb/s transmissions with nonzero dispersion shifted fiber     

Polarization independent LiNbO3 8×8 matrix switch

A polarization-independent LiNbO₃ strictly blocking 8×8 matrix switch has been developed. A relatively low insertion loss, below 12 dB, has been obtained by a reduction in bending loss, using a wide bent waveguide width. The switch has less than -18.7-dB crosstalk and about 85-V switching voltage at any incident polarization with 1.3-μ wavelength light     

Performance of eight-channel OEIC p-i-n/HBT receiver array in8×2.5 Gb/s WDM transmission system

The performance of an eight-channel, 2.5 Gb/s OEIC photoreceiver array in an eight-wavelength long-distance WDM testbed is described. The sensitivity penalties due to crosstalk and transmission are measured, and the source of crosstalk is investigated. Channel sensitivities range from -25.4 to -26.2 dBm after transmission through 720 km of standard fiber, with transmission penalties ranging from 0.3 dB to 1.0 dB. When the power in each of seven interfering channels is 5 dB above sensitivity, the maximum crosstalk penalty suffered by an individual channel does not exceed 1 dB. These experiments are the first comprehensive characterization of monolithic receiver arrays for crosstalk performance under multichannel operation in a realistic system environment     

A GaAs HBT 16×16 10-Gb/s/channel crosspoint switch

A 16×16 crosspoint switch IC has been designed and implemented in a 2-μm GaAs heterojunction bipolar transistor (HBT) technology. The IC is a strictly nonblocking switch with broadcast capability and asynchronous data paths. The IC has fully differential internal circuitry and is packaged in a custom high-speed assembly. Test results confirmed that the IC achieves a 10-Gb/s/channel (or 160-Gb/s aggregate) capacity, the highest reported to date for a 16×16 crosspoint switch IC     

100×100 optoelectronic cross-connect interconnects usingOPTOBUS

This paper demonstrates an OPTOBUS-based fully packaged optoelectronic cross-connect interconnect technique for data communication applications. Optical insertion loss of the compact 100×100 cross-connect interconnect device ranges from 0.4 to 2.9 dB among all possible connections. Optical transmissions with bit error rate (BER) of >10^-12 can be maintained at per channel bandwidth of 900 Mb/s. The system is expected to have an aggregated interconnect bandwidth near 100 Gb/s when being fully connected with the OPTOBUS chips     

Rearrangeably nonblocking 8×8 guided wave optical switch

The design and construction of a lithium niobate 8×8 optical switch with a rearrangeably nonblocking architecture is described. The design is compared with the more familiar strictly nonblocking architecture. The switch has 28 elements, a switching voltage of 26 V and a loss of 5.5 dB at 1.3 μm wavelength     

A 16×622 Mb/s ATM switch: PRELUDE switch architectureintegrated into a 6-million transistor monochip

This paper presents the integration of the Prelude switch architecture into a monochip ATM switch, COM16M, capable of handling 16 multiplexes carrying ATM cells at 622 Mb/s. It is a fully autonomous switch, i.e., the chip includes clock adaptation, routing, and cell buffering as well as header translation and control capabilities. The switch is integrated into one single chip containing 6000000 transistors implemented in a 0.5-μm CMOS process     

A 1.5 Gb/s link interface chipset for computer data transmission

The authors designed a set of four ICs to provide encoding, multiplexing, clock extraction/demultiplexing, and decoding for gigabit-rate serial data transmission. These chips form a high bandwidth data link for point-to-point communication. A new line code is implemented that provides DC balance, efficient encoding, framing, and simple clock extraction. Embedded in the code is a fixed transition used by the phase/frequency locked loop (PLL) for simple clock extraction and frame synchronization. Unlike other links, this PLL requires no trimming for data retiming, either in production or later. An on-chip voltage-controlled oscillator (VCO) with a tuning range of 1.1-1.6 GHz is available for use with the PLL. With this chip set the authors demonstrated a transmission rate of 16 bits in parallel at 75 MHz or, with encoding overhead, a serial rate of 1.5 Gb/s     

A low-voltage 8×8 Ti:LiNbO3 switch with adilated-Benes architecture

An 8×8 switch array with a dilated-Benes architecture that greatly relaxes the crosspoint extinction ratio requirements needed to achieve low overall switch array crosstalk is discussed. This, combined with the low uniform switching voltages (9.2+0.2 V) of the 48 directional coupler crosspoints, facilitates high-speed low-crosstalk operation. The crosspoints can be switched in about 1 ns. The switch array is fully packaged with permanently attached single-mode fiber pigtails. The high data transfer rate inherent in lithium niobate switches in general, combined with the low crosstalk and high switching speed of this switch array, is a good match to the requirements of time-multiplexing switching     

A 40–44 Gb/s 3× Oversampling CMOS CDR/1:16 DEMUX

A CMOS CDR and 1:16 DEMUX fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3times blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER <10^-12 with a 2³¹-1 PRBS source) is demonstrated using both an on-chip and an external BERT.     

应用于subLVDS接口的1.5Gb/s收发器设计

介绍了subLVDS接口的系统结构并给出一种改进的内部收发器实现电路.为了稳定直流工作点,在发送器内部加入与电源电压无关的自偏置电压源和共模负反馈电路;通过轨到轨预放大器,接收器的共模输入电压可以达到电源至地的范围.SMIC0.18μm 1P6M的工艺下,仿真结果表明该系统对随机输入数据的工作速度可以达到1.5Gb/s,工作温度范围为-40～120℃.     

An experimental 5-Gb/s 16×16 Si-bipolar crosspoint switch

An experimental 16×16, nonblocking, asynchronous crosspoint switch with a data rate of 5-Gb/s per channel is presented. Implemented in a 0.8-μm, double-poly, self-aligned Si-bipolar ECL technology, the 3-mm×3-mm chip, featuring a multiplexer-type architecture with a three-device crosspoint cell, demonstrates a nominal data path delay of 420 ps with 12.5-ps RMS jitter and a setup time of 1 ns and dissipates about 4.6 W     

A 10-Gb/s (1.25 Gb/s×8)4×2 0.25-μm CMOS/SIMOX ATMswitch based on scalable distributed arbitration

This paper presents the design and implementation of a scalable asynchronous transfer mode switch. We fabricated a 10-Gb/s 4×2 switch large-scale integration (LSI) that uses a new distributed contention control technique that allows the switch LSI to be expanded. The developed contention control is executed in a distributed manner at each switch LSI, and the contention control time does not depend on the number of connected switch LSI's. To increase the LSI throughput and reduce the power consumption, we used 0.25-μm CMOS/SIMOX (separation by implanted oxygen) technology, which enables us to make 221 pseudo-emitter-coupled-logic I/O pins with 1.25-Gb/s throughput. In addition, power consumption of 7 W is achieved by operating the CMOS/SIMOX gates at -2.0 V. This consumption is 36% less than that of bulk CMOS gates (11 W) at the same speed at -2.5 V. Using these switch LSI's, an 8×8 switching multichip module with 80-Gb/s throughput was fabricated with a compact size     

High-extinction ratio and low-loss silica-based 8×8thermooptic matrix switch

A high-extinction ratio and low-loss silica-based 8×8 thermooptic matrix switch is demonstrated. The 8×8 matrix switch is realized by using a double Mach-Zehnder interferometer switching unit and a matrix arrangement which reduces the total waveguide length. The average extinction ratio and the average insertion loss are 60.3 and 5.2 dB, respectively     

40-Gb/s OTDM to 4×10 Gb/s WDM conversion in monolithic InPMach-Zehnder interferometer module

Transformation of high bit-rate optical time-domain multiplexed (OTDM) signals into a multitude of lower bit-rate wavelength-division-multiplexed (WDM) channels is demonstrated by means of a single monolithically integrated indium phosphide Mach-Zehnder interferometer with semiconductor optical amplifiers in its arms. Full demultiplexing of 10-Gb/s OTDM signals into 4×10-Gb/s WDM channels is demonstrated. Bit-error-rate penalties are below 1.5 dB for polarization independent signal conversion throughout the 1.55-μm wavelength range