Chip layout design of a Josephson LSI circuit for examininghigh-speed operability by using a standard cell automatic placement androuting technique

A chip layout design technique for a high-speed Josephson LSI circuit using an automatic placement and routing technique with a standard cell method has been developed. A chip layout design of a Josephson LSI circuit with 1500 gates for examining high-speed operability with a 1 GHz clock frequency has been successfully obtained. Related to high-frequency power on a high-speed Josephson LSI circuit, a dividing method for a circuit and a balancing method for power loads are proposed     

Rail to rail radiation hardened operational amplifier in standard CMOS technology with standard layout techniques

This work presents a rail-to-rail operational amplifier hardened by design against ionizing radiation at circuit level, using only standard layout techniques. Not changing transistor layout, for instance by using enclosed layout structures, allows design and simulation using the standard models provided by the foundry. The circuit was fabricated on a standard 0.35 μm CMOS process, and submitted to a total ionizing dose (TID) test campaign using a ⁶⁰Co radiation source, at a dose rate of 0.5 rad(Si)/s, reaching a final accumulated dose of 500 krad(Si). The circuit proved to be radiation tolerant for the tested accumulated dose. The design practices used to mitigate TID effects are presented and discussed in detail.     

Standard cell layout with regular contact placement

The practicability and methodology of applying regularly placed contacts on layout design of standard cells are studied. The regular placement enables more effective use of resolution enhancement technologies, which in turn allows for a reduction of critical dimensions. Although placing contacts on a grid adds restrictions during cell layout, overall circuit area can be made smaller by a careful selection of the grid pitch, allowing slight contact offset, applying double exposure, and shrinking the minimum size and pitch. The contact level of 250 nm standard cells was shrunk by 10%, resulting in an area change ranging from -20% to +25% with an average decrease of 5% for the 84 cells studied. The areas of two circuits, a finite-impulse-response (FIR) filter and an add-compare-select (ACS) unit in the Viterbi decoder, decrease by 4% and 2%, respectively.     

Design of 3:1 multiplexer standard cell

A new VLSI 3:1 multiplexer is presented. The proposed circuit is based on a double controlled tri-state buffer. A custom cell which can easily be added to the AMS 0.6 μm CMOS standard cell library has been developed. The new cell shows a propagation delay of ~780 ps and dissipates 5.2 μW/MHz     

Radial EBG cell layout for GPS patch antennas

A novel radial layout for mushroom-like electromagnetic-bandgap (EBG) cells surrounding a printed circularly-polarised patch antenna is proposed. Two radial EBG configurations surrounding a circular patch are compared to a reference patch on a conventional ground plane of the same dimension. The radial shape and displacement of the EBG cells around the patch offers improvements in terms of gain and axial-ratio compared to the reference antenna and is more suitable for circular geometries compared to conventional Cartesian layouts. In particular, the distance between the patch and the surrounding EBG cells is independent of the cell period, which can be arbitrarily chosen, and the overall layout offers footprint reduction.     

超深亚微米可制造标准单元库设计

当集成电路的特征尺寸下降到100nm以下,可制造性设计就变得尤为重要。本文提出了一种65nm可制造性标准单元库的设计方法。通过精简基本单元的数量,降低光学矫正的时间和空间复杂度;利用DFM设计规则和光学模拟仿真对每个单元的版图进行优化以提高整个单元库的可制造性。应用该方法实现的标准单元库在时序,功耗,面积方面与传统标准单元库相比具有很好的性能,并且通过Foundry的TD部门65nm工艺线的可制造性测试,有利于65nm工艺生产良率的提升。     

Lattice Boltzmann method study of effect three dimensional stacking-chip package layout on micro-void formation during encapsulation process

The current study applied the lattice Boltzmann method to examine the effects of stacking chips layout to the micro-void formation in three-dimensional (3D) packaging. Three-dimensional 19-velocities commonly known as D3Q19 scheme is utilized in this study. Three different cases, which are different in layout design, are examined. For code verification purpose, an experimental work is also presented to compare the flow front results between numerical and experimental at different filling percentage. The numerical predictions compared well with the experimental results. Minor differences are observed in their flow front profile. The numerical findings identified the predicted locations of micro-void formation during the encapsulation process. The entrapment of micro-void was visualized clearly in the simulation because of the unbalanced molecular force at the interface during encapsulation. Knit lines were also identified at the interface between the flows that occurred in the encapsulation. Different layout of stacking flip-chips package have influence the micro-void in the package, which tended to form at the stacking chips region. The results show that the lattice Boltzmann method has a good performance in the IC encapsulation simulation.     

Large-signal 2T, 1C DRAM cell: signal and layout analysis

This paper presents a general signal and layout analysis for the two-transistor, one-capacitor DRAM cell. The 2T, 1C configuration enables significantly larger, typically ≳3x, raw sense-signal than is achievable in conventional 1T, 1C cells. In general, stray capacitances at the capacitor nodes further increase the signal level; an exact analytic formula is derived in this case, including the dependence upon bitline precharge level. With trench technology, the 2T, 1C cell occupies 25-30% more area than a corresponding folded-bitline 1T, 1C cell; an implementation employing a buried strap is proposed. Maximization of array density requires multiplexing bitlines to sense amps     

Design of a process-tolerant cell library for regular structuresusing symbolic layout and hierarchical compaction

A method to design cell libraries for macrocell layouts, which are constructed as an array of cells, is discussed. It is based on symbolic layout and a hierarchical compaction algorithm. This algorithm provides automatic terminal fitting and compacts cells in such a way that translated and mirrored cells are kept identical. The cells can be changed with a set of parameters by a macrocell generator. The compaction technique then guarantees that no design-rule errors occur for any combination of the parameter values. The method also allows easy adaptability to circuit techniques and layout rules. It can be applied to all regular hierarchical layout structures where constrained cells have to be designed. Once the library is established its cells can be used over and over again with different personality matrices for fast generation of correct layout     

Cellular system design using the expansion cell layout Method

Cellular system design using the expansion layout method is described and the background and basis of the approach are covered. Key considerations in layout and cell selection emphasize portable coverage and smooth growth as the system matures. The concept is most useful in large systems but applies to any size which will experience additional cell needs as it grows. The approach is basically one that examines the evolution path of a system, including cell additions and subdvision and then constructs a physical cell layout for a future configuration instead of the first year. This is used as a framework to implement the system as required to meet capacity and distribution needs as actual growth is experienced. This results in the following main advantages: extra cell overlap in the early years for added reliability and backup for variable density response; improved in-building portable service from more extensive building penetration in the early years; flexibility in capacity adjustments for various years as individual cell requirements develop; a frequency plan which is a complete framework for all stages of system implementation. No retuning will be required. Other characteristics include: more cell sites in the early years than are needed simply for cellular geographic service area (CGSA) coverage but which will be needed later for capacity; some extra hardware may be involved in the early years, depending on trunking efficiency and user distribution; it may be necessary to introduce some sector transmit at an earlier stage in some cells than would be needed with the classical approach.     

FLAG: a flexible layout generator for analog MOS transistors

This paper describes a flexible MOS transistor layout generator which draws optimal layouts whatever the W and L dimensions. The drawing methodology is based on the use of small elementary parts, called bricks, which are placed side by side inside a user-specified boundary. The generated transistors may allow diffusion merging along whichever sides the user wishes and may have a global rectilinear shape. The internal structure of these cells may also be chosen by the designer so that it is well suited to his application. Transistors developed using this generator have been tested, and have been used to build a simple operational amplifier.     

CALMOS: a computer-aided layout program for MOS/LSI

A new computer program CALMOS has been developed for the automatic layout of MOS/LSI circuits. It provides an automatic 100-percent routing with emphasis on the minimization of the interconnection area. The program runs on a minicomputer and allows for interactive design.     

Fully integrated standard cell digital PLL

A fully integrated digital phase-locked loop (PLL) used as a clock multiplying circuit is designed. The PLL is made from standard cells found in almost any commercial standard cell library and therefore portable between processes in netlist format. Using a 0.35 μm standard complementary metal-oxide-semiconductor CMOS process and a 3.0 V supply voltage, the PLL is designed for a locking range of 170 to 360 MHz and occupies an on-chip area of 0.06 mm²     

便携式产品需要正确的芯片封装

现今手持产品设计者面临的挑战来自两个方面.首先,现代电子产品的设计远远超过被设计设备所命名的功能.其次,设计者在多种多样的生产方法中必须十分慎重地选择出可供使用的既可靠又成熟的方法.     

Reliability evaluation of a silicon-on-silicon MCM-D package

This paper presents the results of reliability testing on a multichip module technology with active silicon substrates. The modules use flip-chip technology to attach silicon chips to the active substrate and this assembly is then packaged into a plastic ball grid array package. Performance was evaluated using two custom designed test chips incorporating thermal, thermomechanical, electrical and reliability test structures. A rigorous environmental test sequence including temperature, cycling, humidity, highly accelerated stress test and power cycling were carried out on the demonstrators. A full destructive physical analysis was then performed, consisting of die/substrate shear, wire bond pull tests and microsectioning.     

Thermal analysis of a multi-chip package design

Two-dimensional finite difference computer simulations were used for thermal analysis of an advanced multi-chip package design. In order to model high performance VLSI and ULSI applications, power dissipations ranging from 10 to 40 W/cm² on each chip and zero to 5 W/cm² on the substrate were simulated. It was found that heating due to resistive losses in the thin film interconnections between chips can impact package thermal performance. The calculated device-to-water thermal resistance was 0.4° C/W and the worst case chip-to-chip temperature variation was less than 22° C. This excellent thermal performance illustrates the effectiveness of the package’s water cooled heat sink with direct backside contact to each die. Methods to improve thermal performance are discussed.     

A CMOS-based analog standard cell product family

Successful integration of mixed analog-logic standard cells has been demonstrated in a 1.0-μm CMOS-based technology. Considerations for analog cell area, power distribution, noise immunity, circuit library design, and product test are described     

Novel HEMT layout: the RoundHEMT

A novel HEMT layout with ringshaped gate is reported. This conception avoids the problems related to mesa etching at the active region and provides additional possibilities for circuit design. The layer structure of the investigated device is based on an Al-free InP/InGaAs material system. Transistors with a gate length of 0.7 μm show an f_T of 40 GHz and an f_max of 117 GHz. These values are similar to results obtained with the conventional HEMT design