GaAs MESFET中的背栅效应

随着集成电路集成度的提高,器件间距不断减小,在GaAs MESFET中产生了一种被称为背栅效应的有害寄生效应。由于器件间距越来越小,某一个器件的电极可能就是另一个器件的背栅,背栅效应影响了集成电路集成度的提高,因此背栅效应在国内外引起了重视。本文介绍了背栅效应及其可能的起因。     

MOS器件的栅氧化层抗HPM击穿效应的研究

随着集成度的不断提高,集成电路的绝缘层越来越薄.如CMOS器件绝缘层的典型厚度约为0.1μm,其相应的耐击穿电压在80～100V间.当器件特征尺寸进人深亚微来时,栅氧化层厚度仅为数纳米,而器件工作的电源电压却不宜降低,这使栅氧化层工作在较高的电场强度下,栅氧化层的抗电性能成为一个突出的问题.往往一个能量不算大的电磁脉冲,就可以让集成电路的栅氧击穿,将直接导致MOS器件的失效.     

超深亚微米器件的失效机理及其可靠性研究

集成电路的集成度不断攀升,集成化器件的特征尺寸已进入超深亚微米层次.小尺寸制造进程、超微细结构及超低功耗的工作环境,使诸多寄生效应、小尺寸效应严重地影响着器件的性能、电路的寿命.本文论述了基于超深亚微米层次小尺寸效应的诱因分析及器件,重点剖析了陷阱效应、短沟效应、热载流子效应和栅氧击穿对器件可靠性的影响.在此基础上,提出了抑制小尺寸效应、提高器件失效阈值、保障器件可靠性的若干工艺措施.     

磷离子注入对部分耗尽SOI MOS总剂量背栅效应的影响

本文研究了背栅磷离子注入加固技术对部分耗尽绝缘体上硅（silicon-on-insulator, SOI）MOS器件抗总剂量辐射性能提升的机理。认为可以对背栅沟道处进行磷离子注入,改变界面处的离子浓度分布,通过引入电子陷阱,抵消背栅界面陷阱俘获正电荷,从而改善背栅效应,提高器件的抗辐射性能。通过用高浓度磷离子对部分耗尽SOI NMOS器件背栅进行离子注入,大大减小了器件的背栅效应,实验器件的抗辐射能力能够达到1M rad（Si）。     

GaAs衬底深能级EL2与电路旁栅效应的光敏特性和迟滞现象

旁栅效应是制约GaAs集成电路性能和集成度的有害寄生效应。本文研究了MESFET电路的旁栅效应的光敏特性和迟滞现象 ,认为这两个现象可能与衬底深能级 (如EL2 )有密切的关系 ,通过减小衬底杂质补偿度有可能减轻旁栅效应影响。     

半绝缘非掺GaAs材料制备的MESFETs背栅效应

设计了一套适用于二种工艺(离子注入隔离工艺和半绝缘衬底自隔离工艺)的背栅效应测试版图,用选择离子注入形成有源层和欧姆接触区,在非掺杂的半绝缘GaAs衬底上制备GaAs MESFETs器件。研究了这二种不同工艺制备的MESFETs器件的背栅效应以及不同距离背栅电极的背栅效应大小。结果表明,采用离子注入隔离工艺制备的MESFETs器件的背栅效应要比采用半绝缘衬底自隔离工艺制备MESFETs器件的背栅效应小,背栅效应的大小与距离近似成反比,采用隔离注入的背栅阈值电压随距离变化的趋势比采用衬底自隔离的更大。     

GaAs衬底深能级EL2与电路旁栅效应的光敏特征和迟滞现象

旁栅效应是制约GaAs集成电路性能和集成度的有害寄生效应。本文研究了MESFET电路的旁栅效应的光敏特性和迟滞现象 ,认为这两个现象可能与衬底深能级 (如EL2 )有密切的关系 ,通过减小衬底杂质补偿度有可能减轻旁栅效应影响。     

陷阱效应对4H-SiC MESFET温度特性的影响

针对4H-SiC射频MESFET中的自热效应,建立了基于解析模型的材料参数温度模型和器件直流模型.研究了由陷阱造成的背栅效应,并结合材料的温度特性分析了温度升高对器件特性的影响.分析了陷阱对器件特性的影响,并进一步阐明了陷落-发射机制.计算得到陷阱能级为1.07eV,俘获截面为1×10-8cm2,器件的自升温达到100K以上,能够较好地反映实验结果.分析结果表明,背栅电势随陷阱浓度的增大而增大,并随着漏极电压的增大而减小,在室温下达到～3V.另外,由于器件中存在自热效应,背栅电势随漏压的变化加剧.这些模拟分析对实际器件的设计及工艺制造提供了理论上的依据.     

陷阱效应对4H-SiC MESFET温度特性的影响

针对4H-SiC射频MESFET中的自热效应,建立了基于解析模型的材料参数温度模型和器件直流模型.研究了由陷阱造成的背栅效应,并结合材料的温度特性分析了温度升高对器件特性的影响.分析了陷阱对器件特性的影响,并进一步阐明了陷落-发射机制.计算得到陷阱能级为1.07eV,俘获截面为1×10-8cm2,器件的自升温达到100K以上,能够较好地反映实验结果.分析结果表明,背栅电势随陷阱浓度的增大而增大,并随着漏极电压的增大而减小,在室温下达到～3V.另外,由于器件中存在自热效应,背栅电势随漏压的变化加剧.这些模拟分析对实际器件的设计及工艺制造提供了理论上的依据.     

半绝缘非掺GaAs材料制备的MESFETs背栅效应

设计了一套适用于二种工艺（离子注入隔离工艺和半绝缘衬底自隔离工艺）的背栅效应测试版图,用选择离子注入形成有源层和欧姆接触区,在非掺杂的半绝缘ＧａＡｓ衬底上制备ＧａＡｓＭＥＳＦＥＴｓ器件．研究了这二种不同工艺制备的ＭＥＳＦＥＴｓ器件的背栅效应以及不同距离背栅电极的背栅效应大小．结果表明,采用离子注入隔离工艺制备的ＭＥＳＦＥＴｓ器件的背栅效应要比采用半绝缘衬底自隔离工艺制备ＭＥＳＦＥＴｓ器件的背栅效应小,背栅效应的大小与距离近似成反比,采用隔离注入的背栅阈值电压随距离变化的趋势比采用衬底自隔离的更大．     

Temperature dependence of backgating effect in GaAs integrated circuits

The backgating effect in GaAs IC's has been found to be temperature dependent. The threshold voltage for backgating increases with temperature, resulting in lower backgating at higher temperatures. The measured activation energy of the backgating threshold versus temperature is 83 meV, in agreement with the energy difference between the Fermi level and the EL2 level at the surface of semi-insulating GaAs.     

Deep-Level Effects in GaAs Microelectronics: A Review

A considerable body of research literature on deep centers in GaAs is analyzed. It is shown that the issue remains most relevant to GaAs microelectronics. Data are discussed on the nature of deep centers in the bulk-grown and epitaxial forms of GaAs, whether ion-implanted or undoped. Methods for the characterization of deep centers are described. Theoretical models representing the influence of deep centers on the parameters of devices and ICs are considered. Particular coverage is given to backgating. Practical recommendations are reviewed for controlling the adverse effects of deep centers on the performance of GaAs devices and ICs.     

Reduction of backgating effect in MBE-Grown GaAs/AlGaAs HEMT's

We have investigated the backgating effect in high electron mobility transistors (HEMT's) fabricated on MBE-grown GaAs/AlGaAs layers, which is undesirable for LSI fabrication. Comparing five different types of devices, we related the backgating effect to the interface between the GaAs substrate and the undoped GaAs buffer layer. By using a thermally etched GaAs substrate, we successfully reduced the backgating to the same order as that of ion-implanted GaAs MESFET's.     

Analysis of kink-related backgating effect in GaAs MESFET

Two-dimensional simulation of backgating effect in a GaAs MESFET is made in which impact ionization of carriers and deep donors “EL2” in the substrate are considered. The kink-related backgating is reproduced, which is qualitatively consistent with recent experiments. Based on the simulated results, physical mechanism of kink-related backgating effect is discussed     

Carrier injection and backgating effect in GaAs MESFET's

The relation between the backgating effects on GaAs MESFET's and current conduction in the semi-insulating substrate is studied. The onset voltage of the backgating effect is found to coincide with the trap-fill-limited voltage for the substrate conduction. This observation implies that carrier injection in the substrate is directly related to the backgating effect.     

Backgating characteristics of MODFET structures

Significant backgating in mesa-isolated AlGaAs/GaAs MODFET structures is reported. Results are presented on the influence of backgate potential on the electrical characteristics of enhancement-mode MODFET's fabricated on MBE grown material. An observed zero threshold voltage for the onset of backgating is attributed to a high level of current leakage in the high-purity GaAs buffer layer. Transconductance and capacitance-voltage measurements on MODFET's show that the backgate potential influences primarily the electrical properties of the 2-D electron gas channel and the adjacent AlGaAs layer.     

Shielding of backgating effects in GaAs integrated circuits

Shielding of backgating effects in GaAs IC's by using Schottky metal, ohmic metal, and n⁺-implant has been studied. Contrary to what is expected from the electrostatic principle, positive bias to the shielding bars enhances backgating. Negative bias to the Schottky shielding bars increases the threshold for backgating, effectively reducing the backgating effect. These phenomena are explained in terms of carrier injection controlled by the surface potential. The results indicate that backgating effects can be reduced through proper circuit layout.     

Reduction of backgating in GaAs/AlGaAs MESFETs by optimisation of active-layer/buffer-layer interface

Backgating measurements made on GaAs MESFETs with abrupt, graded alloy and graded superlattice interface AlGaAs buffer layers were compared to measurements made on conventional GaAs buffer-layer MESFETs. Only the superlattice interface structure showed a reduction in the backgating transconductance (by a factor of 24 compared to the GaAs buffer-layer FET). The lack of reduction in the backgating transconductance for the abrupt and graded alloy interface devices is attributed to traps resulting from GaAs growth on an AlGaAs layer.     

Backgating in submicrometer GaAs MESFET's operated at high drainbias

GaAs 0.8-μm MESFETs were seen to exhibit an increased sensitivity to backgating when operated at drain voltages above 3.5 V. This is accompanied by an abrupt increase in the DC output conductance (kink effect) and an increase in the current flowing in the back-gate electrode. It is proposed that the increased sensitivity to backgating is due to the injection of holes, from the high-field region of the channel, into the semi-insulating substrate. The results suggest that conventional layout rules may not always be sufficient to avoid backgating in circuits based in submicrometer GaAs MESFETs