Avalanche robustness of SiC Schottky diode

Reliability is one of the key issues for the application of Silicon carbide (SiC) diode in high power conversion systems. For instance, in high voltage direct current (HVDC) converters, the devices can be submitted to high voltage transients which yield to avalanche. This paper presents the experimental evaluation of SiC diodes submitted to avalanche, and shows that the energy dissipation in the device can increase quickly and will not be uniformly distributed across the surface of the device. It has been observed that failure occurs at a fairly low energy level (< 0.3 J/cm²), on the edge of the die, where the electrical field intensity is the greatest. The failure results in the collapse of the voltage across the diode (short-circuit failure mode). If a large current is maintained through the diode after its failure, then the damage site is enlarged, masking the initial failure spot, and eventually resulting in a destruction of the device and an open circuit.     

SiC power Schottky and PiN diodes

The present state of SiC power Schottky and PiN diodes are presented in this paper. The design, fabrication, and characterization of a 130 A Schottky diode, 4.9 kV Schottky diode, and an 8.6 kV 4H-SiC PiN diode, which are considered to be significant milestones in the development of high power SiC diodes, are described in detail. Design guidelines and practical issues for the realization of high-power SiC Schottky and PiN diodes are also presented. Experimental results on edge termination techniques applied to newly developed, extremely thick (e.g., 85 and 100 μm) 4H-SiC epitaxial layers show promising results. Switching and high-temperature measurements prove that SiC power diodes offer extremely low loss alternatives to conventional technologies and show the promise of demonstrating efficient power circuits. At sufficiently high on-state current densities, the on-state voltage drop of Schottky and PiN diodes have been shown to be comparable to those offered by conventional technologies     

MEGA技术支持移动设备与汽车应用

移动导航设备、可拍照手机、汽车防盗系统等,都是当前产业的发展趋势。系统设计方面的主要目标是设计可充电电池的多功能移动装置,以及满足汽车产业对降低成本、节省能源、缩小体积与重量等方面要求的产品。为此,利浦半导体研发MEGA发Schottky二极管(Maximum Efficiency General Application),拱配改良型分离式“Low VCESAT(BISS)晶体管     

A novel SiC high-k superjunction power MOSFET integrated Schottky barrier diode with improved forward and reverse performance

A new SiC superjunction power MOSFET device using high-k insulator and p-type pillar with an integrated Schottky barrier diode(Hk-SJ-SBD MOSFET) is proposed, and has been compared with the SiC high-k MOSFET(Hk MOSFET), SiC superjuction MOSFET(SJ MOSFET) and the conventional SiC MOSFET in this article. In the proposed SiC Hk-SJ-SBD MOSFET, under the combined action of the p-type region and the Hk dielectric layer in the drift region, the concentration of the N-drift region and the current spreadi...     

Soft-switching boost chopper for diode bridge power factorcorrection

A new soft-switching boost chopper, which can be utilised for diode-bridge power factor correction, is presented. The soft-switching cell is composed of two switch-diode pairs linked by an inductor and a capacitor in parallel The soft-switching scheme is verified by means of PSPICE simulation and prototype experiment     

高功率110 GHz平衡式肖特基二极管频率倍频器

高频段的太赫兹信号通常是由多个倍频器级联输出的,因此要求倍频链路的前级必须具备高输出功率的能力。为了提升太赫兹倍频器的功率容量和效率,结合高频特性下肖特基二极管有源区电气模型建模方法,采用高热导率的陶瓷基片,利用对称边界条件,在HFSS和ADS中实现对倍频器电路的分析和优化,研制出了高功率110 GHz平衡式倍频器。最终测试结果表明,驱动功率为28 dBm左右时,该倍频器在102~114.2 GHz的工作带宽内的最高输出功率和效率分别为108 mW和17.6%,为链路后续的二倍频和三倍频提供足够的驱动功率。     

A 119 GHz planar Schottky diode mixer for a space application

A planar single-ended GaAs Schottky diode mixer has been designed, built, and tested at 119 GHz. The mixer front end includes also a waveguide filter for image rejection, and a temperature compensated ring filter. Measurements at room temperature showed a conversion loss of 7 dB and a noise temperature of 900 K (SSB). At 100 K the measured noise temperature of the mixer was 500 K (SSB).     

Dual metal SiC Schottky rectifiers with low power dissipation

Nickel and titanium are the most commonly used metals for Schottky barrier diodes on silicon carbide (SiC). Ti has a low Schottky barrier height (i.e. 0.8 eV on 6H-SiC), whilst Ni has a higher barrier (i.e. 1.25 eV). Therefore, the first metal allows to achieve a low forward voltage drop V_F but leads to a high leakage current. On the other hand, the second one presents the advantage of a lower reverse leakage current but has also a high value of V_F. In this work, dual-metal-planar (DMP) Schottky diodes on silicon carbide are reported. The rectifying barrier was formed by using an array of micrometric Ti and Ni₂Si (nickel silicide) stripes. This low/high Schottky barrier allowed to combine the advantages of the two metals, i.e. to fabricate diodes with a forward voltage drop close to that of a Ti diode and with a level of reverse current comparable to that of a Ni₂Si diode. Under the application point of view, using this kind of barrier can lead to a reduction of the device power dissipation and an increase of the maximum operating temperature.     

Effect of a buffer layer in the epi-substrate region to boost the avalanche capability of a 100V Schottky diode

The aim of this paper is to give an insight and a possible explanation of the limitations in the Reverse Bias Safe Operating Area of 100V Si Power Schottky Diodes. Starting from experiments and going through device simulations and theory a physical explanation of device failure both in short (i.e. isothermal) and long pulse are explained. With the help of the theoretical analysis an improvement of the design is proposed to increase avalanche capability of these devices and preliminary experimental data are reporting a very promising increase of both the maximum sustainable current in avalanche condition and the maximum sustainable avalanche energy in UIS conditions.     

Conduction power loss in MOSFET synchronous rectifier withparallel-connected Schottky barrier diode

The conduction power loss in an MOSFET synchronous rectifier with a parallel-connected Schottky barrier diode (SBD) was investigated. It was found that the parasitic inductance between the MOSFET and SBD has a large effect on the conduction power loss. This parasitic inductance creates a current that is shared by the two devices for a certain period and increases the conduction power loss. If conventional devices are used for under 1 MHz switching, the advantage of the low on-resistance MOSFET will almost be lost. To reduce the conduction loss for 10 MHz switching, the parasitic inductance must be a subnanohenley     

Comprehensive review of high power factor ac-dc boost converters for PFC applications

High power factor rectifiers have been consolidated as an effective solution to improve power quality indices in terms of input power factor correction, reduction in the total harmonic distortion of the input current and also regulated dc voltages. Within this context, this subject has motivated the introduction of numerous converter topologies based on classic dc-dc structures associated with novel control techniques, thus leading to the manufacturing of dedicated integrated circuits that allow high input power factor by adding a front-end stage to switch-mode converters. In particular, boost converters in continuous current mode (CCM) are widely employed since they allow obtaining minimised electromagnetic interference levels. This work is concerned with a literature review involving relevant ac-dc single-phase boost-based topologies with high input power factor. The evolution of aspects regarding the conventional boost converter is shown in terms of improved characteristics inherent to other ac-dc boost converters. Additionally, the work intends to be a fast and concise reference to single-phase ac-dc boost converters operating in CCM for engineers, researchers and experts in the field of power electronics by properly analysing and comparing the aforementioned rectifiers.     

基于石英基片的W波段高输出功率肖特基二极管倍频器

W-band quartz based high output power fix-tuned doublers are analyzed and designed with planar Schot- tky diodes. Full-wave analysis is carried out to find diode embedding impedances with a lumped port to model the nonlinear junction. Passive networks of the circuit, such as the low pass filter, the E-plane waveguide to strip transitions, input and output matching networks, and passive diode parts are analyzed by using electromagnetic simulators, and the different parts are then combined and optimized together. The exported S-parameters of the doubler circuit are used for multiply efficiency analysis. The highest measured output power is 29.5 mW at 80 GHz and higher than 15 mW in 76-94 GHz. The highest measured efficiency is 11.5% at 92.5 GHz, and the typical value is 6.0% in 70-100 GHz.     

Influence of pinning trap in Ti/4H–SiC Schottky barrier diode

Ti/4H–SiC Schottky barrier diode without any intentional edge termination is fabricated. The obtained properties, low on-resistance of 3 mΩ cm² and low leakage current of 10⁻⁴ A/cm² at 1000 V, are evaluated by device simulation considering pinning at metal/semiconductor interface. The breakdown voltage is explained by minimization of electric field enhancement at the Schottky electrode edge due to pinning. The leakage current corresponds to Schottky barrier tunneling current depending on drift layer doping and Schottky barrier height.     

Schottky diode analysis for evaluation of RIE effects on silicon surfaces

Electrical measurements on titanium-Schottky diodes were used to evaluate the effects of reactive ion etching (RIE) processing and various post-RIE treatments on silicon substrates. Based on a model for the Schottky barrier with an interfacial layer, the measurements allow one to estimate the effect of an oxygen treatment or an O₂-RIE clean-up with a wet chemical etch on the C- and F-containing insulator layer and the residual damage to a silicon surface by different RIE systems. It was shown that the oxygen treatment reduced the thickness of the “polymeric” layer, and decreased the density of surface states. A significant residual damage after O₂ clean-up with HF dip was found for the CF₄/H₂ system. Lastly, the effect of thermal annealing at 950°C was investigated, and it was found that it gives rise to an increased density of surface states.     

A new soft-switched PFC boost rectifier with integrated flyback converter for stand-by power

This paper presents a magnetic integration approach that reduces the number of magnetic components in a power supply by integrating magnetic components in two conversion stages. Specifically, in the proposed approach, a single transformer is used to implement the continuous-conduction-mode boost power-factor-corrected (PFC) converter and the dc/dc flyback converter. The integrated boost and flyback converters offer soft switching of all semiconductor switches including a controlled di/dt turn-off rate of the boost rectifier. The performance of the proposed approach was evaluated on a 150-kHz, 450-W, universal-line range boost PFC converter with 12-V/2.2-A integrated stand-by flyback converter.     

一种用于单相Boost型PFC中的数字预测算法

本文提出了用于数字控制PFC中的一种新颖的数字控制算法,称为预测算法。它可以得到较高的PF值,并且随着输入电压或者负载电流的变化有近似最快的动态响应。对于一个确定的系统,预测算法根据系统当前的状态参数,可以估算出输出电压和电感电流在下一个开关周期的变化趋势,并且得到一组完美跟踪输入电压轨迹最优的控制序列。在多种仿真条件下的仿真结果证实了预测算法的有效性。当输入电压从90V到265V,负载电流从20%~100%范围变化时,PF值都大于0.998。启动时间和恢复时间分别约为0.1s和0.02s,且无超调。实验结果也验证了设计的有效性。     

Implementation and performance evaluation of DSP-based control for constant-frequency discontinuous-conduction-mode boost PFC front end

A digital signal processor (DSP) implementation of digital control for constant-frequency, discontinuous-conduction-mode boost power-factor-correction converter for universal line-voltage (90-264 V/sub rms/) applications is presented. A step-by-step design procedure based on digital redesign technique is also provided. The performance evaluation of the proposed DSP control is performed on a 400-W prototype. It was shown that the implemented DSP-based control can achieve a power factor higher than 0.99 in the entire line range.     

Theoretical comparison of SiC PiN and Schottky diodes based on power dissipation considerations

In order to select the optimal device for a particular application, designers must carefully analyze the tradeoffs between competing devices. Recent progress in SiC power rectifiers has resulted in the demonstration of high-voltage PiN and Schottky barrier diodes (SBDs). With both technologies maturing, power electronics engineers will soon face the task of selecting between these two devices. Until recently, the choice was simple, since silicon SBDs are only available for relatively low voltage applications. The choice is not as clear when considering SiC diodes, and guidelines for determining the proper application of each are needed. The purpose of this paper is to provide such guidelines, based on an analysis of the most significant tradeoffs involved.     

平面肖特基二极管的制作

为研究制作THz频段下工作的肖特基二极管器件,系统研究了平面肖特基二极管的制作工艺。通过分子束外延(MBE)生长了掺杂浓度分别为5×1018 cm-3的缓冲层和2×1017 cm-3的外延层,并研究温度对厚度的影响,使得膜层厚度控制良好,晶格完整。通过参数控制,减小了等离子体增强化学气相沉积(PECVD)的SiO2钝化层应力,使压指结构的翘曲情况得以改善。研究了不同退火温度下欧姆接触的情况,使接触电阻率减小到0.8×10-7 ?/cm2。用电子束光刻和干法刻蚀制作了亚微米级的阳极区域,结合GaAs湿法刻蚀的速率控制,完成了表面沟道的制作,制作出完整的平面肖特基二极管。通过I-U曲线理论计算,二极管的截止频率达到太赫兹量级,为后续工作奠定了基础。     

Characterization of erbium-silicided Schottky diode junction

Trap density, lifetime, and the Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted trap density, lifetime, and Schottky barrier height for hole are determined as 1.5/spl times/10/sup 13/ traps/cm/sup 2/, 3.75 ms and 0.76 eV, respectively. By using the developed method, the interface of the Schottky diode can be evaluated quantitatively.