Adaptive double recycling folded cascode amplifier

Analog Integrated Circuits and Signal Processing - A new structure for improving the performance of recycling folded cascode (RFC) operational transconductance amplifier (OTA) is presented. The...     

A power-efficient improved recycling folded cascode amplifier

An improved recycling folded cascode amplifier for wide-bandwidth ΣΔ modulator is presented in this article. The proposed amplifier introduces internal positive-feedback pairs to achieve a significant boost in transconductance and DC gain without increasing power or area budget. The proposed recycling folded cascode amplifier was implemented in SMIC standard 65?nm CMOS process. Compared to other recycling folded cascode structures, simulation results show that the proposed amplifier achieves the enhancement of gain-bandwidth and DC gain with the best figure-of-merits.     

A transconductance enhanced recycling structure for folded cascode amplifier

This letter is to present a transconductance enhanced recycling structure for folded cascode amplifier. The proposed structure introduces a positive feedback path to achieve a significant boost in transconductance without increasing power or area consumption. A folded cascode amplifier using the proposed structure was implemented in SMIC standard 65 nm CMOS process. Simulation results show that the proposed amplifier achieves 400% improvement in gain-bandwidth and 16.6 dB boost in DC gain compared to the conventional folded cascode.     

Enhancing general performance of folded cascode amplifier by recycling current

A modification to the conventional folded cascode transconductance amplifier is proposed. The proposed amplifier has the benefit of achieving a given set of design specifications while consuming a fraction of the power compared to the conventional folded cascode. Moreover, the proposed modification is robust even for low voltage applications.     

改进型循环折叠共源共栅放大器的分析与实现

本文分析并实现了一种改进型循环折叠共源共栅放大器（IRFC）。本文分析了IRFC并将其与循环折叠共源共栅放大器（RFC）和传统折叠共源共栅放大器（FC）进行了比较,并证明IRFC能显著提升跨导、压摆率和噪声性能。放大器由0.13微米工艺实现,测试结果表明在相同功耗和面积的条件下,IRFC的单位增益带宽和压摆率是FC的3倍,并且是RFC的1.5倍。     

Multipath recycling method for transconductance enhancement of folded cascade amplifier

A multipath recycling method to enhance transconductance of the folded cascode amplifier is presented in this paper. The proposed method utilizes two idle paths to conduct small signal current, which leads to significant enhancement of transconductance compared to conventional folded cascade structure. Moreover, the improved performance is almost at no expense of power dissipation. The proposed multipath recycling and the conventional amplifiers are all designed in UMC 0.18 μm CMOS technology. Simulation results demonstrate that the transconductance of the proposed amplifier is improved by 450% and dc gain enhances 16 dB when compared with the folded cascode counterpart.     

改进型折叠式共源共栅运算放大器电路的设计

在套筒式共源共栅、折叠式共源共栅运放中,折叠式共源共栅运算放大器凭借较大的输出摆幅和偏置电压的较低等优点而得到广泛运用。但是,折叠式的这些优势是以牺牲较大的功耗、较低的电流利用率而换取的。本文以提高电流利用率为着手点设计了一种改进的折叠式共源共栅运算放大器,在相同的电压和负载下改进的折叠式共源共栅运算放大器能显著提升跨导、压摆率和噪声性能。仿真结果表明在相同功耗和面积的条件下,改进的折叠式共源共栅运算放大器的单位增益带宽和压摆率是折叠式共源共栅运放的3倍。     

A very high-frequency CMOS complementary folded cascode amplifier

A wide-band, fast settling CMOS complementary folded cascode (CFC) transconductance amplifier for use in analog VLSI high frequency signal processing applications is introduced. The superior performance of the CFC architecture over that of the folder cascode (FC) or mirrored cascode (MC) approaches for VLSI amplifiers is demonstrated. The symmetrically configured complementary input stage provides a wide common-mode input voltage range. The amplifier performs as an operational transconductance amplifier (OTA) and displays a first-order dominant pole when loaded by a shunt capacitor. The transconductance amplifier is small in area (0.016 mm²), and well suited for high frequency analog signal processing applications. Simulation and experimental results demonstrate a DC gain of approximately 50 dB, with a 0.1% settling response of under 10 ns for loads varied from 0 to 2 pF     

Post-linearization of cascode CMOS low noise amplifier using folded PMOS IMD sinker

A post-linearization technique for the cascode complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) is presented. The proposed method uses an additional folded cascode positive-channel metal oxide semiconductor field-effect transistor for sinking the third-order intermodulation distortion (IMD3) current generated by the common source stage, while minimizing the degradation of gain and noise figure. This technique is applied to enhance the linearity of CMOS LNA using 0.18-/spl mu/m technology. The LNA achieved +13.3-dBm IIP3 with 12.8-dB gain, 1.4dB NF at 2GHz consuming 8mA from a 1.8-V supply.     

Design and analysis of DC gain and transconductance boosted recycling folded cascode OTA

A new technique for improving the transconductance and low frequency output impedance of recycling folded cascode (RFC) amplifiers is presented. This enhancement was achieved by using a positive feedback and upgrading the recycling structure. The new structure profits from better transconductance, slew rate, and DC gain in comparison with conventional folded cascode (FC) amplifier. Moreover, the input referred noise is reduced and the phase-margin improved. The enhanced amplifier, simulated in 0.18 μm CMOS technology, exhibits a DC gain enhancement of 16.3 dB as well as 115.5 MHz increase in gain bandwidth compared to conventional FC configuration. The amplifier consumes 360 μW @ 1.2 V which makes it suitable for low-voltage applications.     

Self-biasing of folded cascode CMOS op-amps

In cascode CMOS op-amps a large number transistors are biased using independent standard bias circuits. This results in numerous drawbacks, namely, an area and power overhead, and high sensitivity of the bias point to process variations. In this paper we present a self-biasing technique for folded cascode CMOS op-amps that uses no additional devices and no bias voltages other than the two supply rails. The resulting self-biased op-amps are free from the above mentioned drawbacks and exhibit the same performance as existing folded cascode op-amps. This is achieved by following transistor sizing constraints derived through detailed circuit analysis. The technique is applied to an existing high performance op-amp. Simulation results show that the high performance is maintained while nine bias voltages are eliminated.     

Novel cross-connected cascode differential amplifier

We report on a novel amplifier circuit–differential cross-connected cascode1 1.?Reported briefly on WSEAS and ICECS Conferences. . Its fundamental distinction from an ordinary differential cascode lies in simultaneous feeding of input signal both to the common emitter (source) and common base (gate) stages, which are cross-connected. Such a connection results in the creation of two loops of positive current feedback. The stability of the amplifier is achieved due to low gain and phase shift in the loops. We show that the input signal is amplified in the input circuit. The input and output impedances are gained significantly as well. The current gain is increased considerably and the bandwidth is essentially expanded. Simulation results of such a cascode designed with IBM BJT sige5am and CMOS bicmos7hp transistors are presented. When compared with the ordinary cascode, the predicted and actually obtained bandwidths proved to be more than twice as wide: 8.6–18.7 GHz and 3.4–8.7 GHz on BJT and CMOS based, respectively.     

一种提高放大器增益和带宽的设计技术分析

运算放大器是信号处理中的基础模块,是高性能混合信号数据转换器、片上系统(SoC)等的重要组成部分。低功耗和高性能的基础电路模块成为系统发展的瓶颈,因此对增益和带宽增强型运算放大器的研究成为业界关注的焦点。为了研究运算放大器增益和带宽优化设计技术,实现低功耗高性能的解决方案,对电流重用技术的产生背景和技术演进作了较为详细的分析,体现了在技术进步过程中对结构的优化和改进,对高性能系统集成设计具有重要的参考意义。     

1-V power supply CMOS cascode amplifier

We design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69-dB DC gain, a 2-MHz bandwidth, and compatible input- and output voltage levels at a 1-V power supply. This is done by a novel, current driven bulk (CDB) technique, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique     

A SiGe MMIC variable gain cascode amplifier

A silicon-germanium variable gain cascode amplifier has been developed to combine the functionality of an amplifier and an attenuator into one monolithic microwave integrated circuit (MMIC). The cascode amplifier, which was designed for a 7-11 GHz frequency range, achieved a gain of 12.5 dB, an input return loss of 7.5 dB, and an output return loss of 12.5 dB. The cascode amplifier exhibited 16 dB of gain control.     

100-GHz high-gain InP MMIC cascode amplifier

A high-gain InP monolithic millimeter-wave integrated circuit (MMIC) cascode amplifier has been developed which has 8.0 dB of average gain from 75 to 100 GHz when biased for maximum bandwidth, and more than 12 dB of gain at 80 GHz at the maximum-gain bias point, representing the highest gains reported to date, obtained from MMICs at W band (75-100 GHz). Lattice-matched InGaAs-InAlAs high-electron-mobility-transistors (HEMTs) with 0.1-μm gates were the active devices. A coplanar waveguide (CPW) was the transmission medium for this MMIC with an overall chip dimension of 600×500 μm     

A cascode modulated class-E power amplifier for wireless communications

A cascode modulated CMOS class-E power amplifier (PA) is presented in this paper. It is shown that by applying a modulated signal to the gate of the cascode transistor the output power is modulated. The main advantage of the proposed technique is a high 35 dB output power dynamic range. The peak power added efficiency (PAE) is 35%. The concept of the cascode power control of class-E RF PA operating at 2.2 GHz with 18 dBm output power was implemented in a CMOS technology and the performance has been verified by measurements. The prototype CMOS PA is tested by single tone excitation and by enhanced data rates for GSM evolution (EDGE) modulated signal. Digital predistortion is used to linearize the transfer characteristic. The EDGE spectrum mask is met and the rms error vector magnitude (EVM) is less than 4° in the entire output power range.     

Dispersion-compensating Raman/EDFA hybrid amplifier recycling residual Raman pump for efficiency enhancement

We experimentally demonstrate a novel concept of the dispersion-compensating Raman/erbium-doped fiber amplifier hybrid amplifier recycling residual Raman pump for increase of overall power conversion efficiency. The proposed dispersion-compensating hybrid amplifier system has only one pump source for Raman amplification in the dispersion-compensating fiber (DCF) and the residual pump power after the DCF is recycled for secondary signal amplification in an erbium-doped fiber cascaded to the DCF. Using the proposed scheme, we achieve the significant enhancement of both signal gain and effective gain-bandwidth by 15 dB (small signal gain) and 20 nm, respectively, compared to the performance of the Raman-only amplifier.     

Novel low-voltage ultra-low-power DVCC based on floating-gate folded cascode OTA

In this paper a novel low-voltage ultra-low-power differential voltage current conveyor (DVCC) based on folded cascode operational transconductance amplifier OTA with only one differential pairs floating-gate MOS transistor (FG-MOST) is presented. The main features of the proposed conveyor are: design simplicity; rail-to-rail input voltage swing capability at a low supply voltage of ±0.5 V; and ultra-low-power consumption of mere 10 μW. Thanks to these features, the proposed circuit could be successfully employed in a wide range of low-voltage ultra-low-power analog signal processing applications. Implementation of new multifunction frequency filter based on the proposed FG-DVCC is presented in this paper to take the advantages of the properties of the proposed circuit. PSpice simulation results using 0.18 μm CMOS technology are included as well to validate the functionality of the proposed circuit.     

On the performance of the differential cascode amplifier

Analysis is made of the differential cascode amplifier stage, an amplifier made of a differential common-emitter input pair driving a differential common-base output pair referenced to the emitter potential of the input pair. The analysis shows the differential cascode amplifier to have one or more orders of magnitude increase in common-mode input resistance and common-mode rejection ratio compared to that of a conventional differential pair. Consideration is also given to the use of junction field-effect transistors for either pair in the differential cascode stage. The frequency response of the stage is studied, and a potentially troublesome common-mode complex pole pair is identified as the one disadvantage of the differential cascode circuit.