A low-power,low-noise and high linearity 60 GHz wideband CMOS low-noise amplifier for wireless personal area network (WPAN) systems

A low power and low noise figure (NF) 60 GHz wideband low-noise amplifier (LNA) with excellent phase linearity for wireless personal local network (WPAN) systems using standard 90 nm CMOS technology is reported. To achieve sufficient power gain (S₂₁) and reverse isolation (S₁₂), the LNA comprises a common-source (CS) stage followed by a cascode stage and a CS stage. The LNA consumes 14.1 mW, achieving S₁₁ better than ?10 dB for frequencies 55.1–59.5 GHz, S₂₂ better than ?10 dB for frequencies 55.1–59.4 GHz, S₁₂ better than ?42.6 dB for frequencies 50–64 GHz, and group delay variation smaller than ±13.25 ps for frequencies 50.4–63 GHz. Additionally, high and flat S₂₁ of 9.9 ± 1.5 dB is achieved for frequencies 50.4–62.9 GHz, which means the corresponding 3-dB bandwidth is 12.5 GHz. Furthermore, the LNA achieves minimum NF of 3.88 dB at 55.5 GHz and NF of 4.73 ± 0.85 dB for frequencies 50–63.5 GHz, one of the best NF results ever reported for a 60 GHz CMOS LNA.     

3-10 GHz low-power, low-noise CMOS distributed amplifier using splitting-load inductive peaking and noise-suppression techniques

A CMOS distributed amplifier (DA) with flat and low noise figure (NF), and flat and high gain (S ₂₁) is demonstrated. A flat and low NF was achieved by adopting a RL terminating network for the gate transmission line, and a slightly under-damped Q-factor for the second-order NF response. Besides, flat and high S ₂₁ was achieved using the proposed cascade gain cell, which constitutes a cascode-stage with a low-Q RLC load and a splitting-load inductive-peaking inverter stage. In the high-gain (HG) mode, the DA consumed 27.6 mW and achieved S ₂₁ of 17.5 plusmn 1.23 dB with an average NF of 3.24 dB over the 3-10 GHz band, one of the best reported NF performances for a CMOS UWB DA or LNA in the literature. The measured IIP3 was 2.1 dBm (at 8 GHz). In the low-gain (LG) mode, the DA achieved S ₂₁ of 10.74 plusmn 1.2 dB and an average NF of 4.67 dB with a low power dissipation of 9 mW.     

Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in 0.18 μm CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9 dB NF, 50 Ω input impedance, 1 GHz 3 dB power bandwidth, 20.5 dB power gain (S₂₁), high reverse isolation (S₁₂)<−48 dB, −18.5 dB input matching (S₁₁) and −21.3 dB output matching (S₂₂), while dissipating as low power as 2 mW at 1.8 V power supply.     

A Reconfigurable Low-Noise Amplifier Using a Tunable Active Inductor for Multistandard Receivers

A reconfigurable low-noise amplifier (LNA) based on a high-value active inductor (AI) is presented in this paper. Instead of using a passive on-chip inductor, a high-value on-chip inductor with a wide tuning range is used in this circuit and results in a decrease in the physical silicon area when compared to a passive inductor-based implementation. The LNA is a common source cascade amplifier with RC feedback. A tunable active inductor is used as the amplifier output load, and for input and output impedance matching, a source follower with an RC network is used to provide a 50 Ω impedance. The amplifier circuit has been designed in 0.18 µm CMOS process and simulated using the Cadence Spectra circuit simulator. The simulation results show a reconfigurable frequency from 0.8 to 2.5 GHz, and tuning of the frequency band is achieved by using a CMOS voltage controlled variable resistor. For a selected 1.5 GHz frequency band, simulation results show S ₂₁ (Gain) of 22 dB, S ₁₁ of ?18 dB, S ₂₂ of ?16 dB, NF of 3.02 dB, and a minimum NF (NFmin) of 1.7 dB. Power dissipation is 19.6 mW using a 1.8 V dc power supply. The total LNA physical silicon area is (200×150) µm².     

A SiGe LC-ladder low noise amplifier with base resistance match,gain and noise flatness for UWB applications

This study presents a 3.1–10.6 GHz ultra-wideband low noise amplifier (UWB LNA) in 0.18 µm SiGe HBT technology. To achieve a good input match, parasitic base resistance in a bipolar transistor and an LC-ladder filter are included into calculations with the common-emitter topology using shunt–shunt capacitive feedback. Both high and flat power gain (S₂₁) and low and flat noise figure (NF) are achieved by adjusting the pole and zero in amplifying stage and quality factors of the fourth-order input network. Design equations for performances such as gain, noise figure and linearity IIP3 are derived especially on gain flatness and noise flatness. LNA dissipates 33 mW power and achieves S₂₁ of 20.65+0.7 dB, NF of 2.79+0.2 dB over the band of 3.1–10.6 GHz. The simulated input third-order intermodulation point (IIP3) is −17 dBm at 10 GHz.     

A technique for bandwidth extension and noise optimization of wideband low-noise amplifier with dual feedback loops

A technique for bandwidth extension and noise optimization of wideband low-noise amplifier with dual feedback loops is presented. A LC-ladder matching network has been added in front of conventional amplifier with dual feedback loops. Detailed circuit analysis and general design procedures for the modified amplifier have been provided. The technique is applied to an amplifier covering the frequency range from DC to 6 GHz in a 0.5 μm InGaAs E-mode pHEMT process. Post-layout simulation shows S ₁₁ below ?10 dB, S ₂₂ below ?10 dB, flat S ₂₁ of 16 ± 0.2 dB, and flat NF of 1.85 ± 0.35 dB across the entire band, which confirms the improvement in bandwidth and noise performance.     

A full-band UWB common-gate band-pass noise matched g m -boosted series peaked CMOS differential LNA

This paper presents a low-power noise-matched fully-differential common-gate (CG) low noise amplifier (LNA) for ultrawideband receiver operating in the full 3.1–10.6 GHz band. Performance was optimized by employing the transconductance ‘g _m ’ boosted CG LNA topology with series peaking along with an input noise matching network. A common source g _m -boosting amplifier, in conjunction with an LC T-network, was used to share the bias current with the CG stage. The LNA was demonstrated using a 130 nm IBM CMOS process technology and it consumed 7 mW from a 1 V supply. It exhibited an input return loss (S₁₁) and an output return loss (S₂₂) of ?10.5 and ?14 dB respectively. In addition, it also achieved a forward power gain (S₂₁) of 14.5 dB and a noise figure between 4.5 and 5.0 dB.     

2.3–21 GHz broadband and high linearity distributed low noise amplifier

This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S₂₁), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation and equalization of phase velocity techniques, to absorb their parasitic capacitances into the gate and drain transmission lines in order to achieve wide bandwidth and to enhance gain and linearity. The proposed broadband DA achieved an excellent gain in the flatness of 13.5 ± 0.2 dB, a low noise figure of 3.44 ± 1.12 dB, and a small group delay variation of ±19.721 ps over the range of 2.3–21 GHz. The input and output reflection coefficients S₁₁ and S₂₂ are less than −10 dB. The input compression point (P_1dB) and input third-order intercept point (IIP3) are −1.5 dBm and 11.5 dBm, respectively at 13 GHz. The dissipated power is 282 mW and the core layout size is 2.2 × 0.8 mm².     

Capacitor Cross-Coupled Fully-differential CMOS Folded Cascode LNAs with Ultra Low Power Consumption

This paper proposes a fully-differential folded cascode low noise amplifier (LNA) for 5.5 GHz receiver in 180 nm CMOS technology. By improving folded cascode with an additional inductance connected at the gate of CG stage to cancel parasitic capacitance and then employing capacitor cross-coupled technique as a negative feedback in the proposed LNA, the performance of the LNA can be improved significantly in terms of gain (S21) and noise figure (NF) compared with the conventional fold cascode LNA. Furthermore, the DC power consumption of the LNA is further reduced with forward body bias topology. The measurements show the proposed LNA achieves 16.5 dB power gain, a NF of 1.53 dB, good input/output matching with the S11 and S22 are less than \(-\) 15 dB. And the operating voltage is only 0.5 V with ultra-low power consumption of 0.89 mW.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

Inductor-less PVT robust gain switching balun LNA for multistandard applications

An inductor-less single to differential low-noise amplifier (LNA) is proposed for multistandard applications in the frequency band of 0.2–2 GHz. The proposed LNA incorporates noise cancellation and voltage shunt feedback configuration to achieve minimum noise characteristics and low power consumption. In addition to noise cancellation, trans-conductance of common-source stage is scaled to improve the noise performance. In this way, noise figure (NF) of LNA below 3 dB is achieved. An additional capacitor C_c is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power efficiency. The bias point of all transistors is chosen such that the variation in g_m is not more than 10%. The proposed LNA is implemented in UMC 0.18-μm RF CMOS technology. The core area is 182 μm × 181 μm. Moreover, the LNA has better ratio of relevant performance to area. The proposed balun LNA is validated by rigorous Monte Carlo simulation. The 3σ deviation of gain and NF is less than 5%. Finally, the proposed LNA is robust to unavoidable PVT variations.     

Two-port noise figure optimization of source-degenerated cascode CMOS LNAs

This paper presents a noise figure optimization technique for source-degenerated cascode CMOS LNAs with lossy gate inductors. The optimization technique, based on two-port theory, takes into account second order parasitic components. The effect of inductive source degeneration on LNA noise parameters is discussed. Measured noise figures agree well with the simulations confirming the accuracy of the noise model and allowing us to investigate the contributions of various components to the overall noise figure. A 0.18-μm CMOS LNA with an integrated inductor (Q = 7.5) achieves a noise figure of 1.16 dB and a return loss of 20 dB at 1.4 GHz, drawing 39 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 14.5 dB, input P1dB of ?17.5 dBm, and input IP3 of ?13 dBm. LNAs with external inductors having quality factor of Q = 170 and Q = 40 achieve noise figures of 0.65 dB and 0.68 dB and a return loss of 20 dB at 1.4 GHz, drawing 37 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 17 dB, input P1dB of ?22 dBm, and input IP3 of ?14 dBm. The large power consumption of the presented designs was intentionally selected in order to reduce the noise figure, an acceptable trade-off for LNA’s targeted for radio telescope applications, and to assess the impact of the large currents flowing through interconnect metals on the noise figure     

（英）CMOS毫米波低功耗超宽带共栅低噪声放大器

本文陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA)。该LNA用标准90-nm RF CMOS工艺实现并具有如下特征：在28.5到39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27到42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2 dB,平均NF在27-42 GHz频段内为5.1 dB;S₁₁在整个测试频段内小于-11 dB。40 GHz处输入三阶交调点(IIP3)的测试值为 2 dBm。整个电路的直流功耗为5.3 mW。包括焊盘在内的芯片面积为0.58*0.48 mm2_。     

A Two Stage Variable-Gain Low-Noise Amplifier for X-Band in 0.18 µm CMOS

In this paper a variable gain low noise amplifier (VG-LNA) is designed and analyzed for X band in 0.18 µm CMOS technology. A two-stage structure is utilized in the proposed VG-LNA and its gain, which is controlled by an on-chip voltage (V_cnt), has continuous and almost linear variations. The required range for V_cnt can be initiated from 0.5 V, also the variations of gain doesn’t ruin reflection loss (S11), return loss (S12) and noise figure (NF). The best performance of this VG-LNA is at 10 GHz frequency with 1 GHz bandwidth. In the center frequency, the maximum gain is 20.8 dB that continuously and linearly decreases to 4 dB by increasing V_cnt. Also S11 and S12 in this frequency are lower than ?27 and ?38 dB, respectively. NF is lower than 2 dB in the mentioned frequency range and NF_min is equal to 1.2 dB, while the third-order intercept point (IIP3) equals to 8.27 dBm in the best condition and always stays above ?10 dBm. The main advantage of the proposed structure in compare with the similar structures is not only the key parameters don’t ruin by the gain variations, but also increment of V_cnt operation range (0.5 V to V_dd), leads to expanding gain control range. These results are achieved while the power consumption is 8.4 mW with 1.8 V supply voltage and the chip area is 0.56 mm².     

2 to 23 GHz BiFET low noise amplifier design flow and implementations in 0.25 μm SiGe BiCMOS technology

Two BiFET LNAs are here reported, implemented in a 0.25 μm BiCMOS technology from ST Microelectronics. First of them, dedicated to WCDMA standard, depicts a 15.5 and 2.85 dB, S₂₁ and noise figure (NF), respectively, under 2 mA current consumption. The second realization operates at 23 GHz for Mini-Link application. It provides a 14 dB gain and 7 dB at 22 GHz NF for an 8.2 mA current consumption under 2.5 V. Both circuits were designed according to a design flow, here depicted, based on input matching, NF and gain optimisation. A large part of the article also deals with high frequency layout considerations. Indeed useful techniques dedicated to integrated microstrip waveguides and RF inter-connections are proposed based on 3D electromagnetic field simulations.     

A dual mode 2.4-GHz CMOS low noise amplifier employing body biasing

This paper presents a dual mode CMOS low noise amplifier (LNA) suitable for Worldwide Interoperability for Microwave Access applications, at 2.4?GHz. The design concept is based on body biasing. An off chip Digital to Analog Converter is used to generate the proper body bias voltage to control the LNA gain and linearity. Measurement results show that in the high gain mode, for V _BS?=?0.3?V, the cascode LNA, implemented in a 0.13???m CMOS standard process, exhibits a 14?dB power gain, a 3.6?dB noise figure (NF) and ?4.6?dBm of third order intercept point (IIP3) for a 4?mA current consumption under 1?V supply. Tuning V _BS to ?0.55?V, switches the LNA into the low gain mode. It achieves 8.6?dB power gain, 6.2?dB NF and 6?dBm IIP3 under a constrained power consumption of 1.7?mW.     

A 4 mW 3–5 GHz current reuse g<Subscript>m</Subscript>-boosted short channel common-gate CMOS UWB LNA

A novel architecture is presented to optimize the noise performance and the power consumption of the transconductance ‘g_m’ boosted common-gate (CG) ultrawideband (UWB) low-noise amplifier (LNA), operating in the 3–5 GHz range, by employing current reuse technique. This proposed CG LNA utilizes a common source (CS) amplifier as the g_m-boosting stage and the bias current is shared between the g_m-boosting stage and the CG amplifying stage. The LNA circuit also utilizes the short channel conductance g_ds in conjunction with an LC T-network to further reduce the noise figure (NF). The proposed LNA architecture has been fabricated using the 130 nm IBM CMOS process. The LNA achieved input return loss (S₁₁) of −8 to −10 dB, and, output return loss (S₂₂) of −12 to −14 dB, respectively. The LNA exhibits almost flat forward voltage gain (S₂₁) of 13 dB, and reverse isolation (S₁₂) of −62 to −49 dB, with a NF ranging between 3.8 and 4.6 dB. The measurements indicate an input-referred third order intercept point (IIP3) of −6.1 dBm and an input-referred 1-dB compression point (ICP_1dB) of −15.4 dBm. The complete chip draws 4 mW of DC power from a 1.2 V supply.     

New fully-differential amplifier-less pipelined ADC with wide power scalability and ERBW

A 24 GHz power amplifier for direct-conversion transceiver using standard 0.18 μm CMOS technology is reported. The three-stage power amplifier comprises two cascaded cascode stages for high power gain, followed by a common-source stage for high power linearity. To increase the saturated output power (P_sat) and power-added efficiency (PAE), the output stage adopts a Wilkinson-power-divider- and combiner-based two-way power dividing and combining architecture. The power amplifier consumes 163.8 mW and achieves power gain (S₂₁) of 22.8 dB at 24 GHz. The corresponding 3-dB bandwidth of S₂₁ is 4.2 GHz, from 22.7 to 26.9 GHz. At 24 GHz, the power amplifier achieves P_sat of 15.9 dBm and maximum PAE of 14.6 %, an excellent result for a 24 GHz CMOS power amplifier. In addition, the measured output 1-dB compression point (OP_1dB) is 7 dBm at 24 GHz. These results demonstrate the proposed power amplifier architecture is very promising for 24 GHz short-range communication system applications.     

Design and performance analysis of low power LNA with variable gain current reuse technique

This paper presents a CMOS low power Variable Gain Low Noise Amplifier for 26–34 GHz in 45 nm process technology, which composes of cascaded complimentary common gate (CCG) stage and digital current steering amplifier. First stage is CCG stage, which helps in achieving the low power consumption and less area. Second stage is variable gain amplifier, uses current reuse technique as well as g_m-boost technique and has constant dc current to make the input impedance stable. Source degeneration technique cancel out MOS parasitic capacitance help in achieving linearity. Simulated maximum peak gain is 13.139 dB at 30.57 GHz and lowest peak gain is 7.75 dB at 26 GHz i.e. approximately flat over the entire band. Lowest NF is 3.08 dB at 32.6 GHz. Process corner simulation has been done for all four corners (S–S, S–F, F–S, F–F) showing robustness of LNA. Input return loss has value less than ? 9.58 dB while output return loss has less than ? 2.6 dB showing good matching; power consumption is 16 mW for dc current of 16 mA at 1 V. MOS active chip area is 76.727 µm².

     

A resistive-feedback LNA in 65 nm CMOS with a gate inductor for bandwidth extension

In order to get a wideband and flat gain, a resistive-feedback LNA using a gate inductor to extend bandwidth is proposed in this paper. This LNA is based on an improved resistive-feedback topology with a source follower feedback to match input. A relative small inductor is connected in series to transistor׳s gate, which boosts transistor׳s effective transconductance, compensates gain loss and then leads the proposed LNA with a flat gain and wider bandwidth. Moreover, the LNA׳s noise is partially inhibited by the gate inductor, especially at high frequency. Realized in standard 65-nm CMOS process, this LNA dissipates 12 mW from a 1.5-V supply while its core area is 0.076 mm². Across 0.4–10.6 GHz band, the proposed LNA provides 9.5±0.9 dB power gain (S₂₁), better than −11-dB input matching, 3.5-dB minimum noise figure, and higher than −17.2-dBm P_1 dB.