Over 1000 V/30 mA operation GaN-on-Si MOSFETs fabricated on Si substrates

We demonstrated the operation of GaN-on-Si metal-oxide-semiconductor field effect transistors (MOSFETs) for power electronics components. The interface states at SiO₂/GaN were successfully improved by annealing at 800 °C for 30 min in N₂ ambient. The interface state density was less than 1 × 10¹¹ cm^-2 eV⁻¹ at E_c − 0.4 eV. The n⁺ contact layers as the source and drain regions as well as the reduced surface field (RESURF) zone were formed using a Si ion implantation technique with the activation annealing at 1200 °C for 10 s in rapid thermal annealing (RTA). As a result, we achieved an over 1000 V and 30 mA operation on GaN-on-Si MOSFETs. The threshold voltage was +2.6 V. It was found that the breakdown voltage depended upon the RESURF length and nitride based epi-layer thickness. In addition, we discussed the comparison of each performance of GaN-on-Si with -sapphire devices.     

Low threading dislocation density Ge deposited on Si (1 0 0) using RPCVD

Epitaxial Ge layer growth of low threading dislocation density (TDD) and low surface roughness on Si (1 0 0) surface is investigated using a single wafer reduced pressure chemical vapor deposition (RPCVD) system. Thin seed Ge layer is deposited at 300 °C at first to form two-dimensional Ge surface followed by thick Ge growth at 550 °C. Root mean square of roughness (RMS) of ∼0.45 nm is achieved. As-deposited Ge layers show high TDD of e.g. ∼4 × 10⁸ cm⁻² for a 4.7 μm thick Ge layer thickness. The TDD is decreasing with increasing Ge thickness. By applying a postannealing process at 800 °C, the TDD is decreased by one order of magnitude. By introducing several cycle of annealing during the Ge growth interrupting the Ge deposition, TDD as low as ∼7 × 10⁵ cm⁻² is achieved for 4.7 μm Ge thick layer. Surface roughness of the Ge sample with the cyclic annealing process is in the same level as without annealing process (RMS of ∼0.44 nm). The Ge layers are tensile strained as a result of a higher thermal expansion coefficient of Ge compared to Si in the cooling process down to room temperature. Enhanced Si diffusion was observed for annealed Ge samples. Direct band-to-band luminescence of the Ge layer grown on Si is demonstrated.     

Au and non-Au based rare earth metal-silicide ohmic contacts to p-InGaAs

The aim of this study is to improve the electrical properties of ohmic contacts that plays crucial role on the performance of optoelectronic devices such as laser diodes (LDs), light emitting diodes (LEDs) and photodetectors (PDs). The conventional (Pd/Ir/Au, Ti/Pt/Au and Pt/Ti/Pt/Au), Au and non-Au based rare earth metal-silicide ohmic contacts (Gd/Si/Ti/Au, Gd/Si/Pt/Au and Gd/Si/Pt) to p-InGaAs were investigated and compared each other. To calculate the specific contact resistivities the Transmission Line Model (TLM) was used. Minimum specific contact resistivity of the conventional contacts was found as 0.111 × 10⁻⁶ Ω cm² for Pt/Ti/Pt/Au contact at 400 °C annealing temperature. For the rare earth metal-silicide ohmic contacts, the non-Au based Gd/Si/Pt has the minimum value of 4.410 × 10⁻⁶ Ω cm² at 300 °C annealing temperature. As a result, non-Au based Gd/Si/Pt contact shows the best ohmic contact behavior at a relatively low annealing temperature among the rare earth metal-silicide ohmic contacts. Although the Au based conventional ohmic contacts are thermally stable and have lower noise in electronic circuits, by using the non-Au based rare earth metal-silicide ohmic contacts may overcome the problems of Au-based ohmic contacts such as higher cost, poorer reliability, weaker thermal stability, and the device degradation due to relatively higher alloying temperatures. To the best of our knowledge, the Au and non-Au based rare earth metal-silicide (GdSi_x) ohmic contacts to p-InGaAs have been proposed for the first time.     

Effect of rapid thermal annealing on pentacene-based thin-film transistors

The bottom contact pentacene-based thin-film transistor is fabricated, and it is treated by rapid thermal annealing (RTA) with the annealed temperature up to 240 °C for 2 min in the vacuum of 1.3 × 10⁻² torr. The morphology and structure for the pentacene films of OTFTs were examined by scanning electron microscopy and X-ray diffraction technique. The thin-film phase and a very small fraction of single-crystal phase were found in the as-deposited pentacene films. While the annealing temperature increases to 60 °C, the pentacene molecular ordering was significantly improved though the grain size only slightly increased. The device annealed at temperature of 120 °C has optimal electrical properties, being consistent with the experimental results of XRD. The post-annealing treatment results in the enhancement of field-effect mobility in pentacene-based thin-film transistors. The field-effect mobility increases from 0.243 cm²/V s to 0.62 cm²/V s. Besides, the threshold voltage of device shifts from −7 V to −3.88 V and the on/off current ratio increases from 4.0 × 10³ to 8.7 × 10³.     

Fabrication of high-Ge-fraction strained Si1−xGex/Si hole resonant tunneling diode using low-temperature Si2H6 reaction for nanometer-order ultrathin Si barriers

Low-temperature Si barrier growth with atomically flat heterointerfaces was investigated in order to improve negative differential conductance (NDC) characteristics of high-Ge-fraction strained Si_1−xGe_x/Si hole resonant tunneling diode with nanometer-order thick strained Si_1−xGe_x and unstrained Si layers. Especially to suppress the roughness generation at heterointerfaces for higher Ge fraction, Si barriers were deposited using Si₂H₆ reaction at a lower temperature of 400 °C instead of SiH₄ reaction at 500 °C after the Si_0.42Ge_0.58 growth. NDC characteristics show that difference between peak and valley currents is effectively enhanced at 11-295 K by using Si₂H₆ at 400 °C, compared with that using SiH₄ at 500 °C. Non-thermal leakage current at lower temperatures below 100 K tends to increase with decrease of Si barrier thickness. Additionally, thermionic-emission dominant characteristics at higher temperatures above 100 K suggests a possibility that introduction of larger barrier height (i.e. larger band discontinuity) enhances the NDC at room temperature by suppression of thermionic-emission current.     

Characterization of impact of process options in Germanium-On-Insulator (GeOI) high-k & metal gate pMOSFETs by low-frequency noise

The impact of technological processes on Germanium-On-Insulator (GeOI) noise performance is studied. We present an experimental investigation of low-frequency noise (LFN) measurements carried out on (GeOI) PMOS transistors with different process splits. The front gate is composed of a SiO₂/HfO₂ stack with a TiN metal gate electrode. The result is an aggressively reduced equivalent oxide thickness (EOT) of 1.8 nm. The buried oxide is used as a back gate for experimental purposes. Front and back gate interfaces are characterized and the slow oxide trap densities are extracted. The obtained values are comprised between 5 × 10¹⁷ and 8 × 10¹⁸ cm⁻³eV⁻¹. No correlation between front interface trap density and front interface mobility is observed. We underline a strong correlation between rear interface trap density and rear interface mobility degradation. The impact of Ge film thickness is equally studied. For thin films, the measured drain-current noise spectral density shows that LFN can be described by the carrier fluctuation model from weak to strong inversion. For thicker film devices, in weak inversion the LFN can be described by the mobility fluctuation model and in strong inversion the LFN is described by the carrier fluctuation model. The α_H parameter for these devices is 1.2 × 10⁻³. These results are significant for the future development of GeOI technologies.     

Compact model for long-channel cylindrical surrounding-gate MOSFETs valid from low to high doping concentrations

This paper presents a compact model for the electrostatic potentials and the current characteristics of doped long-channel cylindrical surrounding-gate (SRG) MOSFETs. An analytical expression of the potentials is derived as a function of doping concentration. Then, the mobile charge density is calculated using the analytical expressions of the surface potential at the surface and the difference of potentials between the surface and the center of the silicon doped layer. Using the expression obtained for the mobile charge, a drain current expression is derived. Comparisons of the modeled expressions with the simulated characteristics obtained from the 3D ATLAS device simulator for the transfer characteristics, as well for the output characteristics, show good agreement within the practical range of gate and drain voltages and for doping concentrations ranging from 10¹⁶ cm⁻³ to 5 × 10¹⁸ cm⁻³.     

Activation analytical investigation of contamination and cross-contamination in ion implantation

In silicon layers, implanted at 100–150 keV with P⁺, As⁺ and Ar⁺ ions, considerable Fe, Cr, Ni, Co and Cu were detected by means of neutron activation analysis. With the elements of the Fe group, concentrations up to 5.10¹⁴cm⁻² were obtained, whereby the relationship of these elements to each other corresponds to the composition of the stainless steel apertures used. The contamination of the layers is dose dependent. In accordance with the sputter rates, As⁺ ion implanted layers are more contaminated than those implanted by P⁺ or Ar⁺ ions. Additionally, the implanting process introduces, besides the contamination with heavy metals, dopants from the previous implantation. This so-called cross-contamination amounted to approx. 0.3 % of the implanted ion dose. Essential parts of this work were presented at the symposium on “Solid State Device Technology” Munster, 1977     

Fabrication of Ge-MOS capacitors with high quality interface by ultra-thin SiO2/GeO2 bi-layer passivation combined with the subsequent SiO2-depositions using magnetron sputtering

Ge-MOS capacitors were fabricated by a novel method of ultra-thin SiO₂/GeO₂ bi-layer passivation (BLP) for Ge surface combined with the subsequent SiO₂-depositions using magnetron sputtering. For the Ge-MOS capacitors fabricated by BLP with O₂, to decrease oxygen content in the subsequent SiO₂ deposition is helpful for improving interface quality. By optimizing process parameters of the Ge surface thermal cleaning, the BLP, and the subsequent SiO₂ deposition, interface states density of 4 × 10¹¹ cm⁻² eV⁻¹ at around mid-gap was achieved, which is approximately three times smaller than that of non-passavited Ge-MOS capacitors. On the contrary, for the Ge-MOS capacitors fabricated by BLP without O₂, interface quality could be improved by an increase in oxygen contents during the subsequent SiO₂ deposition, but the interface quality was worse compared with BLP with O₂.     

Doping and processing epitaxial GexSi1−x films on Si(100) by ion implantation for Si-based heterojunction devices applications

The question of whether one can effectively dope or process epitaxial Si(100)/GeSi heterostructures by ion implantation for the fabrication of Si-based heterojunction devices is experimentally investigated. Results that cover several differention species (B, C, Si, P, Ge, As, BF₂, and Sb), doses (10¹³ to 10¹⁶/cm²), implantation temperatures (room temperature to 150°C), as well as annealing techniques (steady-state and rapid thermal annealing) are included in this minireview, and the data are compared with those available in the literature whenever possible. Implantation-induced damage and strain and their annealing behavior for both strained and relaxed GeSi are measured and contrasted with those in Si and Ge. The damage and strain generated in pseudomorphic GeSi by room-temperature implantation are considerably higher than the values interpolated from those of Si and Ge. Implantation at slightly elevated substrate temperatures (e.g., 100°C) can very effectively suppress the implantation-induced damage and strain in GeSi. The fractions of electrically active dopants in both Si and GeSi are measured and compared for several doses and under various annealing conditions. Solid-phase epitaxial regrowth of GeSi amorphized by implantation has also been studied and compared with regrowth in Si and Ge. For the case of metastable epi-GeSi amorphized by implantation, the pseudomorphic strain in the regrown GeSi is always lost and the layer contains a high density of defects, which is very different from the clean regrowth of Si(100). Solid-phase epitaxy, however, facilitates the activation of dopants in both GeSi and Si, irrespective of the annealing techniques used. For metastable GeSi films that are not amorphized by implantation, rapid thermal annealing is shown to outperform steady-state annealing for the preservation of pseudomorphic strain and the activation of dopants. In general, defects generated by ion implantation can enhance the strain relaxation process of strained GeSi during post-implantation annealing. The processing window that is optimized for ion-implanted Si, therefore, has to be modified considerably for ion-implanted GeSi. However, with these modifications, the mature ion implantation technology can be used to effectively dope and process Si/GeSi heterostructures for device applications. Possible impacts of implantation-induced damage on the reliability of Si/GeSi heterojunction devices are briefly discussed.     

A 0.18 μm CMOS linear-in-dB AGC post-amplifier for optical communications

This paper presents a fully integrated 10GBase-LX4 Ethernet receiver front-end automatic gain control amplifier realized in a 0.18 μm CMOS process. Based on a very compact and reliable inductorless design, the proposed differential post-amplifier, comprises three main digitally programmable gain stages, a DC offset cancellation network and an automatic gain feedback control loop. Experimental results demonstrate a −3 dB cut-off frequency above 2.3 GHz over a −3 to 33 dB linear-in-dB controlled gain range with a sensitivity of 2.0 mV_p-p with a BER of 10⁻¹² at 2.5 Gb/s. For the aforementioned standard, 3.125 Gb/s, an input dynamic range above 50 dB is achieved, from 2.5 mV_p-p to 800 mV_p-p, indicating a BER of 10⁻¹². The chip core area is 0.3 × 0.3 mm² and it consumes 58 mW with a single supply voltage of 1.8 V.     

Fully depleted silicon on insulator MOSFETs on (1 1 0) surface for hybrid orientation technologies

Effective memory performance of the nonvolatile memory/thin film transistor (NVM/TFT) devices needs good TFT characteristics. The reduction in leakage current of the TFT devices was accomplished with the gate offset (GOF) structure. A simplified fabrication process for the GOF NVM is introduced in this study using the insulator over-etching approach. Nonvolatile memory devices on glass using SiO₂/SiO_x/SiO_xN_y stack with an offset length of 0, 0.2, 0.4, and 0.6 μm were investigated. The highly selective etching process and the short offset length help to avoid the problem of the gate aluminum collapsing on the source/drain electrodes. The TFT characteristics of the GOF structures displayed the remarkable improvement in leakage from 1.1 × 10⁻¹¹ A, for the TFT without an offset region, to the low OFF current of 1.34 × 10⁻¹² A for the device with a 0.6 μm offset length. The longer offset length gave the lowest OFF current. The degradation in transconductance and the threshold voltage was negligible with the g_m values of about 3 × 10⁻⁶ S and ΔV_th of about 0.2 V, respectively. The switching characteristics remained similar for all the devices. Additionally, the GOF structures slightly enhanced the retention characteristics. The memory window of the NVM without the offset after a retention time of 10,000 s was 58%, lower than the over 69% of the GOF devices. Therefore, the application of the GOF structure to reduce the leakage of the NVM/TFT proved to be effective.     

Transient electroluminescence determination of carrier mobility and charge trapping effects in heavily doped phosphorescent organic light-emitting diodes

Transient electroluminescence (EL) was used to measure the delay between the excitation pulse and onset of emission in OLEDs based on phosphorescent bis[3,5-bis(2-pyridyl)-1,2,4-triazolato] platinum(ΙΙ) doped into 4,4′-bis(carbazol-9-yl) triphenylamine (CBP), from which an electron mobility of 3.2 × 10⁻⁶ cm²/V s was approximated. Delayed recombination was observed after the drive pulse had been removed and based on its dependence on frequency and duty cycle, ascribed to trapping and de-trapping processes associated with disorder-induced carrier localization at the interface between the emissive layer and electron blocker. The data suggests that the exciton recombination zone is at, or close to the interface between the emissive layer and electron blocker. Despite the charge trapping effects, a peak power efficiency of 24 lm/W and peak external quantum efficiency of 10.64% were obtained. Mechanisms for the electroluminescence and delayed recombination are proposed.     

X-ray microdiffraction investigation of crystallinity and strain relaxation in Ge thin lines selectively grown on Si(0 0 1) substrates

We used X-ray microdiffraction (XRMD) to investigate the crystallinity and strain relaxation of Ge thin lines with widths of 100, 200, 500 and 1000 nm selectively grown on Si(0 0 1) substrates using a patterned SiO₂ mask by chemical vapor deposition. The variations of the strain relaxation in the line and width directions were also investigated in Ge thin lines with a width of 100 nm. After growth, crystal domains with very small tilt angles were detected in Ge lines with all four line widths. The tilt angle range was larger in thinner Ge lines. After annealing at 700 °C, the formation of a single, large domain with a specific tilt angle was detected by XRMD for Ge thin lines with widths of 100 and 200 nm. These experimental results reflect the effects of SiO₂ side walls around the Ge thin lines on crystallinity and strain relaxation of Ge.     

Low temperature dopant activation of BF2 implanted silicon

Boron activation and carrier mobility were measured after low temperature furnace heat treatments, in silicon layers implanted with BF ₂ ⁺ ions at 60 keV and at fluence in the 1 − 5 × 10¹⁵ ions cm⁻² range. These quantities were correlated with boron and fluorine chemical depth profiles obtained with secondary ion mass spectrometry (SIMS), and with the lattice defects revealed by transmission electron microscopy (TEM). High dopant activation, well above the extrapolated boron solid solubility, was found for all the fluences investigated after a thermal treatment of 20 min at 600‡ C. In the high fluence implanted samples, the solid phase epitaxial regrowth of the amorphous layer induces a severe fluorine redistribution which causes the formation of a defective band at the sample surface containing microtwins and small precipitates; a decrease in both the activated dopant concentration and carrier mobility was found in this region. The comparison with dopant activation data obtained in samples diffused at higher temperature (from 900 to 1000‡ C) shows that twins are electrically active only when they are decorated by isolated impurities and/or in presence of very small precipitates.     

High-density formation of Ge quantum dots on SiO2

We formed high-density Ge quantum dots (QDs) on an ultrathin SiO₂ layer by controlling the early stages of low-pressure chemical vapor deposition (LPCVD) with a germane gas (GeH₄) assisted by a remote plasma of pure H₂. We then characterized the electronic charged states of the QDs by an AFM/Kelvin probe technique. The formation of single crystalline Ge-QDs with an areal dot density of ∼2.0 × 10¹¹ cm⁻² was confirmed after examining the surface morphology and lattice by atomic force microscopy and transmission electron microscopy, respectively. It has been suggested that an increase in the flux of deposition precursors due to efficient decomposition of GeH₄ by a supply of hydrogen radicals and the dehydration reaction of surface OH bonds plays a role in nucleation of Ge-QDs on SiO₂. Surface passivation with hydrogen may also promote the surface migration of deposition precursors during LPCVD. The surface potential of the dots changed in a stepwise manner with respect to the tip bias due to multistep electron injection into and extraction from the Ge-QDs.     

Strain relaxation in SiGe due to process induced defects and their subsequent annealing behavior

Ion implantation and reactive ion etching are known to create defects in silicon which get cured during subsequent annealing operations. In this paper we have reported the annealing behavior of phosphorus implanted into strained SiGe layer at room temperature. The implantation was performed at 155 KeV with a dose of 1×10¹⁴/cm². Post implantation annealing was performed at 600, 700, 800 and 900°C for 10 s in a rapid thermal process furnace. Annealing behavior of defects generated as a consequence of dry etching is also reported. RTP annealing on reactive ion etching (RIE) etched samples were performed at 650, 700, 750 and 800 °C. I–V, C–V and DLTS measurements hint towards the presence of permanent dislocation loops created as a consequence of RIE and implantation causing strain relaxation.     

DEEP LEVEL DEFECTS IN SI-IMPLANTED LEC UNDOPED Si-GaAs

The residual electrically active defects in(4×10~(12)cm~(-2)(30KeV)+5×10~(12)cm~(-2)(130KeV))si-implanted LEC undoped si-GaAs activated by two-step rapid thermal annealing(RTA)LABELED AS 970℃(9S)+750℃(12S)have been investigated with deep level transient spec-troscopy(DLTS).Two electron traps ET_1(E_c-0.53eV,σ_n=2.3×10~(-16)cm~2)and ET_2(E_c-0.81eV,σ_n=9.7×10(-13)cm~2)are detected.Furthermore,the noticeable variations of trap's con-centration and energy level in the forbidden gap with the depth profile of defects induced by ion im-plantation and RTA process have also been observed.The[As_i·V_(As)·As_(Ga)]and[V_(As)·As_i·V_(Ga)·As_(Ga)]are proposed to be the possible atomic configurations of ET_1 and ET_2,respectively to explaintheir RTA behaviors.     

Aluminum and boron ion implantations into 6H-SiC epilayers

Aluminum and boron ion implantations into n-type 6H-SiC epilayers have been systematically investigated. Redistribution of implanted atoms during high-temperature annealing at 1500°C is negligibly small. The critical implant dose for amorphization is estimated to be 1 × 10¹⁵ cm⁻² for Al⁺ implantation and 5 × 10¹⁵ cm^-2 for B⁺ implantation. By Al⁺ implantation followed with 1500°C-annealing, p-type layers with a sheet resistance of 22 kΩ/^— can be obtained. B⁺ implantation results in the formation of highly resistive layers, which may be attributed to the deep B acceptor level.     

Strain relaxation in silicon ion molecular beam epitaxy on silicon (001) substrates during aging

Silicon strained epitaxial films were grown on Si (001) substrates by low energy ion beam assisted molecular beam epitaxy. Films grown in the range of 450– 550°C with concurrent Ar⁺ ion bombardment (100 eV) were characterized using x-ray diffraction and transmission electron microscopy and found to be disloca-tion free and ununiformly strained. During aging, the strained layers stay stable until 500°C. Relaxation of most of the strain occurred at temperatures of 500-650°C. At higher aging temperatures, the strained layers relaxed by the formation of dense dislocation structures.